Test-oriented Resilient Requirements Engineering (ToRRE): extending model-based effect chain analysis to verification objectives
I. Gräßler, M. Ebel, in: Proceedings of the Design Society, Cambridge University Press (CUP), 2025, pp. 3031–3040.

Method for systematic creation of test scenarios for early customer involvement
I. Gräßler, M. Ebel, J. Pottebaum, in: Procedia CIRP, Elsevier BV, 2025, pp. 213–218.

Human vs. Algorithmic Auditors: The Impact of Entity Type and Ambiguity on Human Dishonesty
M. Protte, B.M. Djawadi, Frontiers in Behavioral Economics 4 (2025) 1645749.

Model-based planning of test cases and test scenarios to support engineering of Cyber-Physical Systems
I. Gräßler, M. Ebel, J. Pottebaum, in: 2024 IEEE International Symposium on Systems Engineering (ISSE), IEEE, 2024.

Hardware Trojans in Reconfigurable Computing
Q.A. Ahmed, Hardware Trojans in Reconfigurable Computing,  Paderborn University, Paderborn, Germany, Paderborn, 2022.

Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware
T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware, Paderborn University, Paderborn, 2021.

Software/Hardware Co-Verification for Custom Instruction Set Processors
M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, T. Wiersema, IEEE Access (2021).

Proof-carrying Approximate Circuits
L.M. Witschen, T. Wiersema, M. Platzner, IEEE Transactions On Very Large Scale Integration Systems 28 (2020) 2084–2088.

Jump Search: A Fast Technique for the Synthesis of Approximate Circuits
L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, Fourth Workshop on Approximate Computing (AxC 2019) (n.d.).

Enforcing IP Core Connection Properties with Verifiable Security Monitors
F.P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable Security Monitors, Universität Paderborn, 2018.

An Assisted Single Source Verification Metric Model Code Generation Methodology
C. Kuznik, W. Müller, G.B. Defo, in: San Francisco, USA, 2014.

Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU
B. Koppelmann, B. Messidat, M. Becker, W. Müller, J.C. Scheytt, in: Proceedings of the Design and Verification Conference Europe (DVCON Europe), München, 2014.

Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU
B. Koppelmann, B. Messidat, C. Kuznik, W. Müller, M. Becker, J.C. Scheytt, in: Proceedings of the Design and Verification Conference Europe (DVCON Europe), München, 2014.

EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks
M. Woehrle, C. Plessl, R. Lim, J. Beutel, L. Thiele, in: IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC), IEEE Computer Society, Los Alamitos, CA, USA, 2008, pp. 201–208.

Automated Wireless Sensor Network Testing
J. Beutel, M. Dyer, R. Lim, C. Plessl, M. Woehrle, M. Yuecel, L. Thiele, in: Proc. Int. Conf. Networked Sensing Systems (INSS), IEEE, Piscataway, NJ, USA, 2007, pp. 303–303.

Past- and Future-Oriented Time-Bound Temporal Properties with OCL
S. Flake, W. Müller, in: Proceedings of SEFM´04, IEEE, Beijing, China, 2004.

The Formal Execution Semantics of SpecC
W. Müller, R. Dömer, A. Gerstlauer, in: Proceedings of the ISS, Nagoya, Japan, 2002.

Specification of Real-Time Properties for UML Models
S. Flake, W. Müller, in: Proceedings of HICSS-35, Big Island, HI, USA , 2002.

The Simulation Semantics of SystemC
W. Müller, J. Ruf, D.W. Hoffmann, J. Gerlach, T. Kropf, W. Rosenstiehl, in: Proceedings of the Design, Automation, and Test in Europe (DATE’01), IEEE, Munich, Germany , 2001.

A Formal Definition of an Abstract VHDL Simulator by EA-Machines
E. Börger, U. Glässer, W. Müller, in: C. Delgado Kloos, P.T. Breuer (Eds.), Semantics of VHDL, Kluwer Academic Publishers, Dordrecht, 1995, pp. 107–139.