StencilStream: A SYCL-based Stencil Simulation Framework Targeting FPGAs
J.-O. Opdenhövel, C. Alt, C. Plessl, T. Kenter, in: 2024 34th International Conference on Field-Programmable Logic and Applications (FPL), IEEE, 2024.

Enabling Performance Portability for Shallow Water Equations on CPUs, GPUs, and FPGAs with SYCL
M. Büttner, C. Alt, T. Kenter, H. Köstler, C. Plessl, V. Aizinger, in: Proceedings of the Platform for Advanced Scientific Computing Conference (PASC), ACM, 2024.

Performance analysis of the free surface lattice Boltzmann implementation in waLBerla
J. Plewinski, C. Alt, H. Köstler, U. Rüde, in: PAMM, Wiley, 2024.

A continuous benchmarking infrastructure for high-performance computing applications
C. Alt, M. Lanser, J. Plewinski, A. Janki, A. Klawonn, H. Köstler, M. Selzer, U. Rüde, International Journal of Parallel, Emergent and Distributed Systems 39 (2024) 501–523.

Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation Pipeline
C. Alt, T. Kenter, S. Faghih-Naini, J. Faj, J.-O. Opdenhövel, C. Plessl, V. Aizinger, J. Hönig, H. Köstler, in: Lecture Notes in Computer Science, Springer Nature Switzerland, Cham, 2023.