Luchterhandt, Lars, Tom Nellius, Robert Beck, Rainer Dömer, Pascal Kneuper, Wolfgang Müller, and Babak Sadiye. “Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells.” In MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“. VDE Verlag, 2024.

Palomero Bernardo, Paul, Patrick Schmid, Oliver Bringmann, Mohammed Iftekhar, Babak Sadiye, Wolfgang Müller, Andreas Koch, et al. “A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing.” In DATE 24 - Design Automation and Test in Europe, 2024.

Luchterhandt, Lars, Tom Nellius, Robert Beck, Rainer Dömer, Pascal Kneuper, Wolfgang Müller, and Babak Sadiye. “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture.” In MBMV 2023 - 26. Workshop "Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg. VDE Verlag, 2023.

Ecker, Wolfgang, Milos Krstic, Markus Ulbricht, Andreas Mauderer, Eyck Jentzsch, Andreas Koch, Bastian Koppelmann, et al. “Scale4Edge – Scaling RISC-V for Edge Applications.” In RISC-V Summit Europe 2023, Barcelona, Spain, June 2023., 2023.

Müller, Wolfgang, Markus Ulbricht, Lu Li, and Milos Krstic. “Der TETRISC SoC - Ein Resilientes Quad-Core System Auf Pulpissimo-Basis.” In 5. ITG / GMM / GI -Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen , 2023.

Iftekhar, Mohammed, Harshan Gowda, Pascal Kneuper, Babak Sadiye, Wolfgang Müller, and Christoph Scheytt. “A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 Nm FD-SOI CMOS Technology.”https://doi.org/10.1109/BCICTS54660.2023.10310954__In 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2023.https://doi.org/10.1109/BCICTS54660.2023.10310954 .

Ecker, Wolfgang, Peer Adelt, Wolfgang Müller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, et al. “The Scale4Edge RISC-V Ecosystem.” In In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022), 2022.

Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” In MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop. Munich, DE: VDE, 2021.

Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “QEMU zur Simulation von Worst-Case-Ausfuhrungszeiten.” In MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop. Munich, DE: VDE, 2021.

Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” In Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021), 2021.

Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures.” In MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop. Stuttgart, DE, 2020.

Koppelmann, Bastian, Peer Adelt, Wolfgang Müller, and Christoph Scheytt. “RISC-V Extensions for Bit Manipulation Instructions.”https://doi.org/10.1109/PATMOS.2019.8862170__In 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS). Rhodos, Griechenland, 2019.https://doi.org/10.1109/PATMOS.2019.8862170 .

Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “Analyse Sicherheitskritischer Software Fur RISC-V Prozessoren.” In MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019). Kaiserslautern, DE, 2019.

Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Christoph Scheytt, and Benedikt Driessen. “QEMU for Dynamic Memory Analysis of Security Sensitive Software.” In  2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019, 32–34. Florence, Italy, 2019.

Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “QEMU Support for RISC-V: Current State and Future Releases.” 2nd International Workshop on RISC-V Research Activities (Presentation) (2019).

Bringmann, Oliver, Wolfgang Ecker, Wolfgang Müller, and Daniel Müller-Gridschneder, eds. Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT. Florence, Italy, 2019.

Adelt, Peer, Bastian Koppelmann, and Wolfgang Müller. “Current and Future RISC-V Activities for Virtual Prototyping and Chip Design.” International Workshop on RISC-V Research Activities Presentation (2018).

Wu, Liang, Mohammad Khizer Hussain, Saed Abughannam, Wolfgang Müller, Christoph Scheytt, and Wolfgang Ecker. “Analog Fault Simulation Automation at Schematic Level with Random Sampling Techniques.”https://doi.org/10.1109/DTIS.2018.8368549__In 2018 13th International Conference on Design &; Technology of Integrated Systems In Nanoscale Era (DTIS)) . Italy/Taormina: IEEE, 2018.https://doi.org/10.1109/DTIS.2018.8368549 .

Bringmann, Oliver, Wolfgang Ecker, Wolfgang Müller, and Daniel Müller-Gridschneder, eds. Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT. Dresden, Germany, 2018.

Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Daniel Mueller-Gritschneder, Bernd Kleinjohann, and Christoph Scheytt. “Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen.”https://doi.org/10.17619/UNIPB/1-93__In Tagungsband des Wissenschaftsforums Intelligente Technische Systeme. Germany, Paderborn: Verlagsschriftenreihe des Heinz Nixdorf Instituts, 2017.https://doi.org/10.17619/UNIPB/1-93 .