L. Luchterhandt et al., “Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells,” presented at the MBMV 2023 - 26. Workshop, Freiburg, , Germany,  Freiburg, 2024.

P. Palomero Bernardo et al., “A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing,” Valencia, Spain, 2024.

L. Luchterhandt et al., “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture,” presented at the MBMV 2023, Freiburg, Freiburg, 2023.

W. Ecker et al., “Scale4Edge – Scaling RISC-V for Edge Applications,” presented at the RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.,  Barcelona, Spain, 2023.

W. Müller, M. Ulbricht, L. Li, and M. Krstic, “Der TETRISC SoC - Ein resilientes Quad-Core System auf Pulpissimo-Basis,” presented at the 5. ITG / GMM / GI -Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen , Erfurt. Germany, 2023.

M. Iftekhar, H. Gowda, P. Kneuper, B. Sadiye, W. Müller, and C. Scheytt, “A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology,”10.1109/BCICTS54660.2023.10310954__presented at the 2023 IEEE BiCMOS und Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), Monterey, CA, USA, 2023, doi:10.1109/BCICTS54660.2023.10310954 .

W. Ecker et al., “The Scale4Edge RISC-V Ecosystem,” 2022.

P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules,” 2021.

P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “QEMU zur Simulation von Worst-Case-Ausfuhrungszeiten,” 2021.

P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules,” 2021.

P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures,” 2020.

B. Koppelmann, P. Adelt, W. Müller, and C. Scheytt, “RISC-V Extensions for Bit Manipulation Instructions,”10.1109/PATMOS.2019.8862170__2019, doi:10.1109/PATMOS.2019.8862170 .

P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Analyse sicherheitskritischer Software fur RISC-V Prozessoren,” 2019.

P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, and B. Driessen, “QEMU for Dynamic Memory Analysis of Security Sensitive Software,” in  2nd International Workshop on Embedded Software for Industrial IoT in conjunction with DATE 2019, 2019, pp. 32–34.

P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “QEMU Support for RISC-V: Current State and Future Releases,” 2nd International Workshop on RISC-V Research Activities, vol. (Presentation), 2019.

O. Bringmann, W. Ecker, W. Müller, and D. Müller-Gridschneder, Eds., Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT. Florence, Italy, 2019.

P. Adelt, B. Koppelmann, and W. Müller, “Current and Future RISC-V Activities for Virtual Prototyping and Chip Design,” International Workshop on RISC-V Research Activities, vol. Presentation, 2018.

L. Wu, M. K. Hussain, S. Abughannam, W. Müller, C. Scheytt, and W. Ecker, “Analog fault simulation automation at schematic level with random sampling techniques,”10.1109/DTIS.2018.8368549__2018, doi:10.1109/DTIS.2018.8368549 .

O. Bringmann, W. Ecker, W. Müller, and D. Müller-Gridschneder, Eds., Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT. Dresden, Germany, 2018.

P. Adelt, B. Koppelmann, W. Müller, D. Mueller-Gritschneder, B. Kleinjohann, and C. Scheytt, “Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen,”10.17619/UNIPB/1-93__2017, doi:10.17619/UNIPB/1-93 .