Optimizing Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL
M. Meyer, T. Kenter, L. Petrica, K. O’Brien, M. Blott, C. Plessl, ArXiv:2403.18374 (2024).

Noctua 2 Supercomputer
C. Bauer, T. Kenter, M. Lass, L. Mazur, M. Meyer, H. Nitsche, H. Riebler, R. Schade, M. Schwarz, N. Winnwa, A. Wiens, X. Wu, C. Plessl, J. Simon, Journal of Large-Scale Research Facilities 9 (2024).

HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory
A.R. Tareen, M. Meyer, C. Plessl, T. Kenter, in: 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2024.

Compute Centers I: Heterogeneous Execution Environments
T. Hansmeier, T. Kenter, M. Meyer, H. Riebler, M. Platzner, C. Plessl, in: C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, H. Wehrheim (Eds.), On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets, Heinz Nixdorf Institut, Universität Paderborn, Paderborn, 2023, pp. 165–182.

Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks
M. Meyer, T. Kenter, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems (2023).

In-depth FPGA Accelerator Performance Evaluation with Single Node Benchmarks from the HPC Challenge Benchmark Suite for Intel and Xilinx FPGAs using OpenCL
M. Meyer, T. Kenter, C. Plessl, Journal of Parallel and Distributed Computing (2022).

Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks
M. Meyer, in: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021.

Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite
M. Meyer, T. Kenter, C. Plessl, in: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (RC), 2020.