Optimizing Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL
M. Meyer, T. Kenter, L. Petrica, K. O’Brien, M. Blott, C. Plessl, ArXiv:2403.18374 (2024).
LibreCat: /record/53364
arXiv: 2403.18374

Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks
M. Meyer, T. Kenter, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems (2023).
LibreCat: /record/38041
DOI: 10.1145/3576200

Compute Centers I: Heterogeneous Execution Environments
T. Hansmeier, T. Kenter, M. Meyer, H. Riebler, M. Platzner, C. Plessl, in: C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, H. Wehrheim (Eds.), On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets, Heinz Nixdorf Institut, Universität Paderborn, Paderborn, 2023, pp. 165–182.
LibreCat: /record/45893
DOI: 10.5281/zenodo.8068642

In-depth FPGA Accelerator Performance Evaluation with Single Node Benchmarks from the HPC Challenge Benchmark Suite for Intel and Xilinx FPGAs using OpenCL
M. Meyer, T. Kenter, C. Plessl, Journal of Parallel and Distributed Computing (2022).
LibreCat: /record/27364
DOI: 10.1016/j.jpdc.2021.10.007

Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks
M. Meyer, in: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021.
LibreCat: /record/27365
DOI: 10.1145/3468044.3468058

Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite
M. Meyer, T. Kenter, C. Plessl, in: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (RC), 2020.
LibreCat: /record/21632
DOI: 10.1109/h2rc51942.2020.00007