P. Palomero Bernardo et al., “A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing,” Valencia, Spain, 2024.
LibreCat: /record/53579

M. Iftekhar and J. C. Scheytt, “ENHANCED PLL CIRCUIT.” 2023.
LibreCat: /record/48631

M. Iftekhar, H. Gowda, P. Kneuper, B. Sadiye, W. Müller, and C. Scheytt, “A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology,”10.1109/BCICTS54660.2023.10310954__presented at the 2023 IEEE BiCMOS und Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), Monterey, CA, USA, 2023, doi:10.1109/BCICTS54660.2023.10310954 .
LibreCat: /record/48961
DOI: 10.1109/BCICTS54660.2023.10310954

S. Abughannam, S. Kruse, M. Iftekhar, and J. C. Scheytt, “Design and Measurements of a Low-power Low-Date-rate Direct-detection Wireless Receiver with Improved Co-channel Interference Robustness,” 2022.
LibreCat: /record/29770

M. Iftekhar, S. Gudyriev, and J. C. Scheytt, “Reference-less Bang-bang CDR with Enhanced Frequency Acquisition Range Using Static and Modulated Integral Branch Offset Currents,”10.1109/BCICTS50416.2021.9682207__2021, doi:10.1109/BCICTS50416.2021.9682207 .
LibreCat: /record/29213
DOI: 10.1109/BCICTS50416.2021.9682207

M. Iftekhar, S. Gudyriev, and C. Scheytt, “Gbps Bang-Bang CDR for 100G PSM4 with Independently Tunable Proportional and Integral Parameters of the Loop Filter in 0.25 µm Photonic BiCMOS Technology,”10.1109/SIRF46766.2020.9040190__2020, doi:10.1109/SIRF46766.2020.9040190 .
LibreCat: /record/24028
DOI: 10.1109/SIRF46766.2020.9040190