Ecker W, Adelt P, Müller W, et al. The Scale4Edge RISC-V Ecosystem. In: In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022). ; 2022.
LibreCat: /record/29302

Adelt P, Koppelmann B, Müller W, Scheytt C. Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. In: MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop. VDE; 2021.
LibreCat: /record/32125

Adelt P, Koppelmann B, Müller W, Scheytt C. QEMU zur Simulation von Worst-Case-Ausfuhrungszeiten. In: MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop. VDE; 2021.
LibreCat: /record/32132

Adelt P, Koppelmann B, Müller W, Scheytt C. Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. In: Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021). ; 2021.
LibreCat: /record/23992

Adelt P, Koppelmann B, Müller W, Scheytt C. A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures. In: MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop. ; 2020.
LibreCat: /record/24027

Koppelmann B, Adelt P, Müller W, Scheytt C. RISC-V Extensions for Bit Manipulation Instructions. In: 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS). ; 2019. doi:10.1109/PATMOS.2019.8862170
LibreCat: /record/24058
DOI: 10.1109/PATMOS.2019.8862170

Adelt P, Koppelmann B, Müller W, Scheytt C. Analyse sicherheitskritischer Software fur RISC-V Prozessoren. In: MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019). ; 2019.
LibreCat: /record/24060

Adelt P, Koppelmann B, Müller W, Scheytt C, Driessen B. QEMU for Dynamic Memory Analysis of Security Sensitive Software. In:  2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019. ; 2019:32-34.
LibreCat: /record/24061

Adelt P, Koppelmann B, Müller W, Scheytt C. QEMU Support for RISC-V: Current State and Future Releases. 2nd International Workshop on RISC-V Research Activities. 2019;(Presentation).
LibreCat: /record/24063

Adelt P, Koppelmann B, Müller W. Current and Future RISC-V Activities for Virtual Prototyping and Chip Design. International Workshop on RISC-V Research Activities. 2018;Presentation.
LibreCat: /record/24194

Adelt P, Koppelmann B, Müller W, Mueller-Gritschneder D, Kleinjohann B, Scheytt C. Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen. In: Tagungsband des Wissenschaftsforums Intelligente Technische Systeme. Verlagsschriftenreihe des Heinz Nixdorf Instituts; 2017. doi:10.17619/UNIPB/1-93
LibreCat: /record/24220
DOI: 10.17619/UNIPB/1-93

Adelt P, Koppelmann B, Müller W, Kleinjohann B, Scheytt C. ANALISA - A Tool for Static Instruction Set Analysis. In: Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation. ; 2017.
LibreCat: /record/24224

Adelt P, Koppelmann B, Müller W, Kleinjohann B, Scheytt C. An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries. In: 2nd Workshop on Resiliency in Embedded Electronic Systems (REES) . ; 2017:44.
LibreCat: /record/24225

Adelt P, Koppelmann B, Müller W, Becker M, Kleinjohann B, Scheytt C. Fast Dynamic Fault Injection for Virtual Microcontroller Platforms. In: Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC). ; 2016. doi:10.1109/VLSI-SoC.2016.7753545
LibreCat: /record/24264
DOI: 10.1109/VLSI-SoC.2016.7753545

Jatzkowski J, Adelt P, Rettberg A. Hierarchical Scheduling for Plug-and-Produce. In: 3rd International Conference on System-Integrated Intelligence: New Challenges for Product and Production Engineering. Elsevier; 2016:227-234. doi: 10.1016/j.protcy.2016.08.031
LibreCat: /record/24269
DOI:  10.1016/j.protcy.2016.08.031

Adelt P. Analyse von Ausführungszeiten Durch Integration Einer Statischen WCET-Analyse Mit Einer Dynamischen Befehlssatzsimulation Am Beispiel Der TriCore-Architektur. Universität Paderborn, Fakultät EIM; 2015.
LibreCat: /record/24288