Ecker, Wolfgang, Peer Adelt, Wolfgang Müller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, et al. “The Scale4Edge RISC-V Ecosystem.” In In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022), 2022.
LibreCat: /record/29302

Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” In MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop. Munich, DE: VDE, 2021.
LibreCat: /record/32125

Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “QEMU zur Simulation von Worst-Case-Ausfuhrungszeiten.” In MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop. Munich, DE: VDE, 2021.
LibreCat: /record/32132

Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” In Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021), 2021.
LibreCat: /record/23992

Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures.” In MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop. Stuttgart, DE, 2020.
LibreCat: /record/24027

Koppelmann, Bastian, Peer Adelt, Wolfgang Müller, and Christoph Scheytt. “RISC-V Extensions for Bit Manipulation Instructions.”https://doi.org/10.1109/PATMOS.2019.8862170__In 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS). Rhodos, Griechenland, 2019.https://doi.org/10.1109/PATMOS.2019.8862170 .
LibreCat: /record/24058
DOI: 10.1109/PATMOS.2019.8862170

Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “Analyse Sicherheitskritischer Software Fur RISC-V Prozessoren.” In MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019). Kaiserslautern, DE, 2019.
LibreCat: /record/24060

Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Christoph Scheytt, and Benedikt Driessen. “QEMU for Dynamic Memory Analysis of Security Sensitive Software.” In  2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019, 32–34. Florence, Italy, 2019.
LibreCat: /record/24061

Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “QEMU Support for RISC-V: Current State and Future Releases.” 2nd International Workshop on RISC-V Research Activities (Presentation) (2019).
LibreCat: /record/24063

Adelt, Peer, Bastian Koppelmann, and Wolfgang Müller. “Current and Future RISC-V Activities for Virtual Prototyping and Chip Design.” International Workshop on RISC-V Research Activities Presentation (2018).
LibreCat: /record/24194

Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Daniel Mueller-Gritschneder, Bernd Kleinjohann, and Christoph Scheytt. “Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen.”https://doi.org/10.17619/UNIPB/1-93__In Tagungsband des Wissenschaftsforums Intelligente Technische Systeme. Germany, Paderborn: Verlagsschriftenreihe des Heinz Nixdorf Instituts, 2017.https://doi.org/10.17619/UNIPB/1-93 .
LibreCat: /record/24220
DOI: 10.17619/UNIPB/1-93

Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Bernd Kleinjohann, and Christoph Scheytt. “ANALISA - A Tool for Static Instruction Set Analysis.” In Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation. Lausanne, CH, 2017.
LibreCat: /record/24224

Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Bernd Kleinjohann, and Christoph Scheytt. “An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries.” In 2nd Workshop on Resiliency in Embedded Electronic Systems (REES) , 44. Lausanne, Switzerland, 2017.
LibreCat: /record/24225

Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Markus Becker, Bernd Kleinjohann, and Christoph Scheytt. “Fast Dynamic Fault Injection for Virtual Microcontroller Platforms.”https://doi.org/10.1109/VLSI-SoC.2016.7753545__In Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC). Tallin, Estonia, 2016.https://doi.org/10.1109/VLSI-SoC.2016.7753545 .
LibreCat: /record/24264
DOI: 10.1109/VLSI-SoC.2016.7753545

Jatzkowski, Jan, Peer Adelt, and Achim Rettberg. “Hierarchical Scheduling for Plug-and-Produce.”https://doi.org/ 10.1016/j.protcy.2016.08.031__In 3rd International Conference on System-Integrated Intelligence: New Challenges for Product and Production Engineering, 227–34. Paderborn, DE: Elsevier, 2016.https://doi.org/ 10.1016/j.protcy.2016.08.031 .
LibreCat: /record/24269
DOI:  10.1016/j.protcy.2016.08.031

Adelt, Peer. Analyse von Ausführungszeiten Durch Integration Einer Statischen WCET-Analyse Mit Einer Dynamischen Befehlssatzsimulation Am Beispiel Der TriCore-Architektur. Universität Paderborn, Fakultät EIM, 2015.
LibreCat: /record/24288