W. Ecker et al., “The Scale4Edge RISC-V Ecosystem,” 2022.
LibreCat: /record/29302

P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules,” 2021.
LibreCat: /record/32125

P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “QEMU zur Simulation von Worst-Case-Ausfuhrungszeiten,” 2021.
LibreCat: /record/32132

P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules,” 2021.
LibreCat: /record/23992

P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures,” 2020.
LibreCat: /record/24027

B. Koppelmann, P. Adelt, W. Müller, and C. Scheytt, “RISC-V Extensions for Bit Manipulation Instructions,”10.1109/PATMOS.2019.8862170__2019, doi:10.1109/PATMOS.2019.8862170 .
LibreCat: /record/24058
DOI: 10.1109/PATMOS.2019.8862170

P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Analyse sicherheitskritischer Software fur RISC-V Prozessoren,” 2019.
LibreCat: /record/24060

P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, and B. Driessen, “QEMU for Dynamic Memory Analysis of Security Sensitive Software,” in  2nd International Workshop on Embedded Software for Industrial IoT in conjunction with DATE 2019, 2019, pp. 32–34.
LibreCat: /record/24061

P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “QEMU Support for RISC-V: Current State and Future Releases,” 2nd International Workshop on RISC-V Research Activities, vol. (Presentation), 2019.
LibreCat: /record/24063

P. Adelt, B. Koppelmann, and W. Müller, “Current and Future RISC-V Activities for Virtual Prototyping and Chip Design,” International Workshop on RISC-V Research Activities, vol. Presentation, 2018.
LibreCat: /record/24194

P. Adelt, B. Koppelmann, W. Müller, D. Mueller-Gritschneder, B. Kleinjohann, and C. Scheytt, “Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen,”10.17619/UNIPB/1-93__2017, doi:10.17619/UNIPB/1-93 .
LibreCat: /record/24220
DOI: 10.17619/UNIPB/1-93

P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and C. Scheytt, “ANALISA - A Tool for Static Instruction Set Analysis,” 2017.
LibreCat: /record/24224

P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and C. Scheytt, “An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries,” in 2nd Workshop on Resiliency in Embedded Electronic Systems (REES) , 2017, p. 44.
LibreCat: /record/24225

P. Adelt, B. Koppelmann, W. Müller, M. Becker, B. Kleinjohann, and C. Scheytt, “Fast Dynamic Fault Injection for Virtual Microcontroller Platforms,”10.1109/VLSI-SoC.2016.7753545__2016, doi:10.1109/VLSI-SoC.2016.7753545 .
LibreCat: /record/24264
DOI: 10.1109/VLSI-SoC.2016.7753545

J. Jatzkowski, P. Adelt, and A. Rettberg, “Hierarchical Scheduling for Plug-and-Produce,” 10.1016/j.protcy.2016.08.031__in 3rd International Conference on System-integrated Intelligence: New Challenges for Product and Production Engineering, 2016, pp. 227–234, doi: 10.1016/j.protcy.2016.08.031 .
LibreCat: /record/24269
DOI:  10.1016/j.protcy.2016.08.031

P. Adelt, Analyse von Ausführungszeiten durch Integration einer statischen WCET-Analyse mit einer dynamischen Befehlssatzsimulation am Beispiel der TriCore-Architektur. Universität Paderborn, Fakultät EIM, 2015.
LibreCat: /record/24288