Ecker, W., Adelt, P., Müller, W., Heckmann, R., Krstic, M., Herdt, V., Drechsler, R., Angst, G., Wimmer, R., Mauderer, A., Stahl, R., Emrich, K., Mueller-Gritschneder, D., Becker, B., Scholl, P., Jentzsch, E., Schlamelcher, J., Grüttner, K., Bernardo, P. P.,  Kunz, W. (2022). The Scale4Edge RISC-V Ecosystem. In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022).

Adelt, P., Koppelmann, B., Müller, W., &; Scheytt, C. (2021). Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop.

Adelt, P., Koppelmann, B., Müller, W., &; Scheytt, C. (2021). QEMU zur Simulation von Worst-Case-Ausfuhrungszeiten. MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop.

Adelt, P., Koppelmann, B., Müller, W., &; Scheytt, C. (2021). Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021).

Adelt, P., Koppelmann, B., Müller, W., &; Scheytt, C. (2020). A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures. MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop.

Koppelmann, B., Adelt, P., Müller, W., &; Scheytt, C. (2019). RISC-V Extensions for Bit Manipulation Instructions. 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS).https://doi.org/10.1109/PATMOS.2019.8862170 

Adelt, P., Koppelmann, B., Müller, W., &; Scheytt, C. (2019). Analyse sicherheitskritischer Software fur RISC-V Prozessoren. MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019).

Adelt, P., Koppelmann, B., Müller, W., Scheytt, C., &; Driessen, B. (2019). QEMU for Dynamic Memory Analysis of Security Sensitive Software.  2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019, 32–34.

Adelt, P., Koppelmann, B., Müller, W., &; Scheytt, C. (2019). QEMU Support for RISC-V: Current State and Future Releases. 2nd International Workshop on RISC-V Research Activities, (Presentation).

Adelt, P., Koppelmann, B., &; Müller, W. (2018). Current and Future RISC-V Activities for Virtual Prototyping and Chip Design. International Workshop on RISC-V Research Activities, Presentation.

Adelt, P., Koppelmann, B., Müller, W., Mueller-Gritschneder, D., Kleinjohann, B., &; Scheytt, C. (2017). Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen. Tagungsband des Wissenschaftsforums Intelligente Technische Systeme.https://doi.org/10.17619/UNIPB/1-93 

Adelt, P., Koppelmann, B., Müller, W., Kleinjohann, B., &; Scheytt, C. (2017). ANALISA - A Tool for Static Instruction Set Analysis. Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation.

Adelt, P., Koppelmann, B., Müller, W., Kleinjohann, B., &; Scheytt, C. (2017). An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries. 2nd Workshop on Resiliency in Embedded Electronic Systems (REES) , 44.

Adelt, P., Koppelmann, B., Müller, W., Becker, M., Kleinjohann, B., &; Scheytt, C. (2016). Fast Dynamic Fault Injection for Virtual Microcontroller Platforms. Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC).https://doi.org/10.1109/VLSI-SoC.2016.7753545 

Jatzkowski, J., Adelt, P., &; Rettberg, A. (2016). Hierarchical Scheduling for Plug-and-Produce. 3rd International Conference on System-Integrated Intelligence: New Challenges for Product and Production Engineering, 227–234.https://doi.org/ 10.1016/j.protcy.2016.08.031 

Adelt, P. (2015). Analyse von Ausführungszeiten durch Integration einer statischen WCET-Analyse mit einer dynamischen Befehlssatzsimulation am Beispiel der TriCore-Architektur. Universität Paderborn, Fakultät EIM.