Brede M. Implementation and Profiling of XCS in the Context of Embedded Systems. Paderborn: Paderborn University; 2021.

Sheikh MA. Design and Implementation of a ReconROS-Based Obstacle Avoidance System. Paderborn University; 2021.

Chandrakar K. Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis.; 2020.

Henke L-S. Evaluation of a ReconOS-ROS Combination Based on a Video Processing Application.; 2020.

Thiele S. Implementing Machine Learning Functions as PYNQ FPGA Overlays.; 2020.

Jaganath V. Extension and Evaluation of Python-Based High-Level Synthesis Tool Flows.; 2020.

Jentzsch FP. Design and Implementation of a ReconOS-Based TensorFlow Lite Delegate Architecture.; 2020.

Keerthipati M. A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking. Universität Paderborn; 2019.

Sabu NS. FPGA Acceleration of String Search Techniques in Huge Data Sets. Paderborn University; 2019.

Hansmeier T. Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers. Universität Paderborn; 2019.

Lienen C. Implementing a Real-Time System on a Platform FPGA Operated with ReconOS. Universität Paderborn

Schnuer J-P. Static Scheduling Algorithms for Heterogeneous Compute Nodes. Universität Paderborn; 2018.

Croce M. Evaluation of OpenCL-Based Compilation for FPGAs. Universität Paderborn; 2018.

Ho N. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn; 2018. doi:10.17619/UNIPB/1-376

Hansmeier T. An FPGA Accelerator for Checking Resolution Proofs. Universität Paderborn; 2017.

Witschen LM. A Framework for the Synthesis of Approximate Circuits. Universität Paderborn; 2017.

Knorr C. OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten. Universität Paderborn; 2017.

Knorr C. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn; 2015.

Koch B. Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University; 2014.

Schäfers L. Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH; 2014.

Surmund S. Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University; 2014.

Kaufmann P. Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag Berlin GmbH; 2013.

Happe M. Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores. Berlin: Logos Verlag Berlin GmbH; 2013.

Drzevitzky S. Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn; 2012.

Giefers H. Design and Programming of Reconfigurable Mesh Based Many-Cores. Berlin: Logos Verlag Berlin GmbH; 2012.