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Meißner, R. (2015). Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs. Universität Paderborn.
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Posewsky, T. (2015). Acceleration of Artificial Neural Networks on a Zynq Platform. Paderborn University.
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M. Mora, A., Squillero, G., Agapitos, A., Burelli, P., S. Bush, W., Cagnoni, S.,  Zhang (editors), M. (2015). Applications of Evolutionary Computation - 18th European Conference, EvoApplications (Vol. 9028). Copenhagen, Denmark: Springer.
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H.W. Leong, P., Amano, H., Anderson, J., Bertels, K., M.P. Cardoso, J., Diessel, O.,https://doi.org/10.1109/FPL.2015.7293747__Wang, Y. (2015). Significant papers from the first 25 years of the FPL conference. In Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL) (pp. 1–3). Imperial College.https://doi.org/10.1109/FPL.2015.7293747 
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Ghribi, I., Ben Abdallah, R., Khalgui, M., &; Platzner, M. (2015). New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software. In Proceedings of the 29th European Simulation and Modelling Conference (ESM).
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Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., &; De Micheli, G. (2015). From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires. IEEE Transactions on Nanotechnology, 14(6), 1117–1126.https://doi.org/10.1109/TNANO.2015.2482359 
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Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., Zhang, J., De Micheli, G., Sanchez, E., &; Reorda, M. S. (2015). On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors. In 2015 IEEE Computer Society Annual Symposium on VLSI (pp. 491–496). IEEE.https://doi.org/10.1109/ISVLSI.2015.13 
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Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., &; De Micheli, G. (2015). Fault modeling in controllable polarity silicon nanowire circuits. In Proceedings of the 2015 Design, Automation &; Test in Europe Conference \'26; Exhibition (pp. 453–458). EDA Consortium.https://doi.org/10.7873/DATE.2015.0428 
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Guettatfi, Z., Kermia, O., &; Khouas, A. (2015). Over effective hard real-time hardware tasks scheduling and allocation. In 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College.https://doi.org/10.1109/FPL.2015.7293994 
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