@inproceedings{19421, author = {{Holst, Stefan and Kampmann, Matthias and Sprenger, Alexander and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim and Weng, Xiaoqing}}, booktitle = {{IEEE International Test Conference (ITC'20), November 2020}}, title = {{{Logic Fault Diagnosis of Hidden Delay Defects}}}, year = {{2020}}, } @misc{8112, author = {{Maaz, Mohammad Urf and Sprenger, Alexander and Hellebrand, Sybille}}, keywords = {{WORKSHOP}}, publisher = {{31. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'19)}}, title = {{{A Hybrid Space Compactor for Varying X-Rates}}}, year = {{2019}}, } @article{8667, author = {{Sprenger, Alexander and Hellebrand, Sybille}}, issn = {{0218-1266}}, journal = {{Journal of Circuits, Systems and Computers}}, number = {{1}}, pages = {{1--23}}, publisher = {{World Scientific Publishing Company}}, title = {{{Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test}}}, doi = {{10.1142/s0218126619400012}}, volume = {{28}}, year = {{2019}}, } @article{13048, abstract = {{Marginal hardware introduces severe reliability threats throughout the life cycle of a system. Although marginalities may not affect the functionality of a circuit immediately after manufacturing, they can degrade into hard failures and must be screened out during manufacturing test to prevent early life failures. Furthermore, their evolution in the field must be proactively monitored by periodic tests before actual failures occur. In recent years small delay faults have gained increasing attention as possible indicators of marginal hardware. However, small delay faults on short paths may be undetectable even with advanced timing aware ATPG. Faster-than-at-speed test (FAST) can detect such hidden delay faults, but so far FAST has mainly been restricted to manufacturing test.}}, author = {{Kampmann, Matthias and A. Kochte, Michael and Liu, Chang and Schneider, Eric and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, issn = {{1937-4151}}, journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}}, number = {{10}}, pages = {{1956 -- 1968}}, publisher = {{IEEE}}, title = {{{Built-in Test for Hidden Delay Faults}}}, volume = {{38}}, year = {{2019}}, } @inproceedings{12918, abstract = {{The test for small delay faults is of major importance for predicting potential early life failures or wearout problems. Typically, a faster-than-at-speed test (FAST) with sev¬eral different frequencies is used to detect also hidden small delays, which can only be propagated over short paths. But then the outputs at the end of long paths may no longer reach their stable values at the nominal observation time and must be considered as unknown (X-values). Thus, test response compaction for FAST must be extremely flexible to cope with high X-rates, which also vary with the test frequencies. Stochastic compaction introduced by Mitra et al. is controlled by weighted pseudo-random signals allowing for easy adaptation to varying conditions. As demonstrated in previous work, the pseudo-random control can be optimized for high fault efficiency or X-reduction, but a given target in fault efficiency cannot be guaranteed. To close this gap, a hybrid space compactor is introduced in this paper. It is based on the observation that many faults are lost in the compaction of relatively few critical test patterns. For these critical patterns a deterministic compaction phase is added to the test, where the existing compactor structure is re-used, but controlled by specifically determined control vectors. }}, author = {{Maaz, Mohammad Urf and Sprenger, Alexander and Hellebrand, Sybille}}, booktitle = {{50th IEEE International Test Conference (ITC)}}, keywords = {{Faster-than-at-speed test, BIST, DFT, Test response compaction, Stochastic compactor, X-handling}}, location = {{Washington, DC, USA}}, pages = {{1--8}}, publisher = {{IEEE}}, title = {{{A Hybrid Space Compactor for Adaptive X-Handling}}}, year = {{2019}}, } @misc{4576, author = {{Sprenger, Alexander and Hellebrand, Sybille}}, keywords = {{WORKSHOP}}, publisher = {{30. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'18)}}, title = {{{Stochastische Kompaktierung für den Hochgeschwindigkeitstest}}}, year = {{2018}}, } @article{12974, author = {{Hellebrand, Sybille and Henkel, Joerg and Raghunathan, Anand and Wunderlich, Hans-Joachim}}, journal = {{IEEE Embedded Systems Letters}}, number = {{1}}, pages = {{1--1}}, publisher = {{IEEE}}, title = {{{Guest Editors' Introduction - Special Issue on Approximate Computing}}}, doi = {{10.1109/les.2018.2789942}}, volume = {{10}}, year = {{2018}}, } @article{13057, author = {{Kampmann, Matthias and Hellebrand, Sybille}}, journal = {{Microelectronics Reliability}}, pages = {{124--133}}, title = {{{Design For Small Delay Test - A Simulation Study}}}, volume = {{80}}, year = {{2018}}, } @misc{13072, author = {{Kampmann, Matthias and Hellebrand, Sybille}}, keywords = {{WORKSHOP}}, title = {{{Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test}}}, year = {{2018}}, } @inproceedings{29460, abstract = {{STT-RAM cells can be considered as an alternative or a hybrid addition to today's SRAM-based cache memories. This is mostly because of their scalability and low leakage power. Moreover, their data storing mechanism (storing the value as resistance) makes them very suitable and applicable for multivalue cache architectures. This feature results in system performance enhancement without any area overhead. On the other hand, the required two-step read/write procedure in multilevel cells results in a non-uniform time access and energy and power overhead on the system. In this paper, we propose a new architecture to dynamically swap data between soft (fast read access) and hard (slow read access) bits in ML cell. Moreover, by reconfiguring cache block size, the proposed architecture can switch between ML and SL modes at runtime. In other words, the swapping method places the hot part of each cache block into soft-bits and the less accessed part into the hard-bits. The SL/ML switching method benefits from the low latency and energy of SL mode and the high storing capacity of ML mode at the same time. Although experimental results show that our proposed method slightly increases the miss rate compared with the conventional ML caches, the performance and energy are improved by 4.9% and 6.5%, respectively. Also, the storage overhead of our method is about 1% that is negligible.}}, author = {{Rezaeizadeh Rookerd, Ramin and Sadeghi-Kohan, Somayeh and Navabi, Zainalabedin}}, booktitle = {{Proceedings of the 2018 on Great Lakes Symposium on VLSI}}, publisher = {{ACM}}, title = {{{Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture}}}, doi = {{10.1145/3194554.3194599}}, year = {{2018}}, } @inproceedings{4575, author = {{Sprenger, Alexander and Hellebrand, Sybille}}, booktitle = {{2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)}}, isbn = {{9781538657546}}, publisher = {{IEEE}}, title = {{{Tuning Stochastic Space Compaction to Faster-than-at-Speed Test}}}, doi = {{10.1109/ddecs.2018.00020}}, year = {{2018}}, } @inproceedings{10575, author = {{Liu, Chang and Schneider, Eric and Kampmann, Matthias and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{27th IEEE Asian Test Symposium (ATS'18)}}, isbn = {{9781538694664}}, title = {{{Extending Aging Monitors for Early Life and Wear-Out Failure Prevention}}}, doi = {{10.1109/ats.2018.00028}}, year = {{2018}}, } @inproceedings{29459, abstract = {{Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. With the emergence of new issues like Electro-migration these problems are getting more crucial. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes that expose smaller overheads to the circuit, using correlation between nodes and the shareability amongst them. To select internal nodes, we first prune some nodes based on some attributes and thus provide a near-optimal solution that can effectively get a number of internal nodes and consider the effects of electro-migration as well. We have applied our proposed scheme to several processors and ITC benchmarks and have looked at its effectiveness for these circuits.}}, author = {{Sadeghi-Kohan, Somayeh and Vafaei, Arash and Navabi, Zainalabedin}}, booktitle = {{2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)}}, publisher = {{IEEE}}, title = {{{Near-Optimal Node Selection Procedure for Aging Monitor Placement}}}, doi = {{10.1109/iolts.2018.8474120}}, year = {{2018}}, } @inproceedings{12973, author = {{Deshmukh, Jyotirmoy and Kunz, Wolfgang and Wunderlich, Hans-Joachim and Hellebrand, Sybille}}, booktitle = {{35th IEEE VLSI Test Symposium (VTS'17)}}, publisher = {{IEEE}}, title = {{{Special Session on Early Life Failures}}}, doi = {{10.1109/vts.2017.7928933}}, year = {{2017}}, } @misc{13078, author = {{Kampmann, Matthias and Hellebrand, Sybille}}, keywords = {{WORKSHOP}}, title = {{{X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz}}}, year = {{2017}}, } @inproceedings{10576, author = {{Kampmann, Matthias and Hellebrand, Sybille}}, booktitle = {{20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS'17)}}, isbn = {{9781538604724}}, publisher = {{IEEE}}, title = {{{Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test}}}, doi = {{10.1109/ddecs.2017.7934564}}, year = {{2017}}, } @article{29462, abstract = {{Time-variant age information of different parts of a system can be used for system-level performance improvement through high-level task scheduling, thus extending the life-time of the system. Progressive age information should provide the age state that the system is in, and the rate that it is being aged at. In this paper, we propose a structure that monitors certain paths of a circuit and detects its gradual age growth, and provides the aging rate and aging state of the circuit. The proposed monitors are placed on a selected set of nodes that represent a timing bottleneck of the system. These monitors sample expected data on these nodes, and compare them with the expected values. The timing of sampling changes as the circuit ages and its delay increases. The timing of sampling will provide a measure of aging advancement of a circuit. To assess the efficacy of the proposed method and compare it with other state-of-the-art aging monitors, we use them on selected nodes of the execution unit of different processors, as well as some circuits from ITC99 benchmarks. The results reveal that the precision of our proposed method is between 0.12 (ns) to 0.401 (ns). Its Area and power overhead are negligible and are about 2.13 and 0.69 percent respectively.}}, author = {{Sadeghi-Kohan, Somayeh and Kamal, Mehdi and Navabi, Zainalabedin}}, issn = {{2168-6750}}, journal = {{IEEE Transactions on Emerging Topics in Computing}}, keywords = {{Age advancement, age monitoring clock, aging rate, self-adjusting monitors}}, number = {{3}}, pages = {{627--641}}, publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}}, title = {{{Self-Adjusting Monitor for Measuring Aging Rate and Advancement}}}, doi = {{10.1109/tetc.2017.2771441}}, volume = {{8}}, year = {{2017}}, } @inproceedings{29463, abstract = {{In this paper we propose to think out of the box and discuss an approach for universal mitigation of Negative Bias Temperature Instability (NBTI) induced aging untied from the limitations of its modelling. The cost-effective approach exploits a simple property of a randomized design, i.e., the equalized signal probability and switching activity at gate inputs. The techniques considered for structural design randomization involve both the hardware architecture and embedded software layers. Ultimately, the proposed approach aims at extending the reliable lifetime of nanoelectronic systems.}}, author = {{Jenihhin, Maksim and Kamkin, Alexander and Navabi, Zainalabedin and Sadeghi-Kohan, Somayeh}}, booktitle = {{2016 IEEE East-West Design & Test Symposium (EWDTS)}}, publisher = {{IEEE}}, title = {{{Universal mitigation of NBTI-induced aging by design randomization}}}, doi = {{10.1109/ewdts.2016.7807635}}, year = {{2017}}, } @inproceedings{12975, author = {{Kampmann, Matthias and Hellebrand, Sybille}}, booktitle = {{25th IEEE Asian Test Symposium (ATS'16)}}, pages = {{1--6}}, publisher = {{IEEE}}, title = {{{X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test}}}, doi = {{10.1109/ats.2016.20}}, year = {{2016}}, } @inproceedings{12976, author = {{Kampmann, Matthias and A. Kochte, Michael and Schneider, Eric and Indlekofer, Thomas and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{24th IEEE Asian Test Symposium (ATS'15)}}, pages = {{109--114}}, publisher = {{IEEE}}, title = {{{Optimized Selection of Frequencies for Faster-Than-at-Speed Test}}}, doi = {{10.1109/ats.2015.26}}, year = {{2015}}, }