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ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024, 2024."},"year":"2024","place":"Darmstadt, Germany","department":[{"_id":"48"}],"user_id":"209","_id":"50284","language":[{"iso":"eng"}],"type":"misc","status":"public"},{"status":"public","type":"conference","publication":"In: IEEE International Test Conference (ITC'24), San Diego, CA, USA, November 2024","language":[{"iso":"eng"}],"user_id":"36703","department":[{"_id":"48"}],"_id":"56014","citation":{"bibtex":"@inproceedings{Jafarzadeh_Klemme_Reimer_ Amrouch_Hellebrand_Wunderlich_2024, place={San Diego, CA}, title={Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing}, booktitle={In: IEEE International Test Conference (ITC’24), San Diego, CA, USA, November 2024}, publisher={IEEE}, author={Jafarzadeh, Hanieh and Klemme, Florian and Reimer, Jan Dennis and  Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2024} }","short":"H. Jafarzadeh, F. Klemme, J.D. Reimer, H.  Amrouch, S. Hellebrand, H.-J. Wunderlich, in: In: IEEE International Test Conference (ITC’24), San Diego, CA, USA, November 2024, IEEE, San Diego, CA, 2024.","mla":"Jafarzadeh, Hanieh, et al. “Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing.” <i>In: IEEE International Test Conference (ITC’24), San Diego, CA, USA, November 2024</i>, IEEE, 2024.","apa":"Jafarzadeh, H., Klemme, F., Reimer, J. D.,  Amrouch, H., Hellebrand, S., &#38; Wunderlich, H.-J. (2024). Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing. <i>In: IEEE International Test Conference (ITC’24), San Diego, CA, USA, November 2024</i>. IEEE International Test Conference (ITC’24), San Diego, CA, USA.","chicago":"Jafarzadeh, Hanieh, Florian Klemme, Jan Dennis Reimer, Hussam  Amrouch, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing.” In <i>In: IEEE International Test Conference (ITC’24), San Diego, CA, USA, November 2024</i>. San Diego, CA: IEEE, 2024.","ieee":"H. Jafarzadeh, F. Klemme, J. D. Reimer, H.  Amrouch, S. Hellebrand, and H.-J. Wunderlich, “Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing,” presented at the IEEE International Test Conference (ITC’24), San Diego, CA, USA, 2024.","ama":"Jafarzadeh H, Klemme F, Reimer JD,  Amrouch H, Hellebrand S, Wunderlich H-J. Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing. In: <i>In: IEEE International Test Conference (ITC’24), San Diego, CA, USA, November 2024</i>. IEEE; 2024."},"year":"2024","place":"San Diego, CA","conference":{"location":"San Diego, CA, USA","end_date":"2024-11-08","start_date":"2024-11-03","name":"IEEE International Test Conference (ITC'24)"},"title":"Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing","author":[{"first_name":"Hanieh","last_name":"Jafarzadeh","full_name":"Jafarzadeh, Hanieh"},{"first_name":"Florian","full_name":"Klemme, Florian","last_name":"Klemme"},{"last_name":"Reimer","full_name":"Reimer, Jan Dennis","id":"36703","first_name":"Jan Dennis"},{"last_name":" Amrouch","full_name":" Amrouch, Hussam","first_name":"Hussam"},{"first_name":"Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille"},{"first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich"}],"date_created":"2024-09-04T09:25:20Z","date_updated":"2025-03-31T15:57:16Z","publisher":"IEEE"},{"language":[{"iso":"eng"}],"user_id":"36703","department":[{"_id":"48"}],"_id":"46738","status":"public","type":"conference","publication":"IEEE Asian Test Symposium (ATS'23), October 2023","conference":{"name":"IEEE Asian Test Symposium (ATS'23)","start_date":"2023-10-14","end_date":"2023-10-17"},"title":"Optimizing the Streaming of Sensor Data with Approximate Communication","date_created":"2023-08-26T08:47:52Z","author":[{"id":"78614","full_name":"Sadeghi-Kohan, Somayeh","last_name":"Sadeghi-Kohan","orcid":"https://orcid.org/0000-0001-7246-0610","first_name":"Somayeh"},{"full_name":"Reimer, Jan Dennis","id":"36703","last_name":"Reimer","first_name":"Jan Dennis"},{"first_name":"Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille"},{"full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich","first_name":"Hans-Joachim"}],"date_updated":"2024-01-08T08:49:08Z","citation":{"short":"S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, in: IEEE Asian Test Symposium (ATS’23), October 2023, Beijing, China, 2023.","bibtex":"@inproceedings{Sadeghi-Kohan_Reimer_Hellebrand_Wunderlich_2023, place={Beijing, China}, title={Optimizing the Streaming of Sensor Data with Approximate Communication}, booktitle={IEEE Asian Test Symposium (ATS’23), October 2023}, author={Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023} }","mla":"Sadeghi-Kohan, Somayeh, et al. “Optimizing the Streaming of Sensor Data with Approximate Communication.” <i>IEEE Asian Test Symposium (ATS’23), October 2023</i>, 2023.","apa":"Sadeghi-Kohan, S., Reimer, J. D., Hellebrand, S., &#38; Wunderlich, H.-J. (2023). Optimizing the Streaming of Sensor Data with Approximate Communication. <i>IEEE Asian Test Symposium (ATS’23), October 2023</i>. IEEE Asian Test Symposium (ATS’23).","chicago":"Sadeghi-Kohan, Somayeh, Jan Dennis Reimer, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Optimizing the Streaming of Sensor Data with Approximate Communication.” In <i>IEEE Asian Test Symposium (ATS’23), October 2023</i>. Beijing, China, 2023.","ieee":"S. Sadeghi-Kohan, J. D. Reimer, S. Hellebrand, and H.-J. Wunderlich, “Optimizing the Streaming of Sensor Data with Approximate Communication,” presented at the IEEE Asian Test Symposium (ATS’23), 2023.","ama":"Sadeghi-Kohan S, Reimer JD, Hellebrand S, Wunderlich H-J. Optimizing the Streaming of Sensor Data with Approximate Communication. In: <i>IEEE Asian Test Symposium (ATS’23), October 2023</i>. ; 2023."},"place":"Beijing, China","year":"2023"},{"publication":"IEEE Design &Test","type":"journal_article","abstract":[{"text":"System-level interconnects provide the\r\nbackbone for increasingly complex systems on a chip. Their\r\nvulnerability to electromigration and crosstalk can lead to\r\nserious reliability and safety issues during the system lifetime.\r\nThis article presents an approach for periodic in-system testing\r\nwhich maintains a reliability profile to detect potential\r\nproblems before they actually cause a failure. Relying on a\r\ncommon infrastructure for EM-aware system workload\r\nmanagement and test, it minimizes the stress induced by the\r\ntest itself and contributes to the self-healing of system-induced\r\nelectromigration degradations. ","lang":"eng"}],"status":"public","_id":"46264","department":[{"_id":"48"}],"user_id":"209","keyword":["Electrical and Electronic Engineering","Hardware and Architecture","Software"],"article_type":"original","language":[{"iso":"eng"}],"publication_identifier":{"issn":["2168-2356","2168-2364"]},"publication_status":"published","year":"2023","page":"1-1","citation":{"ama":"Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Workload-Aware Periodic Interconnect BIST. <i>IEEE Design &#38;Test</i>. Published online 2023:1-1. doi:<a href=\"https://doi.org/10.1109/mdat.2023.3298849\">10.1109/mdat.2023.3298849</a>","chicago":"Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Workload-Aware Periodic Interconnect BIST.” <i>IEEE Design &#38;Test</i>, 2023, 1–1. <a href=\"https://doi.org/10.1109/mdat.2023.3298849\">https://doi.org/10.1109/mdat.2023.3298849</a>.","ieee":"S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Workload-Aware Periodic Interconnect BIST,” <i>IEEE Design &#38;Test</i>, pp. 1–1, 2023, doi: <a href=\"https://doi.org/10.1109/mdat.2023.3298849\">10.1109/mdat.2023.3298849</a>.","bibtex":"@article{Sadeghi-Kohan_Hellebrand_Wunderlich_2023, title={Workload-Aware Periodic Interconnect BIST}, DOI={<a href=\"https://doi.org/10.1109/mdat.2023.3298849\">10.1109/mdat.2023.3298849</a>}, journal={IEEE Design &#38;Test}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023}, pages={1–1} }","mla":"Sadeghi-Kohan, Somayeh, et al. “Workload-Aware Periodic Interconnect BIST.” <i>IEEE Design &#38;Test</i>, Institute of Electrical and Electronics Engineers (IEEE), 2023, pp. 1–1, doi:<a href=\"https://doi.org/10.1109/mdat.2023.3298849\">10.1109/mdat.2023.3298849</a>.","short":"S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, IEEE Design &#38;Test (2023) 1–1.","apa":"Sadeghi-Kohan, S., Hellebrand, S., &#38; Wunderlich, H.-J. (2023). Workload-Aware Periodic Interconnect BIST. <i>IEEE Design &#38;Test</i>, 1–1. <a href=\"https://doi.org/10.1109/mdat.2023.3298849\">https://doi.org/10.1109/mdat.2023.3298849</a>"},"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","date_updated":"2024-03-22T17:15:10Z","date_created":"2023-08-02T11:07:43Z","author":[{"full_name":"Sadeghi-Kohan, Somayeh","id":"78614","last_name":"Sadeghi-Kohan","orcid":"https://orcid.org/0000-0001-7246-0610","first_name":"Somayeh"},{"first_name":"Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","id":"209"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"}],"title":"Workload-Aware Periodic Interconnect BIST","doi":"10.1109/mdat.2023.3298849","main_file_link":[{"url":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10194315"}]},{"date_created":"2023-07-03T08:20:17Z","author":[{"full_name":"Jafarzadeh, Hanieh","last_name":"Jafarzadeh","first_name":"Hanieh"},{"last_name":"Klemme","full_name":"Klemme, Florian","first_name":"Florian"},{"first_name":"Jan Dennis","id":"36703","full_name":"Reimer, Jan Dennis","last_name":"Reimer"},{"first_name":"Zahra Paria","full_name":"Najafi Haghi, Zahra Paria","last_name":"Najafi Haghi"},{"last_name":" Amrouch","full_name":" Amrouch, Hussam","first_name":"Hussam"},{"first_name":"Sybille","full_name":"Hellebrand, Sybille","id":"209","last_name":"Hellebrand","orcid":"0000-0002-3717-3939"},{"first_name":"Hans-Joachim","full_name":" Wunderlich, Hans-Joachim","last_name":" Wunderlich"}],"date_updated":"2024-03-22T17:14:02Z","publisher":"IEEE","conference":{"end_date":"2023-10-13","location":"Anaheim, USA","name":"IEEE International Test Conference (ITC'23)","start_date":"2023-10-08"},"title":"Robust Pattern Generation for Small Delay Faults under Process Variations","publication_status":"published","citation":{"ama":"Jafarzadeh H, Klemme F, Reimer JD, et al. Robust Pattern Generation for Small Delay Faults under Process Variations. In: <i>IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023</i>. IEEE; 2023.","chicago":"Jafarzadeh, Hanieh, Florian Klemme, Jan Dennis Reimer, Zahra Paria Najafi Haghi, Hussam  Amrouch, Sybille Hellebrand, and Hans-Joachim  Wunderlich. “Robust Pattern Generation for Small Delay Faults under Process Variations.” In <i>IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023</i>. Anaheim, CA, USA: IEEE, 2023.","ieee":"H. Jafarzadeh <i>et al.</i>, “Robust Pattern Generation for Small Delay Faults under Process Variations,” presented at the IEEE International Test Conference (ITC’23), Anaheim, USA, 2023.","short":"H. Jafarzadeh, F. Klemme, J.D. Reimer, Z.P. Najafi Haghi, H.  Amrouch, S. Hellebrand, H.-J.  Wunderlich, in: IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023, IEEE, Anaheim, CA, USA, 2023.","mla":"Jafarzadeh, Hanieh, et al. “Robust Pattern Generation for Small Delay Faults under Process Variations.” <i>IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023</i>, IEEE, 2023.","bibtex":"@inproceedings{Jafarzadeh_Klemme_Reimer_Najafi Haghi_ Amrouch_Hellebrand_ Wunderlich_2023, place={Anaheim, CA, USA}, title={Robust Pattern Generation for Small Delay Faults under Process Variations}, booktitle={IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023}, publisher={IEEE}, author={Jafarzadeh, Hanieh and Klemme, Florian and Reimer, Jan Dennis and Najafi Haghi, Zahra Paria and  Amrouch, Hussam and Hellebrand, Sybille and  Wunderlich, Hans-Joachim}, year={2023} }","apa":"Jafarzadeh, H., Klemme, F., Reimer, J. D., Najafi Haghi, Z. P.,  Amrouch, H., Hellebrand, S., &#38;  Wunderlich, H.-J. (2023). Robust Pattern Generation for Small Delay Faults under Process Variations. <i>IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023</i>. IEEE International Test Conference (ITC’23), Anaheim, USA."},"place":"Anaheim, CA, USA","year":"2023","user_id":"209","department":[{"_id":"48"}],"_id":"45830","language":[{"iso":"eng"}],"type":"conference","publication":"IEEE International Test Conference (ITC'23), Anaheim, USA, October 2023","status":"public"},{"page":"2","citation":{"ama":"Ghazal A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. <i>On Cryptography Effects on Interconnect Reliability</i>. 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023; 2023.","ieee":"A. Ghazal, S. Sadeghi-Kohan, J. D. Reimer, and S. Hellebrand, <i>On Cryptography Effects on Interconnect Reliability</i>. Erfurt, Germany: 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, 2023.","chicago":"Ghazal, Abdulkarim, Somayeh Sadeghi-Kohan, Jan Dennis Reimer, and Sybille Hellebrand. <i>On Cryptography Effects on Interconnect Reliability</i>. Erfurt, Germany: 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, 2023.","apa":"Ghazal, A., Sadeghi-Kohan, S., Reimer, J. D., &#38; Hellebrand, S. (2023). <i>On Cryptography Effects on Interconnect Reliability</i>. 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023.","short":"A. Ghazal, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, On Cryptography Effects on Interconnect Reliability, 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, Erfurt, Germany, 2023.","bibtex":"@book{Ghazal_Sadeghi-Kohan_Reimer_Hellebrand_2023, place={Erfurt, Germany}, title={On Cryptography Effects on Interconnect Reliability}, publisher={35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023}, author={Ghazal, Abdulkarim and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}, year={2023} }","mla":"Ghazal, Abdulkarim, et al. <i>On Cryptography Effects on Interconnect Reliability</i>. 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, 2023."},"year":"2023","place":"Erfurt, Germany","date_created":"2023-01-04T10:20:41Z","author":[{"full_name":"Ghazal, Abdulkarim","last_name":"Ghazal","first_name":"Abdulkarim"},{"first_name":"Somayeh","last_name":"Sadeghi-Kohan","id":"78614","full_name":"Sadeghi-Kohan, Somayeh"},{"full_name":"Reimer, Jan Dennis","id":"36703","last_name":"Reimer","first_name":"Jan Dennis"},{"first_name":"Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","id":"209","full_name":"Hellebrand, Sybille"}],"date_updated":"2023-04-06T21:06:37Z","publisher":"35. Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\" (TuZ'23), Feb. 2023","title":"On Cryptography Effects on Interconnect Reliability","type":"misc","status":"public","department":[{"_id":"48"}],"user_id":"36703","_id":"35204","language":[{"iso":"eng"}],"keyword":["WORKSHOP"]},{"extern":"1","user_id":"22707","department":[{"_id":"48"}],"_id":"46482","status":"public","type":"dissertation","main_file_link":[{"open_access":"1","url":"https://nbn-resolving.org/urn:nbn:de:hbz:466:2-45493"}],"doi":"10.17619/UNIPB/1-1787","supervisor":[{"orcid":"0000-0002-3717-3939","last_name":"Hellebrand","id":"209","full_name":"Hellebrand, Sybille","first_name":"Sybille"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"author":[{"first_name":"Alexander","orcid":"0000-0002-0775-7677","last_name":"Sprenger","id":"22707","full_name":"Sprenger, Alexander"}],"date_updated":"2023-08-12T09:13:18Z","oa":"1","citation":{"bibtex":"@book{Sprenger_2023, place={Paderborn}, title={Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen}, DOI={<a href=\"https://doi.org/10.17619/UNIPB/1-1787\">10.17619/UNIPB/1-1787</a>}, publisher={Universität Paderborn}, author={Sprenger, Alexander}, year={2023} }","short":"A. Sprenger, Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen, Universität Paderborn, Paderborn, 2023.","mla":"Sprenger, Alexander. <i>Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Universität Paderborn, 2023, doi:<a href=\"https://doi.org/10.17619/UNIPB/1-1787\">10.17619/UNIPB/1-1787</a>.","apa":"Sprenger, A. (2023). <i>Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Universität Paderborn. <a href=\"https://doi.org/10.17619/UNIPB/1-1787\">https://doi.org/10.17619/UNIPB/1-1787</a>","ama":"Sprenger A. <i>Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Universität Paderborn; 2023. doi:<a href=\"https://doi.org/10.17619/UNIPB/1-1787\">10.17619/UNIPB/1-1787</a>","ieee":"A. Sprenger, <i>Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Paderborn: Universität Paderborn, 2023.","chicago":"Sprenger, Alexander. <i>Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Paderborn: Universität Paderborn, 2023. <a href=\"https://doi.org/10.17619/UNIPB/1-1787\">https://doi.org/10.17619/UNIPB/1-1787</a>."},"page":"xi, 160","place":"Paderborn","publication_status":"published","language":[{"iso":"ger"}],"keyword":["Testantwortkompaktierung","Prozessvariation","Silicon Lifecycle Management"],"abstract":[{"lang":"eng","text":"Ever increasing demands on the performance of microchips are leading to ever more complex semiconductor technologies with ever shrinking feature sizes. Complex applications with high demands on safety and reliability, such as autonomous driving, are simultaneously driving the requirements for test and diagnosis of VLSI circuits. Throughout the life cycle of a microchip, uncertainties occur that affect its timing behavior. For example, weak circuit structures, aging effects, or process variations can lead to a change in the timing behavior of the circuit. While these uncertainties do not necessarily lead to a change of the functional behavior, they can lead to a reliability problem.\r\nWith modular and hybrid compaction two test instruments are presented in this work that can be used for X-tolerant test response compaction in the built-in Faster-than-At-Speed Test (FAST) which is used to detect uncertainties in VLSI circuits. One challenge for test response compaction during FAST is the high and varying X-rate at the outputs of the circuit under test. By dividing the circuit outputs into test groups and separately compacting these test groups using stochastic compactors, the modular compaction is able to handle these high and varying X-rates.\r\nTo deal with uncertainties on logic interconnects, a method for distinguishing crosstalk and process variation is presented. In current semiconductor technologies, the number of parasitic coupling capacitances between logic interconnects is growing. These coupling capacitances can lead to crosstalk, which causes increased current flow in the logic interconnects, which in turn can lead to increased electromigration. In the presented method, delay maps describing the timing behavior of the circuit outputs at different operating points are used to train artificial neural networks which classify the tested circuits into fault-free and faulty."},{"lang":"ger","text":"Immer größere Anforderungen an die Leistungsfähigkeit von Mikrochips führen zu Halbleitertechnologien mit immer kleiner werdenden Strukturgrößen. Anwendungen mit hohen Ansprüchen an Sicherheit und Zuverlässigkeit, wie z.B. das autonome Fahren, treiben gleichzeitig die Anforderungen an den Test hochintegrierter Schaltungen an. Während des gesamten Lebenszyklus eines Mikrochips kommt es zu Unsicherheiten im Zeitverhalten. So können z.B. schwache Schaltungsstrukturen, Alterungseffekte oder Prozessvariationen zu einer Veränderung des Zeitverhaltens führen. Während diese Unsicherheiten nicht zu einer Veränderung des funktionalen Verhaltens führen müssen, können sie jedoch zu einem Zuverlässigkeitsproblem führen.\r\nMit der modularen und der hybriden Kompaktierung werden in dieser Arbeit zwei Testinstrumente vorgestellt, die für die X-tolerante Testantwortkompaktierung im eingebauten Hochgeschwindigkeitstest verwendet werden können. Eine Herausforderung für die Testantwortkompaktierung während des Hochgeschwindigkeitstests ist die hohe und variierende X-Rate an den Ausgängen der zu testenden Schaltung. Durch die Einteilung der Schaltungsausgänge in Prüfgruppen und die separierte Kompaktierung der Prüfgruppen mithilfe von stochastischen Kompaktierern, können die vorgestellten Verfahren diese hohen und variierenden X-Raten verarbeiten.\r\nFür den Umgang mit Unsicherheiten auf Verbindungsleitungen der Logik-Schaltung wird ein Verfahren zur Unterscheidung von Übersprechen und Prozessvariation vorgestellt. In aktuellen Halbleitertechnologien kommt es vermehrt zu parasitären Koppelkapazitäten zwischen den Verbindungsleitungen. In dem vorgestellten Verfahren werden künstliche neuronale Netze trainiert, um die Schaltungen in fehlerfrei und fehlerhaft zu klassifizieren."}],"title":"Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen","date_created":"2023-08-12T09:10:38Z","publisher":"Universität Paderborn","year":"2023"},{"doi":"10.1109/dsn-w58399.2023.00056","title":"Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication","author":[{"id":"78614","full_name":"Sadeghi-Kohan, Somayeh","last_name":"Sadeghi-Kohan","orcid":"https://orcid.org/0000-0001-7246-0610","first_name":"Somayeh"},{"orcid":"0000-0002-3717-3939","last_name":"Hellebrand","full_name":"Hellebrand, Sybille","id":"209","first_name":"Sybille"},{"first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich"}],"date_created":"2023-08-26T10:48:31Z","date_updated":"2023-08-26T10:49:07Z","publisher":"IEEE","citation":{"bibtex":"@inproceedings{Sadeghi-Kohan_Hellebrand_Wunderlich_2023, title={Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication}, DOI={<a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">10.1109/dsn-w58399.2023.00056</a>}, booktitle={2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023} }","short":"S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, in: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), IEEE, 2023.","mla":"Sadeghi-Kohan, Somayeh, et al. “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication.” <i>2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)</i>, IEEE, 2023, doi:<a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">10.1109/dsn-w58399.2023.00056</a>.","apa":"Sadeghi-Kohan, S., Hellebrand, S., &#38; Wunderlich, H.-J. (2023). Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. <i>2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)</i>. <a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">https://doi.org/10.1109/dsn-w58399.2023.00056</a>","ama":"Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. In: <i>2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)</i>. IEEE; 2023. doi:<a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">10.1109/dsn-w58399.2023.00056</a>","chicago":"Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication.” In <i>2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)</i>. IEEE, 2023. <a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">https://doi.org/10.1109/dsn-w58399.2023.00056</a>.","ieee":"S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication,” 2023, doi: <a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">10.1109/dsn-w58399.2023.00056</a>."},"year":"2023","publication_status":"published","language":[{"iso":"eng"}],"user_id":"78614","department":[{"_id":"48"}],"_id":"46739","status":"public","type":"conference","publication":"2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)"},{"type":"journal_article","publication":"Journal of Electronic Testing","abstract":[{"text":"Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The paper at hand extends this approach to interconnect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test.","lang":"eng"}],"status":"public","_id":"29351","user_id":"209","department":[{"_id":"48"}],"article_type":"original","keyword":["Electrical and Electronic Engineering"],"language":[{"iso":"eng"}],"publication_status":"published","publication_identifier":{"issn":["0923-8174","1573-0727"]},"year":"2022","citation":{"ama":"Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Stress-Aware Periodic Test of Interconnects. <i>Journal of Electronic Testing</i>. Published online 2022. doi:<a href=\"https://doi.org/10.1007/s10836-021-05979-5\">10.1007/s10836-021-05979-5</a>","chicago":"Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Stress-Aware Periodic Test of Interconnects.” <i>Journal of Electronic Testing</i>, 2022. <a href=\"https://doi.org/10.1007/s10836-021-05979-5\">https://doi.org/10.1007/s10836-021-05979-5</a>.","ieee":"S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Stress-Aware Periodic Test of Interconnects,” <i>Journal of Electronic Testing</i>, 2022, doi: <a href=\"https://doi.org/10.1007/s10836-021-05979-5\">10.1007/s10836-021-05979-5</a>.","apa":"Sadeghi-Kohan, S., Hellebrand, S., &#38; Wunderlich, H.-J. (2022). Stress-Aware Periodic Test of Interconnects. <i>Journal of Electronic Testing</i>. <a href=\"https://doi.org/10.1007/s10836-021-05979-5\">https://doi.org/10.1007/s10836-021-05979-5</a>","bibtex":"@article{Sadeghi-Kohan_Hellebrand_Wunderlich_2022, title={Stress-Aware Periodic Test of Interconnects}, DOI={<a href=\"https://doi.org/10.1007/s10836-021-05979-5\">10.1007/s10836-021-05979-5</a>}, journal={Journal of Electronic Testing}, publisher={Springer Science and Business Media LLC}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2022} }","short":"S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, Journal of Electronic Testing (2022).","mla":"Sadeghi-Kohan, Somayeh, et al. “Stress-Aware Periodic Test of Interconnects.” <i>Journal of Electronic Testing</i>, Springer Science and Business Media LLC, 2022, doi:<a href=\"https://doi.org/10.1007/s10836-021-05979-5\">10.1007/s10836-021-05979-5</a>."},"date_updated":"2022-05-11T16:10:01Z","publisher":"Springer Science and Business Media LLC","date_created":"2022-01-14T11:16:34Z","author":[{"first_name":"Somayeh","id":"78614","full_name":"Sadeghi-Kohan, Somayeh","last_name":"Sadeghi-Kohan"},{"first_name":"Sybille","full_name":"Hellebrand, Sybille","id":"209","orcid":"0000-0002-3717-3939","last_name":"Hellebrand"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"}],"title":"Stress-Aware Periodic Test of Interconnects","doi":"10.1007/s10836-021-05979-5"},{"type":"misc","status":"public","_id":"29890","user_id":"209","department":[{"_id":"48"}],"keyword":["WORKSHOP"],"language":[{"iso":"eng"}],"publication_status":"published","place":"Online","year":"2022","citation":{"ama":"Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. <i>EM-Aware Interconnect BIST</i>. European Workshop on Silicon Lifecycle Management, March 18, 2022; 2022.","ieee":"S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, <i>EM-Aware Interconnect BIST</i>. Online: European Workshop on Silicon Lifecycle Management, March 18, 2022, 2022.","chicago":"Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. <i>EM-Aware Interconnect BIST</i>. Online: European Workshop on Silicon Lifecycle Management, March 18, 2022, 2022.","apa":"Sadeghi-Kohan, S., Hellebrand, S., &#38; Wunderlich, H.-J. (2022). <i>EM-Aware Interconnect BIST</i>. European Workshop on Silicon Lifecycle Management, March 18, 2022.","short":"S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, EM-Aware Interconnect BIST, European Workshop on Silicon Lifecycle Management, March 18, 2022, Online, 2022.","mla":"Sadeghi-Kohan, Somayeh, et al. <i>EM-Aware Interconnect BIST</i>. European Workshop on Silicon Lifecycle Management, March 18, 2022, 2022.","bibtex":"@book{Sadeghi-Kohan_Hellebrand_Wunderlich_2022, place={Online}, title={EM-Aware Interconnect BIST}, publisher={European Workshop on Silicon Lifecycle Management, March 18, 2022}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2022} }"},"page":"2","date_updated":"2022-05-11T17:07:24Z","publisher":"European Workshop on Silicon Lifecycle Management, March 18, 2022","author":[{"last_name":"Sadeghi-Kohan","full_name":"Sadeghi-Kohan, Somayeh","id":"78614","first_name":"Somayeh"},{"first_name":"Sybille","id":"209","full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand"},{"full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich","first_name":"Hans-Joachim"}],"date_created":"2022-02-19T14:21:24Z","title":"EM-Aware Interconnect BIST"},{"language":[{"iso":"eng"}],"department":[{"_id":"48"}],"user_id":"209","_id":"19422","status":"public","publication":"IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020","type":"conference","conference":{"start_date":"2020-10-19","end_date":"2020-10-21"},"title":"Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study","date_created":"2020-09-15T14:03:02Z","author":[{"full_name":"Sprenger, Alexander","id":"22707","last_name":"Sprenger","first_name":"Alexander"},{"id":"78614","full_name":"Sadeghi-Kohan, Somayeh","last_name":"Sadeghi-Kohan","first_name":"Somayeh"},{"first_name":"Jan Dennis","id":"36703","full_name":"Reimer, Jan Dennis","last_name":"Reimer"},{"id":"209","full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","first_name":"Sybille"}],"date_updated":"2022-02-19T14:16:58Z","citation":{"bibtex":"@inproceedings{Sprenger_Sadeghi-Kohan_Reimer_Hellebrand_2020, place={Virtual Conference - Originally Frascati (Rome), Italy}, title={Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study}, booktitle={IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020}, author={Sprenger, Alexander and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}, year={2020} }","short":"A. Sprenger, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, Virtual Conference - Originally Frascati (Rome), Italy, 2020.","mla":"Sprenger, Alexander, et al. “Variation-Aware Test for Logic Interconnects Using Neural Networks - A Case Study.” <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>, 2020.","apa":"Sprenger, A., Sadeghi-Kohan, S., Reimer, J. D., &#38; Hellebrand, S. (2020). Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>.","ieee":"A. Sprenger, S. Sadeghi-Kohan, J. D. Reimer, and S. Hellebrand, “Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study,” 2020.","chicago":"Sprenger, Alexander, Somayeh Sadeghi-Kohan, Jan Dennis Reimer, and Sybille Hellebrand. “Variation-Aware Test for Logic Interconnects Using Neural Networks - A Case Study.” In <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>. Virtual Conference - Originally Frascati (Rome), Italy, 2020.","ama":"Sprenger A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. In: <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>. ; 2020."},"year":"2020","place":"Virtual Conference - Originally Frascati (Rome), Italy","publication_status":"published"},{"status":"public","type":"misc","keyword":["WORKSHOP"],"language":[{"iso":"eng"}],"_id":"15419","user_id":"209","department":[{"_id":"48"}],"place":"Ludwigsburg","year":"2020","citation":{"short":"S. Sadeghi-Kohan, S. Hellebrand, Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects, 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, Ludwigsburg, 2020.","mla":"Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. <i>Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects</i>. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, 2020.","bibtex":"@book{Sadeghi-Kohan_Hellebrand_2020, place={Ludwigsburg}, title={Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects}, publisher={32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}, year={2020} }","apa":"Sadeghi-Kohan, S., &#38; Hellebrand, S. (2020). <i>Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects</i>. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020.","ieee":"S. Sadeghi-Kohan and S. Hellebrand, <i>Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects</i>. Ludwigsburg: 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, 2020.","chicago":"Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. <i>Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects</i>. Ludwigsburg: 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, 2020.","ama":"Sadeghi-Kohan S, Hellebrand S. <i>Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects</i>. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020; 2020."},"page":"4","publication_status":"published","title":"Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects","date_updated":"2022-04-04T12:30:02Z","publisher":"32. Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\" (TuZ'20), 16. - 18. Februar 2020","author":[{"first_name":"Somayeh","last_name":"Sadeghi-Kohan","id":"78614","full_name":"Sadeghi-Kohan, Somayeh"},{"first_name":"Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille"}],"date_created":"2019-12-29T16:13:58Z"},{"citation":{"mla":"Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. “Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects.” <i>38th IEEE VLSI Test Symposium (VTS)</i>, IEEE, 2020, doi:<a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">10.1109/vts48691.2020.9107591</a>.","short":"S. Sadeghi-Kohan, S. Hellebrand, in: 38th IEEE VLSI Test Symposium (VTS), IEEE, Virtual Conference - Originally San Diego, CA, USA, 2020.","bibtex":"@inproceedings{Sadeghi-Kohan_Hellebrand_2020, place={Virtual Conference - Originally San Diego, CA, USA}, title={Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects}, DOI={<a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">10.1109/vts48691.2020.9107591</a>}, booktitle={38th IEEE VLSI Test Symposium (VTS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}, year={2020} }","apa":"Sadeghi-Kohan, S., &#38; Hellebrand, S. (2020). Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. <i>38th IEEE VLSI Test Symposium (VTS)</i>. <a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">https://doi.org/10.1109/vts48691.2020.9107591</a>","chicago":"Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. “Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects.” In <i>38th IEEE VLSI Test Symposium (VTS)</i>. Virtual Conference - Originally San Diego, CA, USA: IEEE, 2020. <a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">https://doi.org/10.1109/vts48691.2020.9107591</a>.","ieee":"S. Sadeghi-Kohan and S. Hellebrand, “Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects,” 2020, doi: <a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">10.1109/vts48691.2020.9107591</a>.","ama":"Sadeghi-Kohan S, Hellebrand S. Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. In: <i>38th IEEE VLSI Test Symposium (VTS)</i>. IEEE; 2020. doi:<a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">10.1109/vts48691.2020.9107591</a>"},"year":"2020","place":"Virtual Conference - Originally San Diego, CA, USA","publication_status":"published","doi":"10.1109/vts48691.2020.9107591","title":"Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects","author":[{"full_name":"Sadeghi-Kohan, Somayeh","id":"78614","last_name":"Sadeghi-Kohan","first_name":"Somayeh"},{"first_name":"Sybille","full_name":"Hellebrand, Sybille","id":"209","orcid":"0000-0002-3717-3939","last_name":"Hellebrand"}],"date_created":"2022-01-10T08:38:34Z","date_updated":"2022-05-11T17:06:38Z","publisher":"IEEE","status":"public","publication":"38th IEEE VLSI Test Symposium (VTS)","type":"conference","language":[{"iso":"eng"}],"department":[{"_id":"48"}],"user_id":"209","_id":"29200"}]