[{"issue":"4","year":"2015","citation":{"apa":"Huang, Z., Liang, H., &#38; Hellebrand, S. (2015). A High Performance SEU Tolerant Latch. <i>Journal of Electronic Testing - Theory and Applications (JETTA)</i>, <i>31</i>(4), 349–359.","short":"Z. Huang, H. Liang, S. Hellebrand, Journal of Electronic Testing - Theory and Applications (JETTA) 31 (2015) 349–359.","bibtex":"@article{Huang_Liang_Hellebrand_2015, title={A High Performance SEU Tolerant Latch}, volume={31}, number={4}, journal={Journal of Electronic Testing - Theory and Applications (JETTA)}, publisher={Springer}, author={Huang, Zhengfeng and Liang, Huaguo and Hellebrand, Sybille}, year={2015}, pages={349–359} }","mla":"Huang, Zhengfeng, et al. “A High Performance SEU Tolerant Latch.” <i>Journal of Electronic Testing - Theory and Applications (JETTA)</i>, vol. 31, no. 4, Springer, 2015, pp. 349–59.","ieee":"Z. Huang, H. Liang, and S. Hellebrand, “A High Performance SEU Tolerant Latch,” <i>Journal of Electronic Testing - Theory and Applications (JETTA)</i>, vol. 31, no. 4, pp. 349–359, 2015.","chicago":"Huang, Zhengfeng, Huaguo Liang, and Sybille Hellebrand. “A High Performance SEU Tolerant Latch.” <i>Journal of Electronic Testing - Theory and Applications (JETTA)</i> 31, no. 4 (2015): 349–59.","ama":"Huang Z, Liang H, Hellebrand S. A High Performance SEU Tolerant Latch. <i>Journal of Electronic Testing - Theory and Applications (JETTA)</i>. 2015;31(4):349-359."},"page":"349-359","intvolume":"        31","publisher":"Springer","date_updated":"2022-01-06T06:51:27Z","author":[{"full_name":"Huang, Zhengfeng","last_name":"Huang","first_name":"Zhengfeng"},{"first_name":"Huaguo","full_name":"Liang, Huaguo","last_name":"Liang"},{"first_name":"Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille"}],"date_created":"2019-08-28T11:48:55Z","volume":31,"title":"A High Performance SEU Tolerant Latch","type":"journal_article","publication":"Journal of Electronic Testing - Theory and Applications (JETTA)","status":"public","_id":"13056","user_id":"209","department":[{"_id":"48"}],"language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"keyword":["Workshop"],"department":[{"_id":"48"}],"user_id":"659","_id":"13077","status":"public","type":"misc","title":"Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler","author":[{"first_name":"Sybille","full_name":"Hellebrand, Sybille","id":"209","last_name":"Hellebrand","orcid":"0000-0002-3717-3939"},{"first_name":"Thomas","full_name":"Indlekofer, Thomas","last_name":"Indlekofer"},{"id":"10935","full_name":"Kampmann, Matthias","last_name":"Kampmann","first_name":"Matthias"},{"last_name":"Kochte","full_name":"Kochte, Michael","first_name":"Michael"},{"first_name":"Chang","last_name":"Liu","full_name":"Liu, Chang"},{"full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich","first_name":"Hans-Joachim"}],"date_created":"2019-08-28T12:05:44Z","date_updated":"2022-01-06T06:51:28Z","citation":{"ama":"Hellebrand S, Indlekofer T, Kampmann M, Kochte M, Liu C, Wunderlich H-J. <i>Effiziente Auswahl von Testfrequenzen Für Den Test Kleiner Verzögerungsfehler</i>. 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany; 2015.","ieee":"S. Hellebrand, T. Indlekofer, M. Kampmann, M. Kochte, C. Liu, and H.-J. Wunderlich, <i>Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler</i>. 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015.","chicago":"Hellebrand, Sybille, Thomas Indlekofer, Matthias Kampmann, Michael Kochte, Chang Liu, and Hans-Joachim Wunderlich. <i>Effiziente Auswahl von Testfrequenzen Für Den Test Kleiner Verzögerungsfehler</i>. 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015.","apa":"Hellebrand, S., Indlekofer, T., Kampmann, M., Kochte, M., Liu, C., &#38; Wunderlich, H.-J. (2015). <i>Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler</i>. 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany.","mla":"Hellebrand, Sybille, et al. <i>Effiziente Auswahl von Testfrequenzen Für Den Test Kleiner Verzögerungsfehler</i>. 2015.","bibtex":"@book{Hellebrand_Indlekofer_Kampmann_Kochte_Liu_Wunderlich_2015, place={27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany}, title={Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler}, author={Hellebrand, Sybille and Indlekofer, Thomas and Kampmann, Matthias and Kochte, Michael and Liu, Chang and Wunderlich, Hans-Joachim}, year={2015} }","short":"S. Hellebrand, T. Indlekofer, M. Kampmann, M. Kochte, C. Liu, H.-J. Wunderlich, Effiziente Auswahl von Testfrequenzen Für Den Test Kleiner Verzögerungsfehler, 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015."},"place":"27. Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\" (TuZ'15), Bad Urach, Germany","year":"2015"},{"language":[{"iso":"eng"}],"extern":"1","_id":"29465","department":[{"_id":"48"}],"user_id":"78614","abstract":[{"lang":"eng","text":"Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of hardware aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes in combinational clouds between pipeline stages or combinational parts of a sequential circuit to place hardware monitors that can effectively provide aging information of various components of a modern digital system. In order to implement the node selection procedure, we propose an object-oriented model. Object-oriented model of a circuit along with a probabilistic and logical simulation engine that we have developed can effectively be used for implementation and also fast evaluation of the proposed node selection mechanism. The proposed object-oriented C+ + models can be integrated into a SystemC RTL model making it possible to perform mixed-level simulation, and integrated evaluation of a complete system. We have applied our proposed scheme to several processors including MIPS, ARM, ALPHA and MiniRISC and have looked at its effectiveness for these processors."}],"status":"public","publication":"2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","type":"conference","title":"Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation","doi":"10.1109/dtis.2015.7127373","publisher":"IEEE","date_updated":"2023-08-02T11:35:56Z","author":[{"first_name":"Somayeh","id":"78614","full_name":"Sadeghi-Kohan, Somayeh","orcid":"https://orcid.org/0000-0001-7246-0610","last_name":"Sadeghi-Kohan"},{"first_name":"Arezoo","full_name":"Kamran, Arezoo","last_name":"Kamran"},{"first_name":"Farnaz","last_name":"Forooghifar","full_name":"Forooghifar, Farnaz"},{"first_name":"Zainalabedin","full_name":"Navabi, Zainalabedin","last_name":"Navabi"}],"date_created":"2022-01-19T13:51:35Z","year":"2015","citation":{"ama":"Sadeghi-Kohan S, Kamran A, Forooghifar F, Navabi Z. Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation. In: <i>2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS)</i>. IEEE; 2015. doi:<a href=\"https://doi.org/10.1109/dtis.2015.7127373\">10.1109/dtis.2015.7127373</a>","chicago":"Sadeghi-Kohan, Somayeh, Arezoo Kamran, Farnaz Forooghifar, and Zainalabedin Navabi. “Aging in Digital Circuits and Age Monitoring: Object-Oriented Modeling and Evaluation.” In <i>2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS)</i>. IEEE, 2015. <a href=\"https://doi.org/10.1109/dtis.2015.7127373\">https://doi.org/10.1109/dtis.2015.7127373</a>.","ieee":"S. Sadeghi-Kohan, A. Kamran, F. Forooghifar, and Z. Navabi, “Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation,” 2015, doi: <a href=\"https://doi.org/10.1109/dtis.2015.7127373\">10.1109/dtis.2015.7127373</a>.","apa":"Sadeghi-Kohan, S., Kamran, A., Forooghifar, F., &#38; Navabi, Z. (2015). Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation. <i>2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS)</i>. <a href=\"https://doi.org/10.1109/dtis.2015.7127373\">https://doi.org/10.1109/dtis.2015.7127373</a>","short":"S. Sadeghi-Kohan, A. Kamran, F. Forooghifar, Z. Navabi, in: 2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015.","bibtex":"@inproceedings{Sadeghi-Kohan_Kamran_Forooghifar_Navabi_2015, title={Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation}, DOI={<a href=\"https://doi.org/10.1109/dtis.2015.7127373\">10.1109/dtis.2015.7127373</a>}, booktitle={2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Kamran, Arezoo and Forooghifar, Farnaz and Navabi, Zainalabedin}, year={2015} }","mla":"Sadeghi-Kohan, Somayeh, et al. “Aging in Digital Circuits and Age Monitoring: Object-Oriented Modeling and Evaluation.” <i>2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS)</i>, IEEE, 2015, doi:<a href=\"https://doi.org/10.1109/dtis.2015.7127373\">10.1109/dtis.2015.7127373</a>."},"publication_status":"published"},{"doi":"10.1109/dtis.2015.7127368","title":"Online self adjusting progressive age monitoring of timing variations","author":[{"first_name":"Somayeh","full_name":"Sadeghi-Kohan, Somayeh","id":"78614","last_name":"Sadeghi-Kohan","orcid":"https://orcid.org/0000-0001-7246-0610"},{"last_name":"Kamal","full_name":"Kamal, Mehdi","first_name":"Mehdi"},{"first_name":"John","full_name":"McNeil, John","last_name":"McNeil"},{"last_name":"Prinetto","full_name":"Prinetto, Paolo","first_name":"Paolo"},{"full_name":"Navabi, Zain","last_name":"Navabi","first_name":"Zain"}],"date_created":"2022-01-19T13:52:32Z","publisher":"IEEE","date_updated":"2023-08-02T11:36:58Z","citation":{"ieee":"S. Sadeghi-Kohan, M. Kamal, J. McNeil, P. Prinetto, and Z. Navabi, “Online self adjusting progressive age monitoring of timing variations,” 2015, doi: <a href=\"https://doi.org/10.1109/dtis.2015.7127368\">10.1109/dtis.2015.7127368</a>.","chicago":"Sadeghi-Kohan, Somayeh, Mehdi Kamal, John McNeil, Paolo Prinetto, and Zain Navabi. “Online Self Adjusting Progressive Age Monitoring of Timing Variations.” In <i>2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS)</i>. IEEE, 2015. <a href=\"https://doi.org/10.1109/dtis.2015.7127368\">https://doi.org/10.1109/dtis.2015.7127368</a>.","ama":"Sadeghi-Kohan S, Kamal M, McNeil J, Prinetto P, Navabi Z. Online self adjusting progressive age monitoring of timing variations. In: <i>2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS)</i>. IEEE; 2015. doi:<a href=\"https://doi.org/10.1109/dtis.2015.7127368\">10.1109/dtis.2015.7127368</a>","bibtex":"@inproceedings{Sadeghi-Kohan_Kamal_McNeil_Prinetto_Navabi_2015, title={Online self adjusting progressive age monitoring of timing variations}, DOI={<a href=\"https://doi.org/10.1109/dtis.2015.7127368\">10.1109/dtis.2015.7127368</a>}, booktitle={2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Kamal, Mehdi and McNeil, John and Prinetto, Paolo and Navabi, Zain}, year={2015} }","short":"S. Sadeghi-Kohan, M. Kamal, J. McNeil, P. Prinetto, Z. Navabi, in: 2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015.","mla":"Sadeghi-Kohan, Somayeh, et al. “Online Self Adjusting Progressive Age Monitoring of Timing Variations.” <i>2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS)</i>, IEEE, 2015, doi:<a href=\"https://doi.org/10.1109/dtis.2015.7127368\">10.1109/dtis.2015.7127368</a>.","apa":"Sadeghi-Kohan, S., Kamal, M., McNeil, J., Prinetto, P., &#38; Navabi, Z. (2015). Online self adjusting progressive age monitoring of timing variations. <i>2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS)</i>. <a href=\"https://doi.org/10.1109/dtis.2015.7127368\">https://doi.org/10.1109/dtis.2015.7127368</a>"},"year":"2015","publication_status":"published","extern":"1","language":[{"iso":"eng"}],"department":[{"_id":"48"}],"user_id":"78614","_id":"29466","status":"public","abstract":[{"text":"Transistor and interconnect wearout is accelerated with transistor scaling that results in timing variations. Progressive age measurement of a circuit can help a better prevention mechanism for reducing more aging. This requires age monitors that collect progressive age information of the circuit. This paper focuses on monitor structures for implementation of progressive age detection. The monitors are self-adjusting that they adjust themselves to detect progressive changes in the timing of a circuit. Furthermore, the monitors are designed for low hardware overhead, and certainty in reported timing changes.","lang":"eng"}],"publication":"2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","type":"conference"},{"status":"public","publication":"IEEE International Test Conference (ITC'14)","type":"conference","language":[{"iso":"eng"}],"department":[{"_id":"48"}],"user_id":"209","_id":"12977","citation":{"ieee":"S. Hellebrand, T. Indlekofer, M. Kampmann, M. A. Kochte, C. Liu, and H.-J. Wunderlich, “FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects,” in <i>IEEE International Test Conference (ITC’14)</i>, 2014.","chicago":"Hellebrand, Sybille, Thomas Indlekofer, Matthias Kampmann, Michael A. Kochte, Chang Liu, and Hans-Joachim Wunderlich. “FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects.” In <i>IEEE International Test Conference (ITC’14)</i>. Seattle, Washington, USA: IEEE, 2014. <a href=\"https://doi.org/10.1109/test.2014.7035360\">https://doi.org/10.1109/test.2014.7035360</a>.","ama":"Hellebrand S, Indlekofer T, Kampmann M, A. Kochte M, Liu C, Wunderlich H-J. FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects. In: <i>IEEE International Test Conference (ITC’14)</i>. Seattle, Washington, USA: IEEE; 2014. doi:<a href=\"https://doi.org/10.1109/test.2014.7035360\">10.1109/test.2014.7035360</a>","short":"S. Hellebrand, T. Indlekofer, M. Kampmann, M. A. Kochte, C. Liu, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’14), IEEE, Seattle, Washington, USA, 2014.","bibtex":"@inproceedings{Hellebrand_Indlekofer_Kampmann_A. Kochte_Liu_Wunderlich_2014, place={Seattle, Washington, USA}, title={FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects}, DOI={<a href=\"https://doi.org/10.1109/test.2014.7035360\">10.1109/test.2014.7035360</a>}, booktitle={IEEE International Test Conference (ITC’14)}, publisher={IEEE}, author={Hellebrand, Sybille and Indlekofer, Thomas and Kampmann, Matthias and A. Kochte, Michael and Liu, Chang and Wunderlich, Hans-Joachim}, year={2014} }","mla":"Hellebrand, Sybille, et al. “FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects.” <i>IEEE International Test Conference (ITC’14)</i>, IEEE, 2014, doi:<a href=\"https://doi.org/10.1109/test.2014.7035360\">10.1109/test.2014.7035360</a>.","apa":"Hellebrand, S., Indlekofer, T., Kampmann, M., A. Kochte, M., Liu, C., &#38; Wunderlich, H.-J. (2014). FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects. In <i>IEEE International Test Conference (ITC’14)</i>. Seattle, Washington, USA: IEEE. <a href=\"https://doi.org/10.1109/test.2014.7035360\">https://doi.org/10.1109/test.2014.7035360</a>"},"year":"2014","place":"Seattle, Washington, USA","doi":"10.1109/test.2014.7035360","title":"FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects","author":[{"first_name":"Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","full_name":"Hellebrand, Sybille","id":"209"},{"first_name":"Thomas","full_name":"Indlekofer, Thomas","last_name":"Indlekofer"},{"id":"10935","full_name":"Kampmann, Matthias","last_name":"Kampmann","first_name":"Matthias"},{"first_name":"Michael","last_name":"A. Kochte","full_name":"A. Kochte, Michael"},{"first_name":"Chang","last_name":"Liu","full_name":"Liu, Chang"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"}],"date_created":"2019-08-28T09:04:45Z","publisher":"IEEE","date_updated":"2022-01-06T06:51:27Z"},{"department":[{"_id":"48"}],"user_id":"209","_id":"13054","language":[{"iso":"eng"}],"publication":"DeGruyter Journal on Information Technology (it)","type":"journal_article","status":"public","volume":56,"author":[{"last_name":"Hellebrand","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille","first_name":"Sybille"},{"last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim","first_name":"Hans-Joachim"}],"date_created":"2019-08-28T11:48:13Z","publisher":"DeGruyter","date_updated":"2022-01-06T06:51:27Z","title":"SAT-Based ATPG beyond Stuck-at Fault Testing","issue":"4","page":"165-172","intvolume":"        56","citation":{"mla":"Hellebrand, Sybille, and Hans-Joachim Wunderlich. “SAT-Based ATPG beyond Stuck-at Fault Testing.” <i>DeGruyter Journal on Information Technology (It)</i>, vol. 56, no. 4, DeGruyter, 2014, pp. 165–72.","short":"S. Hellebrand, H.-J. Wunderlich, DeGruyter Journal on Information Technology (It) 56 (2014) 165–172.","bibtex":"@article{Hellebrand_Wunderlich_2014, title={SAT-Based ATPG beyond Stuck-at Fault Testing}, volume={56}, number={4}, journal={DeGruyter Journal on Information Technology (it)}, publisher={DeGruyter}, author={Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2014}, pages={165–172} }","apa":"Hellebrand, S., &#38; Wunderlich, H.-J. (2014). SAT-Based ATPG beyond Stuck-at Fault Testing. <i>DeGruyter Journal on Information Technology (It)</i>, <i>56</i>(4), 165–172.","chicago":"Hellebrand, Sybille, and Hans-Joachim Wunderlich. “SAT-Based ATPG beyond Stuck-at Fault Testing.” <i>DeGruyter Journal on Information Technology (It)</i> 56, no. 4 (2014): 165–72.","ieee":"S. Hellebrand and H.-J. Wunderlich, “SAT-Based ATPG beyond Stuck-at Fault Testing,” <i>DeGruyter Journal on Information Technology (it)</i>, vol. 56, no. 4, pp. 165–172, 2014.","ama":"Hellebrand S, Wunderlich H-J. SAT-Based ATPG beyond Stuck-at Fault Testing. <i>DeGruyter Journal on Information Technology (it)</i>. 2014;56(4):165-172."},"year":"2014"},{"status":"public","publication":"Journal of Electronic Testing - Theory and Applications (JETTA)","type":"journal_article","language":[{"iso":"eng"}],"_id":"13055","department":[{"_id":"48"}],"user_id":"209","year":"2014","page":"527-540","intvolume":"        30","citation":{"ama":"Rodriguez Gomez L, Cook A, Indlekofer T, Hellebrand S, Wunderlich H-J. Adaptive Bayesian Diagnosis of Intermittent Faults. <i>Journal of Electronic Testing - Theory and Applications (JETTA)</i>. 2014;30(5):527-540.","chicago":"Rodriguez Gomez, Laura, Alejandro Cook, Thomas Indlekofer, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Adaptive Bayesian Diagnosis of Intermittent Faults.” <i>Journal of Electronic Testing - Theory and Applications (JETTA)</i> 30, no. 5 (2014): 527–40.","ieee":"L. Rodriguez Gomez, A. Cook, T. Indlekofer, S. Hellebrand, and H.-J. Wunderlich, “Adaptive Bayesian Diagnosis of Intermittent Faults,” <i>Journal of Electronic Testing - Theory and Applications (JETTA)</i>, vol. 30, no. 5, pp. 527–540, 2014.","mla":"Rodriguez Gomez, Laura, et al. “Adaptive Bayesian Diagnosis of Intermittent Faults.” <i>Journal of Electronic Testing - Theory and Applications (JETTA)</i>, vol. 30, no. 5, Springer, 2014, pp. 527–40.","short":"L. Rodriguez Gomez, A. Cook, T. Indlekofer, S. Hellebrand, H.-J. Wunderlich, Journal of Electronic Testing - Theory and Applications (JETTA) 30 (2014) 527–540.","bibtex":"@article{Rodriguez Gomez_Cook_Indlekofer_Hellebrand_Wunderlich_2014, title={Adaptive Bayesian Diagnosis of Intermittent Faults}, volume={30}, number={5}, journal={Journal of Electronic Testing - Theory and Applications (JETTA)}, publisher={Springer}, author={Rodriguez Gomez, Laura and Cook, Alejandro and Indlekofer, Thomas and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2014}, pages={527–540} }","apa":"Rodriguez Gomez, L., Cook, A., Indlekofer, T., Hellebrand, S., &#38; Wunderlich, H.-J. (2014). Adaptive Bayesian Diagnosis of Intermittent Faults. <i>Journal of Electronic Testing - Theory and Applications (JETTA)</i>, <i>30</i>(5), 527–540."},"issue":"5","title":"Adaptive Bayesian Diagnosis of Intermittent Faults","date_updated":"2022-01-06T06:51:27Z","publisher":"Springer","volume":30,"date_created":"2019-08-28T11:48:33Z","author":[{"first_name":"Laura","last_name":"Rodriguez Gomez","full_name":"Rodriguez Gomez, Laura"},{"first_name":"Alejandro","full_name":"Cook, Alejandro","last_name":"Cook"},{"first_name":"Thomas","last_name":"Indlekofer","full_name":"Indlekofer, Thomas"},{"first_name":"Sybille","full_name":"Hellebrand, Sybille","id":"209","last_name":"Hellebrand","orcid":"0000-0002-3717-3939"},{"last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim","first_name":"Hans-Joachim"}]},{"department":[{"_id":"48"}],"user_id":"78614","_id":"46266","language":[{"iso":"eng"}],"extern":"1","keyword":["Computational Theory and Mathematics","Hardware and Architecture","Theoretical Computer Science","Software"],"publication":"IEEE Transactions on Computers","type":"journal_article","status":"public","author":[{"first_name":"Bijan","full_name":"Alizadeh, Bijan","last_name":"Alizadeh"},{"last_name":"Behnam","full_name":"Behnam, Payman","first_name":"Payman"},{"last_name":"Sadeghi-Kohan","orcid":"https://orcid.org/0000-0001-7246-0610","full_name":"Sadeghi-Kohan, Somayeh","id":"78614","first_name":"Somayeh"}],"date_created":"2023-08-02T11:15:22Z","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","date_updated":"2023-08-02T11:32:37Z","doi":"10.1109/tc.2014.2329687","title":"A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs","publication_identifier":{"issn":["0018-9340"]},"publication_status":"published","page":"1-1","citation":{"mla":"Alizadeh, Bijan, et al. “A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs.” <i>IEEE Transactions on Computers</i>, Institute of Electrical and Electronics Engineers (IEEE), 2014, pp. 1–1, doi:<a href=\"https://doi.org/10.1109/tc.2014.2329687\">10.1109/tc.2014.2329687</a>.","bibtex":"@article{Alizadeh_Behnam_Sadeghi-Kohan_2014, title={A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs}, DOI={<a href=\"https://doi.org/10.1109/tc.2014.2329687\">10.1109/tc.2014.2329687</a>}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Alizadeh, Bijan and Behnam, Payman and Sadeghi-Kohan, Somayeh}, year={2014}, pages={1–1} }","short":"B. Alizadeh, P. Behnam, S. Sadeghi-Kohan, IEEE Transactions on Computers (2014) 1–1.","apa":"Alizadeh, B., Behnam, P., &#38; Sadeghi-Kohan, S. (2014). A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. <i>IEEE Transactions on Computers</i>, 1–1. <a href=\"https://doi.org/10.1109/tc.2014.2329687\">https://doi.org/10.1109/tc.2014.2329687</a>","ieee":"B. Alizadeh, P. Behnam, and S. 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