[{"language":[{"iso":"eng"}],"_id":"13052","user_id":"209","department":[{"_id":"48"}],"status":"public","type":"journal_article","publication":"SCIENCE CHINA Information Sciences, Science China Press, co-published with Springer","title":"Variation-Aware Fault Modeling","date_updated":"2022-05-11T16:19:14Z","date_created":"2019-08-28T11:47:14Z","author":[{"first_name":"Fabian","last_name":"Hopsch","full_name":"Hopsch, Fabian"},{"full_name":"Becker, Bernd","last_name":"Becker","first_name":"Bernd"},{"last_name":"Hellebrand","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","id":"209","first_name":"Sybille"},{"first_name":"Ilia","last_name":"Polian","full_name":"Polian, Ilia"},{"last_name":"Straube","full_name":"Straube, Bernd","first_name":"Bernd"},{"first_name":"Wolfgang","last_name":"Vermeiren","full_name":"Vermeiren, Wolfgang"},{"full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich","first_name":"Hans-Joachim"}],"volume":54,"year":"2011","citation":{"chicago":"Hopsch, Fabian, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, and Hans-Joachim Wunderlich. “Variation-Aware Fault Modeling.” <i>SCIENCE CHINA Information Sciences, Science China Press, Co-Published with Springer</i> 54, no. 4 (2011): 1813–26.","ieee":"F. Hopsch <i>et al.</i>, “Variation-Aware Fault Modeling,” <i>SCIENCE CHINA Information Sciences, Science China Press, co-published with Springer</i>, vol. 54, no. 4, pp. 1813–1826, 2011.","ama":"Hopsch F, Becker B, Hellebrand S, et al. Variation-Aware Fault Modeling. <i>SCIENCE CHINA Information Sciences, Science China Press, co-published with Springer</i>. 2011;54(4):1813-1826.","apa":"Hopsch, F., Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., &#38; Wunderlich, H.-J. (2011). Variation-Aware Fault Modeling. <i>SCIENCE CHINA Information Sciences, Science China Press, Co-Published with Springer</i>, <i>54</i>(4), 1813–1826.","bibtex":"@article{Hopsch_Becker_Hellebrand_Polian_Straube_Vermeiren_Wunderlich_2011, title={Variation-Aware Fault Modeling}, volume={54}, number={4}, journal={SCIENCE CHINA Information Sciences, Science China Press, co-published with Springer}, author={Hopsch, Fabian and Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans-Joachim}, year={2011}, pages={1813–1826} }","short":"F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, SCIENCE CHINA Information Sciences, Science China Press, Co-Published with Springer 54 (2011) 1813–1826.","mla":"Hopsch, Fabian, et al. “Variation-Aware Fault Modeling.” <i>SCIENCE CHINA Information Sciences, Science China Press, Co-Published with Springer</i>, vol. 54, no. 4, 2011, pp. 1813–26."},"page":"1813-1826","intvolume":"        54","issue":"4"},{"status":"public","publication":"2010 East-West Design &amp; Test Symposium (EWDTS)","type":"conference","language":[{"iso":"eng"}],"extern":"1","_id":"46272","department":[{"_id":"48"}],"user_id":"78614","year":"2011","citation":{"short":"A. Kamran, N. Nemati, S. Sadeghi-Kohan, Z. Navabi, in: 2010 East-West Design &#38;amp; Test Symposium (EWDTS), IEEE, 2011.","bibtex":"@inproceedings{Kamran_Nemati_Sadeghi-Kohan_Navabi_2011, title={Virtual tester development using HDL/PLI}, DOI={<a href=\"https://doi.org/10.1109/ewdts.2010.5742156\">10.1109/ewdts.2010.5742156</a>}, booktitle={2010 East-West Design &#38;amp; Test Symposium (EWDTS)}, publisher={IEEE}, author={Kamran, Arezoo and Nemati, Nastaran and Sadeghi-Kohan, Somayeh and Navabi, Zainalabedin}, year={2011} }","mla":"Kamran, Arezoo, et al. “Virtual Tester Development Using HDL/PLI.” <i>2010 East-West Design &#38;amp; Test Symposium (EWDTS)</i>, IEEE, 2011, doi:<a href=\"https://doi.org/10.1109/ewdts.2010.5742156\">10.1109/ewdts.2010.5742156</a>.","apa":"Kamran, A., Nemati, N., Sadeghi-Kohan, S., &#38; Navabi, Z. (2011). Virtual tester development using HDL/PLI. <i>2010 East-West Design &#38;amp; Test Symposium (EWDTS)</i>. <a href=\"https://doi.org/10.1109/ewdts.2010.5742156\">https://doi.org/10.1109/ewdts.2010.5742156</a>","ieee":"A. Kamran, N. Nemati, S. Sadeghi-Kohan, and Z. Navabi, “Virtual tester development using HDL/PLI,” 2011, doi: <a href=\"https://doi.org/10.1109/ewdts.2010.5742156\">10.1109/ewdts.2010.5742156</a>.","chicago":"Kamran, Arezoo, Nastaran Nemati, Somayeh Sadeghi-Kohan, and Zainalabedin Navabi. “Virtual Tester Development Using HDL/PLI.” In <i>2010 East-West Design &#38;amp; Test Symposium (EWDTS)</i>. IEEE, 2011. <a href=\"https://doi.org/10.1109/ewdts.2010.5742156\">https://doi.org/10.1109/ewdts.2010.5742156</a>.","ama":"Kamran A, Nemati N, Sadeghi-Kohan S, Navabi Z. Virtual tester development using HDL/PLI. In: <i>2010 East-West Design &#38;amp; Test Symposium (EWDTS)</i>. IEEE; 2011. doi:<a href=\"https://doi.org/10.1109/ewdts.2010.5742156\">10.1109/ewdts.2010.5742156</a>"},"publication_status":"published","title":"Virtual tester development using HDL/PLI","doi":"10.1109/ewdts.2010.5742156","publisher":"IEEE","date_updated":"2023-08-02T11:33:46Z","author":[{"first_name":"Arezoo","last_name":"Kamran","full_name":"Kamran, Arezoo"},{"full_name":"Nemati, Nastaran","last_name":"Nemati","first_name":"Nastaran"},{"first_name":"Somayeh","full_name":"Sadeghi-Kohan, Somayeh","id":"78614","last_name":"Sadeghi-Kohan","orcid":"https://orcid.org/0000-0001-7246-0610"},{"first_name":"Zainalabedin","full_name":"Navabi, Zainalabedin","last_name":"Navabi"}],"date_created":"2023-08-02T11:21:02Z"},{"keyword":["WORKSHOP"],"language":[{"iso":"eng"}],"_id":"10670","user_id":"659","department":[{"_id":"48"}],"status":"public","type":"misc","title":"Testdatenkompression mit Hilfe der Netzwerkinfrastruktur","date_updated":"2022-01-06T06:50:49Z","date_created":"2019-07-10T11:17:36Z","author":[{"full_name":"Fröse, Viktor","last_name":"Fröse","first_name":"Viktor"},{"first_name":"Rüdiger","last_name":"Ibers","full_name":"Ibers, Rüdiger","id":"659"},{"first_name":"Sybille","full_name":"Hellebrand, Sybille","id":"209","orcid":"0000-0002-3717-3939","last_name":"Hellebrand"}],"year":"2010","place":"22. Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\" (TuZ'10), Paderborn, Germany","citation":{"short":"V. Fröse, R. Ibers, S. Hellebrand, Testdatenkompression Mit Hilfe Der Netzwerkinfrastruktur, 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010.","bibtex":"@book{Fröse_Ibers_Hellebrand_2010, place={22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany}, title={Testdatenkompression mit Hilfe der Netzwerkinfrastruktur}, author={Fröse, Viktor and Ibers, Rüdiger and Hellebrand, Sybille}, year={2010} }","mla":"Fröse, Viktor, et al. <i>Testdatenkompression Mit Hilfe Der Netzwerkinfrastruktur</i>. 2010.","apa":"Fröse, V., Ibers, R., &#38; Hellebrand, S. (2010). <i>Testdatenkompression mit Hilfe der Netzwerkinfrastruktur</i>. 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany.","ama":"Fröse V, Ibers R, Hellebrand S. <i>Testdatenkompression Mit Hilfe Der Netzwerkinfrastruktur</i>. 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany; 2010.","chicago":"Fröse, Viktor, Rüdiger Ibers, and Sybille Hellebrand. <i>Testdatenkompression Mit Hilfe Der Netzwerkinfrastruktur</i>. 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010.","ieee":"V. Fröse, R. Ibers, and S. Hellebrand, <i>Testdatenkompression mit Hilfe der Netzwerkinfrastruktur</i>. 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010."}},{"title":"Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits","doi":"10.1109/dsnw.2010.5542612","date_updated":"2022-01-06T06:51:27Z","publisher":"IEEE","author":[{"first_name":"Bernd","last_name":"Becker","full_name":"Becker, Bernd"},{"last_name":"Hellebrand","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","id":"209","first_name":"Sybille"},{"last_name":"Polian","full_name":"Polian, Ilia","first_name":"Ilia"},{"first_name":"Bernd","full_name":"Straube, Bernd","last_name":"Straube"},{"first_name":"Wolfgang","full_name":"Vermeiren, Wolfgang","last_name":"Vermeiren"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"}],"date_created":"2019-08-28T09:22:53Z","year":"2010","place":"Chicago, IL, USA","citation":{"ama":"Becker B, Hellebrand S, Polian I, Straube B, Vermeiren W, Wunderlich H-J. Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In: <i>40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10)</i>. Chicago, IL, USA: IEEE; 2010. doi:<a href=\"https://doi.org/10.1109/dsnw.2010.5542612\">10.1109/dsnw.2010.5542612</a>","ieee":"B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, and H.-J. Wunderlich, “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits,” in <i>40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10)</i>, 2010.","chicago":"Becker, Bernd, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, and Hans-Joachim Wunderlich. “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits.” In <i>40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10)</i>. Chicago, IL, USA: IEEE, 2010. <a href=\"https://doi.org/10.1109/dsnw.2010.5542612\">https://doi.org/10.1109/dsnw.2010.5542612</a>.","mla":"Becker, Bernd, et al. “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits.” <i>40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10)</i>, IEEE, 2010, doi:<a href=\"https://doi.org/10.1109/dsnw.2010.5542612\">10.1109/dsnw.2010.5542612</a>.","bibtex":"@inproceedings{Becker_Hellebrand_Polian_Straube_Vermeiren_Wunderlich_2010, place={Chicago, IL, USA}, title={Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits}, DOI={<a href=\"https://doi.org/10.1109/dsnw.2010.5542612\">10.1109/dsnw.2010.5542612</a>}, booktitle={40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10)}, publisher={IEEE}, author={Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans-Joachim}, year={2010} }","short":"B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10), IEEE, Chicago, IL, USA, 2010.","apa":"Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., &#38; Wunderlich, H.-J. (2010). Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In <i>40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10)</i>. Chicago, IL, USA: IEEE. <a href=\"https://doi.org/10.1109/dsnw.2010.5542612\">https://doi.org/10.1109/dsnw.2010.5542612</a>"},"language":[{"iso":"eng"}],"_id":"12987","user_id":"209","department":[{"_id":"48"}],"status":"public","type":"conference","publication":"40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W'10)"},{"department":[{"_id":"48"}],"user_id":"659","_id":"13051","language":[{"iso":"eng"}],"publication":"4. GMM/GI/ITG-Fachtagung \"Zuverlässigkeit und Entwurf\"","type":"conference","status":"public","date_created":"2019-08-28T11:46:41Z","author":[{"first_name":"Marc","full_name":"Hunger, Marc","last_name":"Hunger"},{"first_name":"Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","id":"209"}],"date_updated":"2022-01-06T06:51:27Z","title":"Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz","page":"81-88","citation":{"bibtex":"@inproceedings{Hunger_Hellebrand_2010, place={Wildbad Kreuth, Germany}, title={Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz}, booktitle={4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf”}, author={Hunger, Marc and Hellebrand, Sybille}, year={2010}, pages={81–88} }","short":"M. Hunger, S. Hellebrand, in: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Wildbad Kreuth, Germany, 2010, pp. 81–88.","mla":"Hunger, Marc, and Sybille Hellebrand. “Ausbeute Und Fehlertoleranz Bei Dreifach Modularer Redundanz.” <i>4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,”</i> 2010, pp. 81–88.","apa":"Hunger, M., &#38; Hellebrand, S. (2010). Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz. In <i>4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf”</i> (pp. 81–88). Wildbad Kreuth, Germany.","ama":"Hunger M, Hellebrand S. Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz. In: <i>4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”</i> Wildbad Kreuth, Germany; 2010:81-88.","ieee":"M. Hunger and S. Hellebrand, “Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz,” in <i>4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf,”</i> 2010, pp. 81–88.","chicago":"Hunger, Marc, and Sybille Hellebrand. “Ausbeute Und Fehlertoleranz Bei Dreifach Modularer Redundanz.” In <i>4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,”</i> 81–88. Wildbad Kreuth, Germany, 2010."},"year":"2010","place":"Wildbad Kreuth, Germany"},{"status":"public","type":"misc","language":[{"iso":"eng"}],"_id":"13073","department":[{"_id":"48"}],"user_id":"659","place":"Editorial, it 4/2010, pp. 179-180","year":"2010","citation":{"apa":"Hellebrand, S. (2010). <i>Nano-Electronic Systems</i>. Editorial, it 4/2010, pp. 179-180.","mla":"Hellebrand, Sybille. <i>Nano-Electronic Systems</i>. 2010.","short":"S. Hellebrand, Nano-Electronic Systems, Editorial, it 4/2010, pp. 179-180, 2010.","bibtex":"@book{Hellebrand_2010, place={Editorial, it 4/2010, pp. 179-180}, title={Nano-Electronic Systems}, author={Hellebrand, Sybille}, year={2010} }","chicago":"Hellebrand, Sybille. <i>Nano-Electronic Systems</i>. Editorial, it 4/2010, pp. 179-180, 2010.","ieee":"S. Hellebrand, <i>Nano-Electronic Systems</i>. Editorial, it 4/2010, pp. 179-180, 2010.","ama":"Hellebrand S. <i>Nano-Electronic Systems</i>. Editorial, it 4/2010, pp. 179-180; 2010."},"title":"Nano-Electronic Systems","date_updated":"2022-01-06T06:51:28Z","date_created":"2019-08-28T12:01:06Z","author":[{"id":"209","full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","first_name":"Sybille"}]},{"type":"conference","publication":"19th IEEE Asian Test Symposium (ATS'10)","status":"public","_id":"12983","user_id":"209","department":[{"_id":"48"}],"language":[{"iso":"eng"}],"year":"2010","place":"Shanghai, China","citation":{"ama":"Hopsch F, Becker B, Hellebrand S, et al. Variation-Aware Fault Modeling. In: <i>19th IEEE Asian Test Symposium (ATS’10)</i>. IEEE; 2010:87-93. doi:<a href=\"https://doi.org/10.1109/ats.2010.24\">10.1109/ats.2010.24</a>","chicago":"Hopsch, Fabian, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, and Hans-Joachim Wunderlich. “Variation-Aware Fault Modeling.” In <i>19th IEEE Asian Test Symposium (ATS’10)</i>, 87–93. Shanghai, China: IEEE, 2010. <a href=\"https://doi.org/10.1109/ats.2010.24\">https://doi.org/10.1109/ats.2010.24</a>.","ieee":"F. Hopsch <i>et al.</i>, “Variation-Aware Fault Modeling,” in <i>19th IEEE Asian Test Symposium (ATS’10)</i>, 2010, pp. 87–93, doi: <a href=\"https://doi.org/10.1109/ats.2010.24\">10.1109/ats.2010.24</a>.","bibtex":"@inproceedings{Hopsch_Becker_Hellebrand_Polian_Straube_Vermeiren_Wunderlich_2010, place={Shanghai, China}, title={Variation-Aware Fault Modeling}, DOI={<a href=\"https://doi.org/10.1109/ats.2010.24\">10.1109/ats.2010.24</a>}, booktitle={19th IEEE Asian Test Symposium (ATS’10)}, publisher={IEEE}, author={Hopsch, Fabian and Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans-Joachim}, year={2010}, pages={87–93} }","short":"F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: 19th IEEE Asian Test Symposium (ATS’10), IEEE, Shanghai, China, 2010, pp. 87–93.","mla":"Hopsch, Fabian, et al. “Variation-Aware Fault Modeling.” <i>19th IEEE Asian Test Symposium (ATS’10)</i>, IEEE, 2010, pp. 87–93, doi:<a href=\"https://doi.org/10.1109/ats.2010.24\">10.1109/ats.2010.24</a>.","apa":"Hopsch, F., Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., &#38; Wunderlich, H.-J. (2010). Variation-Aware Fault Modeling. <i>19th IEEE Asian Test Symposium (ATS’10)</i>, 87–93. <a href=\"https://doi.org/10.1109/ats.2010.24\">https://doi.org/10.1109/ats.2010.24</a>"},"page":"87-93","publisher":"IEEE","date_updated":"2022-05-11T16:20:07Z","date_created":"2019-08-28T09:20:51Z","author":[{"full_name":"Hopsch, Fabian","last_name":"Hopsch","first_name":"Fabian"},{"full_name":"Becker, Bernd","last_name":"Becker","first_name":"Bernd"},{"last_name":"Hellebrand","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille","first_name":"Sybille"},{"first_name":"Ilia","full_name":"Polian, Ilia","last_name":"Polian"},{"last_name":"Straube","full_name":"Straube, Bernd","first_name":"Bernd"},{"first_name":"Wolfgang","last_name":"Vermeiren","full_name":"Vermeiren, Wolfgang"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"}],"title":"Variation-Aware Fault Modeling","doi":"10.1109/ats.2010.24"},{"page":"480-485","citation":{"bibtex":"@inproceedings{Indlekofer_Schnittger_Hellebrand_2010, place={Amsterdam, The Netherlands}, title={Efficient Test Response Compaction for Robust BIST Using Parity Sequences}, DOI={<a href=\"https://doi.org/10.1109/iccd.2010.5647648\">10.1109/iccd.2010.5647648</a>}, booktitle={28th IEEE International Conference on Computer Design (ICCD’10)}, publisher={IEEE}, author={Indlekofer, Thomas and Schnittger, Michael and Hellebrand, Sybille}, year={2010}, pages={480–485} }","short":"T. Indlekofer, M. Schnittger, S. Hellebrand, in: 28th IEEE International Conference on Computer Design (ICCD’10), IEEE, Amsterdam, The Netherlands, 2010, pp. 480–485.","mla":"Indlekofer, Thomas, et al. “Efficient Test Response Compaction for Robust BIST Using Parity Sequences.” <i>28th IEEE International Conference on Computer Design (ICCD’10)</i>, IEEE, 2010, pp. 480–85, doi:<a href=\"https://doi.org/10.1109/iccd.2010.5647648\">10.1109/iccd.2010.5647648</a>.","apa":"Indlekofer, T., Schnittger, M., &#38; Hellebrand, S. (2010). Efficient Test Response Compaction for Robust BIST Using Parity Sequences. <i>28th IEEE International Conference on Computer Design (ICCD’10)</i>, 480–485. <a href=\"https://doi.org/10.1109/iccd.2010.5647648\">https://doi.org/10.1109/iccd.2010.5647648</a>","chicago":"Indlekofer, Thomas, Michael Schnittger, and Sybille Hellebrand. “Efficient Test Response Compaction for Robust BIST Using Parity Sequences.” In <i>28th IEEE International Conference on Computer Design (ICCD’10)</i>, 480–85. Amsterdam, The Netherlands: IEEE, 2010. <a href=\"https://doi.org/10.1109/iccd.2010.5647648\">https://doi.org/10.1109/iccd.2010.5647648</a>.","ieee":"T. Indlekofer, M. Schnittger, and S. Hellebrand, “Efficient Test Response Compaction for Robust BIST Using Parity Sequences,” in <i>28th IEEE International Conference on Computer Design (ICCD’10)</i>, 2010, pp. 480–485, doi: <a href=\"https://doi.org/10.1109/iccd.2010.5647648\">10.1109/iccd.2010.5647648</a>.","ama":"Indlekofer T, Schnittger M, Hellebrand S. Efficient Test Response Compaction for Robust BIST Using Parity Sequences. In: <i>28th IEEE International Conference on Computer Design (ICCD’10)</i>. IEEE; 2010:480-485. doi:<a href=\"https://doi.org/10.1109/iccd.2010.5647648\">10.1109/iccd.2010.5647648</a>"},"place":"Amsterdam, The Netherlands","year":"2010","doi":"10.1109/iccd.2010.5647648","title":"Efficient Test Response Compaction for Robust BIST Using Parity Sequences","author":[{"first_name":"Thomas","last_name":"Indlekofer","full_name":"Indlekofer, Thomas"},{"last_name":"Schnittger","full_name":"Schnittger, Michael","first_name":"Michael"},{"id":"209","full_name":"Hellebrand, Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","first_name":"Sybille"}],"date_created":"2019-08-28T09:21:55Z","date_updated":"2022-05-11T16:21:12Z","publisher":"IEEE","status":"public","publication":"28th IEEE International Conference on Computer Design (ICCD'10)","type":"conference","language":[{"iso":"eng"}],"department":[{"_id":"48"}],"user_id":"209","_id":"12985"},{"author":[{"first_name":"Marc","last_name":"Hunger","full_name":"Hunger, Marc"},{"first_name":"Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","full_name":"Hellebrand, Sybille","id":"209"}],"date_created":"2019-08-28T09:21:57Z","date_updated":"2022-05-11T16:21:52Z","publisher":"IEEE","doi":"10.1109/dft.2010.19","title":"The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems","citation":{"bibtex":"@inproceedings{Hunger_Hellebrand_2010, place={Kyoto, Japan}, title={The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems}, DOI={<a href=\"https://doi.org/10.1109/dft.2010.19\">10.1109/dft.2010.19</a>}, booktitle={25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10)}, publisher={IEEE}, author={Hunger, Marc and Hellebrand, Sybille}, year={2010}, pages={101–108} }","mla":"Hunger, Marc, and Sybille Hellebrand. “The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems.” <i>25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10)</i>, IEEE, 2010, pp. 101–08, doi:<a href=\"https://doi.org/10.1109/dft.2010.19\">10.1109/dft.2010.19</a>.","short":"M. Hunger, S. Hellebrand, in: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), IEEE, Kyoto, Japan, 2010, pp. 101–108.","apa":"Hunger, M., &#38; Hellebrand, S. (2010). The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. <i>25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10)</i>, 101–108. <a href=\"https://doi.org/10.1109/dft.2010.19\">https://doi.org/10.1109/dft.2010.19</a>","ieee":"M. Hunger and S. Hellebrand, “The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems,” in <i>25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10)</i>, 2010, pp. 101–108, doi: <a href=\"https://doi.org/10.1109/dft.2010.19\">10.1109/dft.2010.19</a>.","chicago":"Hunger, Marc, and Sybille Hellebrand. “The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems.” In <i>25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10)</i>, 101–8. Kyoto, Japan: IEEE, 2010. <a href=\"https://doi.org/10.1109/dft.2010.19\">https://doi.org/10.1109/dft.2010.19</a>.","ama":"Hunger M, Hellebrand S. The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. In: <i>25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10)</i>. IEEE; 2010:101-108. doi:<a href=\"https://doi.org/10.1109/dft.2010.19\">10.1109/dft.2010.19</a>"},"page":"101-108","place":"Kyoto, Japan","year":"2010","user_id":"209","department":[{"_id":"48"}],"_id":"12986","language":[{"iso":"eng"}],"type":"conference","publication":"25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'10)","status":"public"},{"title":"Reusing NoC-Infrastructure for Test Data Compression","doi":"10.1109/vts.2010.5469570","publisher":"IEEE","date_updated":"2022-05-11T16:22:36Z","author":[{"full_name":"Froese, Viktor","last_name":"Froese","first_name":"Viktor"},{"last_name":"Ibers","full_name":"Ibers, Rüdiger","id":"659","first_name":"Rüdiger"},{"full_name":"Hellebrand, Sybille","id":"209","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","first_name":"Sybille"}],"date_created":"2019-08-28T09:22:54Z","place":"Santa Cruz, CA, USA","year":"2010","page":"227-231","citation":{"bibtex":"@inproceedings{Froese_Ibers_Hellebrand_2010, place={Santa Cruz, CA, USA}, title={Reusing NoC-Infrastructure for Test Data Compression}, DOI={<a href=\"https://doi.org/10.1109/vts.2010.5469570\">10.1109/vts.2010.5469570</a>}, booktitle={28th IEEE VLSI Test Symposium (VTS’10)}, publisher={IEEE}, author={Froese, Viktor and Ibers, Rüdiger and Hellebrand, Sybille}, year={2010}, pages={227–231} }","mla":"Froese, Viktor, et al. “Reusing NoC-Infrastructure for Test Data Compression.” <i>28th IEEE VLSI Test Symposium (VTS’10)</i>, IEEE, 2010, pp. 227–31, doi:<a href=\"https://doi.org/10.1109/vts.2010.5469570\">10.1109/vts.2010.5469570</a>.","short":"V. Froese, R. Ibers, S. Hellebrand, in: 28th IEEE VLSI Test Symposium (VTS’10), IEEE, Santa Cruz, CA, USA, 2010, pp. 227–231.","apa":"Froese, V., Ibers, R., &#38; Hellebrand, S. (2010). Reusing NoC-Infrastructure for Test Data Compression. <i>28th IEEE VLSI Test Symposium (VTS’10)</i>, 227–231. <a href=\"https://doi.org/10.1109/vts.2010.5469570\">https://doi.org/10.1109/vts.2010.5469570</a>","chicago":"Froese, Viktor, Rüdiger Ibers, and Sybille Hellebrand. “Reusing NoC-Infrastructure for Test Data Compression.” In <i>28th IEEE VLSI Test Symposium (VTS’10)</i>, 227–31. Santa Cruz, CA, USA: IEEE, 2010. <a href=\"https://doi.org/10.1109/vts.2010.5469570\">https://doi.org/10.1109/vts.2010.5469570</a>.","ieee":"V. Froese, R. Ibers, and S. Hellebrand, “Reusing NoC-Infrastructure for Test Data Compression,” in <i>28th IEEE VLSI Test Symposium (VTS’10)</i>, 2010, pp. 227–231, doi: <a href=\"https://doi.org/10.1109/vts.2010.5469570\">10.1109/vts.2010.5469570</a>.","ama":"Froese V, Ibers R, Hellebrand S. Reusing NoC-Infrastructure for Test Data Compression. In: <i>28th IEEE VLSI Test Symposium (VTS’10)</i>. IEEE; 2010:227-231. doi:<a href=\"https://doi.org/10.1109/vts.2010.5469570\">10.1109/vts.2010.5469570</a>"},"language":[{"iso":"eng"}],"_id":"12988","department":[{"_id":"48"}],"user_id":"209","status":"public","publication":"28th IEEE VLSI Test Symposium (VTS'10)","type":"conference"},{"status":"public","type":"conference","publication":"4th Workshop on Dependable and Secure Nanocomputing (WDSN'10), (Invited Paper)","language":[{"iso":"eng"}],"user_id":"209","department":[{"_id":"48"}],"_id":"13049","citation":{"mla":"Becker, Bernd, et al. “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits.” <i>4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper)</i>, 2010.","short":"B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper), Chicago, IL, USA, 2010.","bibtex":"@inproceedings{Becker_Hellebrand_Polian_Straube_Vermeiren_Wunderlich_2010, place={Chicago, IL, USA}, title={Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits}, booktitle={4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper)}, author={Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans-Joachim}, year={2010} }","apa":"Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., &#38; Wunderlich, H.-J. (2010). Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. <i>4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper)</i>.","chicago":"Becker, Bernd, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, and Hans-Joachim Wunderlich. “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits.” In <i>4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper)</i>. Chicago, IL, USA, 2010.","ieee":"B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, and H.-J. Wunderlich, “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits,” 2010.","ama":"Becker B, Hellebrand S, Polian I, Straube B, Vermeiren W, Wunderlich H-J. Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In: <i>4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper)</i>. ; 2010."},"year":"2010","place":"Chicago, IL, USA","title":"Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits","author":[{"full_name":"Becker, Bernd","last_name":"Becker","first_name":"Bernd"},{"full_name":"Hellebrand, Sybille","id":"209","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","first_name":"Sybille"},{"full_name":"Polian, Ilia","last_name":"Polian","first_name":"Ilia"},{"first_name":"Bernd","last_name":"Straube","full_name":"Straube, Bernd"},{"first_name":"Wolfgang","last_name":"Vermeiren","full_name":"Vermeiren, Wolfgang"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"}],"date_created":"2019-08-28T11:45:36Z","date_updated":"2022-05-11T16:26:18Z"},{"_id":"13050","user_id":"209","department":[{"_id":"48"}],"language":[{"iso":"eng"}],"type":"conference","publication":"4. GMM/GI/ITG-Fachtagung \"Zuverlässigkeit und Entwurf\"","status":"public","date_updated":"2022-05-11T16:25:34Z","date_created":"2019-08-28T11:46:13Z","author":[{"first_name":"Thomas","last_name":"Indlekofer","full_name":"Indlekofer, Thomas"},{"full_name":"Schnittger, Michael","last_name":"Schnittger","first_name":"Michael"},{"last_name":"Hellebrand","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille","first_name":"Sybille"}],"title":"Robuster Selbsttest mit extremer Kompaktierung","year":"2010","place":"Wildbad Kreuth, Germany","citation":{"ama":"Indlekofer T, Schnittger M, Hellebrand S. Robuster Selbsttest mit extremer Kompaktierung. In: <i>4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”</i> ; 2010:17-24.","ieee":"T. Indlekofer, M. Schnittger, and S. Hellebrand, “Robuster Selbsttest mit extremer Kompaktierung,” in <i>4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf,”</i> 2010, pp. 17–24.","chicago":"Indlekofer, Thomas, Michael Schnittger, and Sybille Hellebrand. “Robuster Selbsttest Mit Extremer Kompaktierung.” In <i>4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,”</i> 17–24. Wildbad Kreuth, Germany, 2010.","apa":"Indlekofer, T., Schnittger, M., &#38; Hellebrand, S. (2010). Robuster Selbsttest mit extremer Kompaktierung. <i>4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,”</i> 17–24.","short":"T. Indlekofer, M. Schnittger, S. Hellebrand, in: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Wildbad Kreuth, Germany, 2010, pp. 17–24.","mla":"Indlekofer, Thomas, et al. “Robuster Selbsttest Mit Extremer Kompaktierung.” <i>4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,”</i> 2010, pp. 17–24.","bibtex":"@inproceedings{Indlekofer_Schnittger_Hellebrand_2010, place={Wildbad Kreuth, Germany}, title={Robuster Selbsttest mit extremer Kompaktierung}, booktitle={4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf”}, author={Indlekofer, Thomas and Schnittger, Michael and Hellebrand, Sybille}, year={2010}, pages={17–24} }"},"page":"17-24"},{"publication":"15th IEEE International On-Line Testing Symposium (IOLTS'09","type":"conference","status":"public","_id":"12991","department":[{"_id":"48"}],"user_id":"209","language":[{"iso":"eng"}],"place":"Sesimbra-Lisbon, Portugal","year":"2009","citation":{"ama":"Hunger M, Hellebrand S, Czutro A, Polian I, Becker B. ATPG-Based Grading of Strong Fault-Secureness. In: <i>15th IEEE International On-Line Testing Symposium (IOLTS’09</i>. IEEE; 2009. doi:<a href=\"https://doi.org/10.1109/iolts.2009.5196027\">10.1109/iolts.2009.5196027</a>","ieee":"M. Hunger, S. Hellebrand, A. Czutro, I. Polian, and B. Becker, “ATPG-Based Grading of Strong Fault-Secureness,” 2009, doi: <a href=\"https://doi.org/10.1109/iolts.2009.5196027\">10.1109/iolts.2009.5196027</a>.","chicago":"Hunger, Marc, Sybille Hellebrand, Alejandro Czutro, Ilia Polian, and Bernd Becker. “ATPG-Based Grading of Strong Fault-Secureness.” In <i>15th IEEE International On-Line Testing Symposium (IOLTS’09</i>. Sesimbra-Lisbon, Portugal: IEEE, 2009. <a href=\"https://doi.org/10.1109/iolts.2009.5196027\">https://doi.org/10.1109/iolts.2009.5196027</a>.","apa":"Hunger, M., Hellebrand, S., Czutro, A., Polian, I., &#38; Becker, B. (2009). ATPG-Based Grading of Strong Fault-Secureness. <i>15th IEEE International On-Line Testing Symposium (IOLTS’09</i>. <a href=\"https://doi.org/10.1109/iolts.2009.5196027\">https://doi.org/10.1109/iolts.2009.5196027</a>","bibtex":"@inproceedings{Hunger_Hellebrand_Czutro_Polian_Becker_2009, place={Sesimbra-Lisbon, Portugal}, title={ATPG-Based Grading of Strong Fault-Secureness}, DOI={<a href=\"https://doi.org/10.1109/iolts.2009.5196027\">10.1109/iolts.2009.5196027</a>}, booktitle={15th IEEE International On-Line Testing Symposium (IOLTS’09}, publisher={IEEE}, author={Hunger, Marc and Hellebrand, Sybille and Czutro, Alejandro and Polian, Ilia and Becker, Bernd}, year={2009} }","short":"M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: 15th IEEE International On-Line Testing Symposium (IOLTS’09, IEEE, Sesimbra-Lisbon, Portugal, 2009.","mla":"Hunger, Marc, et al. “ATPG-Based Grading of Strong Fault-Secureness.” <i>15th IEEE International On-Line Testing Symposium (IOLTS’09</i>, IEEE, 2009, doi:<a href=\"https://doi.org/10.1109/iolts.2009.5196027\">10.1109/iolts.2009.5196027</a>."},"date_updated":"2022-05-11T16:27:48Z","publisher":"IEEE","author":[{"full_name":"Hunger, Marc","last_name":"Hunger","first_name":"Marc"},{"first_name":"Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","id":"209"},{"full_name":"Czutro, Alejandro","last_name":"Czutro","first_name":"Alejandro"},{"last_name":"Polian","full_name":"Polian, Ilia","first_name":"Ilia"},{"full_name":"Becker, Bernd","last_name":"Becker","first_name":"Bernd"}],"date_created":"2019-08-28T10:17:16Z","title":"ATPG-Based Grading of Strong Fault-Secureness","doi":"10.1109/iolts.2009.5196027"},{"status":"public","type":"conference","publication":"24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'09), (Invited Talk)","language":[{"iso":"eng"}],"user_id":"209","department":[{"_id":"48"}],"_id":"12990","citation":{"chicago":"Hellebrand, Sybille, and Marc Hunger. “Are Robust Circuits Really Robust?” In <i>24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk)</i>, 77. Chicago, IL, USA: IEEE, 2009. <a href=\"https://doi.org/10.1109/dft.2009.28\">https://doi.org/10.1109/dft.2009.28</a>.","ieee":"S. Hellebrand and M. Hunger, “Are Robust Circuits Really Robust?,” in <i>24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk)</i>, 2009, p. 77, doi: <a href=\"https://doi.org/10.1109/dft.2009.28\">10.1109/dft.2009.28</a>.","ama":"Hellebrand S, Hunger M. Are Robust Circuits Really Robust? In: <i>24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk)</i>. IEEE; 2009:77. doi:<a href=\"https://doi.org/10.1109/dft.2009.28\">10.1109/dft.2009.28</a>","apa":"Hellebrand, S., &#38; Hunger, M. (2009). Are Robust Circuits Really Robust? <i>24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk)</i>, 77. <a href=\"https://doi.org/10.1109/dft.2009.28\">https://doi.org/10.1109/dft.2009.28</a>","bibtex":"@inproceedings{Hellebrand_Hunger_2009, place={Chicago, IL, USA}, title={Are Robust Circuits Really Robust?}, DOI={<a href=\"https://doi.org/10.1109/dft.2009.28\">10.1109/dft.2009.28</a>}, booktitle={24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk)}, publisher={IEEE}, author={Hellebrand, Sybille and Hunger, Marc}, year={2009}, pages={77} }","short":"S. Hellebrand, M. Hunger, in: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), IEEE, Chicago, IL, USA, 2009, p. 77.","mla":"Hellebrand, Sybille, and Marc Hunger. “Are Robust Circuits Really Robust?” <i>24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk)</i>, IEEE, 2009, p. 77, doi:<a href=\"https://doi.org/10.1109/dft.2009.28\">10.1109/dft.2009.28</a>."},"page":"77","place":"Chicago, IL, USA","year":"2009","doi":"10.1109/dft.2009.28","title":"Are Robust Circuits Really Robust?","author":[{"first_name":"Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","id":"209"},{"last_name":"Hunger","full_name":"Hunger, Marc","first_name":"Marc"}],"date_created":"2019-08-28T10:17:14Z","publisher":"IEEE","date_updated":"2022-05-11T16:27:03Z"},{"citation":{"apa":"Hunger, M., Hellebrand, S., Czutro, A., Polian, I., &#38; Becker, B. (2009). Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung. <i>3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”</i>","mla":"Hunger, Marc, et al. “Robustheitsanalyse Stark Fehlersicherer Schaltungen Mit SAT-Basierter Testmustererzeugung.” <i>3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,”</i> 2009.","short":"M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Stuttgart, Germany, 2009.","bibtex":"@inproceedings{Hunger_Hellebrand_Czutro_Polian_Becker_2009, place={Stuttgart, Germany}, title={Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung}, booktitle={3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf”}, author={Hunger, Marc and Hellebrand, Sybille and Czutro, Alexander and Polian, Ilia and Becker, Bernd}, year={2009} }","ieee":"M. Hunger, S. Hellebrand, A. Czutro, I. Polian, and B. Becker, “Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung,” 2009.","chicago":"Hunger, Marc, Sybille Hellebrand, Alexander Czutro, Ilia Polian, and Bernd Becker. “Robustheitsanalyse Stark Fehlersicherer Schaltungen Mit SAT-Basierter Testmustererzeugung.” In <i>3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”</i> Stuttgart, Germany, 2009.","ama":"Hunger M, Hellebrand S, Czutro A, Polian I, Becker B. Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung. In: <i>3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”</i> ; 2009."},"place":"Stuttgart, Germany","year":"2009","date_created":"2019-08-28T10:35:48Z","author":[{"last_name":"Hunger","full_name":"Hunger, Marc","first_name":"Marc"},{"full_name":"Hellebrand, Sybille","id":"209","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","first_name":"Sybille"},{"full_name":"Czutro, Alexander","last_name":"Czutro","first_name":"Alexander"},{"first_name":"Ilia","full_name":"Polian, Ilia","last_name":"Polian"},{"full_name":"Becker, Bernd","last_name":"Becker","first_name":"Bernd"}],"date_updated":"2022-05-11T16:28:31Z","title":"Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung","publication":"3. GMM/GI/ITG-Fachtagung \"Zuverlässigkeit und Entwurf\"","type":"conference","status":"public","department":[{"_id":"48"}],"user_id":"209","_id":"13030","language":[{"iso":"eng"}]},{"type":"misc","status":"public","user_id":"659","department":[{"_id":"48"}],"_id":"13033","language":[{"iso":"eng"}],"keyword":["WORKSHOP"],"citation":{"ieee":"T. Coym, S. Hellebrand, S. Ludwig, B. Straube, H.-J. Wunderlich, and C. G. Zoellin, <i>Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit</i>. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich, 2008.","chicago":"Coym, Torsten, Sybille Hellebrand, Stefan Ludwig, Bernd Straube, Hans-Joachim Wunderlich, and Christian G. Zoellin. <i>Ein Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit</i>. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich, 2008.","ama":"Coym T, Hellebrand S, Ludwig S, Straube B, Wunderlich H-J, G. Zoellin C. <i>Ein Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit</i>. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich; 2008.","apa":"Coym, T., Hellebrand, S., Ludwig, S., Straube, B., Wunderlich, H.-J., &#38; G. Zoellin, C. (2008). <i>Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit</i>. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich.","mla":"Coym, Torsten, et al. <i>Ein Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit</i>. 2008.","bibtex":"@book{Coym_Hellebrand_Ludwig_Straube_Wunderlich_G. Zoellin_2008, place={20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich}, title={Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit}, author={Coym, Torsten and Hellebrand, Sybille and Ludwig, Stefan and Straube, Bernd and Wunderlich, Hans-Joachim and G. Zoellin, Christian}, year={2008} }","short":"T. Coym, S. Hellebrand, S. Ludwig, B. Straube, H.-J. Wunderlich, C. G. Zoellin, Ein Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit, 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich, 2008."},"place":"20. ITG/GI/GMM Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\" (Poster), Wien, Österreich","year":"2008","author":[{"first_name":"Torsten","full_name":"Coym, Torsten","last_name":"Coym"},{"last_name":"Hellebrand","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille","first_name":"Sybille"},{"first_name":"Stefan","last_name":"Ludwig","full_name":"Ludwig, Stefan"},{"full_name":"Straube, Bernd","last_name":"Straube","first_name":"Bernd"},{"last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim","first_name":"Hans-Joachim"},{"full_name":"G. Zoellin, Christian","last_name":"G. Zoellin","first_name":"Christian"}],"date_created":"2019-08-28T10:37:06Z","date_updated":"2022-01-06T06:51:27Z","title":"Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit"},{"date_updated":"2022-01-06T06:51:27Z","date_created":"2019-08-28T10:37:09Z","author":[{"last_name":"Amgalan","full_name":"Amgalan, Uranmandakh","first_name":"Uranmandakh"},{"first_name":"Christian","last_name":"Hachmann","full_name":"Hachmann, Christian"},{"first_name":"Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille"},{"first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich"}],"title":"Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen","place":"20. ITG/GI/GMM Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\", Wien, Österreich","year":"2008","citation":{"ama":"Amgalan U, Hachmann C, Hellebrand S, Wunderlich H-J. <i>Testen Mit Rücksetzpunkten - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen</i>. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich; 2008.","ieee":"U. Amgalan, C. Hachmann, S. Hellebrand, and H.-J. Wunderlich, <i>Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen</i>. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich, 2008.","chicago":"Amgalan, Uranmandakh, Christian Hachmann, Sybille Hellebrand, and Hans-Joachim Wunderlich. <i>Testen Mit Rücksetzpunkten - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen</i>. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich, 2008.","apa":"Amgalan, U., Hachmann, C., Hellebrand, S., &#38; Wunderlich, H.-J. (2008). <i>Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen</i>. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich.","short":"U. Amgalan, C. Hachmann, S. Hellebrand, H.-J. Wunderlich, Testen Mit Rücksetzpunkten - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen, 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich, 2008.","bibtex":"@book{Amgalan_Hachmann_Hellebrand_Wunderlich_2008, place={20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich}, title={Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen}, author={Amgalan, Uranmandakh and Hachmann, Christian and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2008} }","mla":"Amgalan, Uranmandakh, et al. <i>Testen Mit Rücksetzpunkten - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen</i>. 2008."},"_id":"13035","department":[{"_id":"48"}],"user_id":"659","keyword":["WORKSHOP"],"language":[{"iso":"eng"}],"type":"misc","status":"public"},{"language":[{"iso":"eng"}],"user_id":"209","department":[{"_id":"48"}],"_id":"12992","status":"public","type":"conference","publication":"14th IEEE International On-Line Testing Symposium (IOLTS'08), (Poster)","doi":"10.1109/iolts.2008.30","title":"A Modular Memory BIST for Optimized Memory Repair","date_created":"2019-08-28T10:18:10Z","author":[{"first_name":"Philipp","last_name":"Oehler","full_name":"Oehler, Philipp"},{"full_name":"Bosio, Alberto","last_name":"Bosio","first_name":"Alberto"},{"full_name":"di Natale, Giorgio","last_name":"di Natale","first_name":"Giorgio"},{"orcid":"0000-0002-3717-3939","last_name":"Hellebrand","full_name":"Hellebrand, Sybille","id":"209","first_name":"Sybille"}],"date_updated":"2022-05-11T16:29:13Z","publisher":"IEEE","citation":{"apa":"Oehler, P., Bosio, A., di Natale, G., &#38; Hellebrand, S. (2008). A Modular Memory BIST for Optimized Memory Repair. <i>14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster)</i>. <a href=\"https://doi.org/10.1109/iolts.2008.30\">https://doi.org/10.1109/iolts.2008.30</a>","mla":"Oehler, Philipp, et al. “A Modular Memory BIST for Optimized Memory Repair.” <i>14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster)</i>, IEEE, 2008, doi:<a href=\"https://doi.org/10.1109/iolts.2008.30\">10.1109/iolts.2008.30</a>.","short":"P. Oehler, A. Bosio, G. di Natale, S. Hellebrand, in: 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster), IEEE, Rhodos, Greece, 2008.","bibtex":"@inproceedings{Oehler_Bosio_di Natale_Hellebrand_2008, place={Rhodos, Greece}, title={A Modular Memory BIST for Optimized Memory Repair}, DOI={<a href=\"https://doi.org/10.1109/iolts.2008.30\">10.1109/iolts.2008.30</a>}, booktitle={14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster)}, publisher={IEEE}, author={Oehler, Philipp and Bosio, Alberto and di Natale, Giorgio and Hellebrand, Sybille}, year={2008} }","ama":"Oehler P, Bosio A, di Natale G, Hellebrand S. A Modular Memory BIST for Optimized Memory Repair. In: <i>14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster)</i>. IEEE; 2008. doi:<a href=\"https://doi.org/10.1109/iolts.2008.30\">10.1109/iolts.2008.30</a>","ieee":"P. Oehler, A. Bosio, G. di Natale, and S. Hellebrand, “A Modular Memory BIST for Optimized Memory Repair,” 2008, doi: <a href=\"https://doi.org/10.1109/iolts.2008.30\">10.1109/iolts.2008.30</a>.","chicago":"Oehler, Philipp, Alberto Bosio, Giorgio di Natale, and Sybille Hellebrand. “A Modular Memory BIST for Optimized Memory Repair.” In <i>14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster)</i>. Rhodos, Greece: IEEE, 2008. <a href=\"https://doi.org/10.1109/iolts.2008.30\">https://doi.org/10.1109/iolts.2008.30</a>."},"place":"Rhodos, Greece","year":"2008"},{"status":"public","publication":"26th IEEE VLSI Test Symposium (VTS'08)","type":"conference","language":[{"iso":"eng"}],"department":[{"_id":"48"}],"user_id":"209","_id":"12994","page":"125-130","citation":{"bibtex":"@inproceedings{Amgalan_Hachmann_Hellebrand_Wunderlich_2008, place={San Diego, CA, USA}, title={Signature Rollback - A Technique for Testing Robust Circuits}, DOI={<a href=\"https://doi.org/10.1109/vts.2008.34\">10.1109/vts.2008.34</a>}, booktitle={26th IEEE VLSI Test Symposium (VTS’08)}, publisher={IEEE}, author={Amgalan, Uranmandakh and Hachmann, Christian and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2008}, pages={125–130} }","mla":"Amgalan, Uranmandakh, et al. “Signature Rollback - A Technique for Testing Robust Circuits.” <i>26th IEEE VLSI Test Symposium (VTS’08)</i>, IEEE, 2008, pp. 125–30, doi:<a href=\"https://doi.org/10.1109/vts.2008.34\">10.1109/vts.2008.34</a>.","short":"U. Amgalan, C. Hachmann, S. Hellebrand, H.-J. Wunderlich, in: 26th IEEE VLSI Test Symposium (VTS’08), IEEE, San Diego, CA, USA, 2008, pp. 125–130.","apa":"Amgalan, U., Hachmann, C., Hellebrand, S., &#38; Wunderlich, H.-J. (2008). Signature Rollback - A Technique for Testing Robust Circuits. <i>26th IEEE VLSI Test Symposium (VTS’08)</i>, 125–130. <a href=\"https://doi.org/10.1109/vts.2008.34\">https://doi.org/10.1109/vts.2008.34</a>","ama":"Amgalan U, Hachmann C, Hellebrand S, Wunderlich H-J. Signature Rollback - A Technique for Testing Robust Circuits. In: <i>26th IEEE VLSI Test Symposium (VTS’08)</i>. IEEE; 2008:125-130. doi:<a href=\"https://doi.org/10.1109/vts.2008.34\">10.1109/vts.2008.34</a>","ieee":"U. Amgalan, C. Hachmann, S. Hellebrand, and H.-J. Wunderlich, “Signature Rollback - A Technique for Testing Robust Circuits,” in <i>26th IEEE VLSI Test Symposium (VTS’08)</i>, 2008, pp. 125–130, doi: <a href=\"https://doi.org/10.1109/vts.2008.34\">10.1109/vts.2008.34</a>.","chicago":"Amgalan, Uranmandakh, Christian Hachmann, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Signature Rollback - A Technique for Testing Robust Circuits.” In <i>26th IEEE VLSI Test Symposium (VTS’08)</i>, 125–30. San Diego, CA, USA: IEEE, 2008. <a href=\"https://doi.org/10.1109/vts.2008.34\">https://doi.org/10.1109/vts.2008.34</a>."},"year":"2008","place":"San Diego, CA, USA","doi":"10.1109/vts.2008.34","title":"Signature Rollback - A Technique for Testing Robust Circuits","date_created":"2019-08-28T10:18:56Z","author":[{"full_name":"Amgalan, Uranmandakh","last_name":"Amgalan","first_name":"Uranmandakh"},{"first_name":"Christian","last_name":"Hachmann","full_name":"Hachmann, Christian"},{"last_name":"Hellebrand","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille","first_name":"Sybille"},{"full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich","first_name":"Hans-Joachim"}],"publisher":"IEEE","date_updated":"2022-05-11T16:30:36Z"},{"status":"public","type":"conference","publication":"14th IEEE International On-Line Testing Symposium (IOLTS'08)","language":[{"iso":"eng"}],"user_id":"209","department":[{"_id":"48"}],"_id":"12993","citation":{"chicago":"Hunger, Marc, and Sybille Hellebrand. “Verification and Analysis of Self-Checking Properties through ATPG.” In <i>14th IEEE International On-Line Testing Symposium (IOLTS’08)</i>. Rhodos, Greece: IEEE, 2008. <a href=\"https://doi.org/10.1109/iolts.2008.32\">https://doi.org/10.1109/iolts.2008.32</a>.","ieee":"M. Hunger and S. Hellebrand, “Verification and Analysis of Self-Checking Properties through ATPG,” 2008, doi: <a href=\"https://doi.org/10.1109/iolts.2008.32\">10.1109/iolts.2008.32</a>.","ama":"Hunger M, Hellebrand S. Verification and Analysis of Self-Checking Properties through ATPG. In: <i>14th IEEE International On-Line Testing Symposium (IOLTS’08)</i>. IEEE; 2008. doi:<a href=\"https://doi.org/10.1109/iolts.2008.32\">10.1109/iolts.2008.32</a>","apa":"Hunger, M., &#38; Hellebrand, S. (2008). Verification and Analysis of Self-Checking Properties through ATPG. <i>14th IEEE International On-Line Testing Symposium (IOLTS’08)</i>. <a href=\"https://doi.org/10.1109/iolts.2008.32\">https://doi.org/10.1109/iolts.2008.32</a>","bibtex":"@inproceedings{Hunger_Hellebrand_2008, place={Rhodos, Greece}, title={Verification and Analysis of Self-Checking Properties through ATPG}, DOI={<a href=\"https://doi.org/10.1109/iolts.2008.32\">10.1109/iolts.2008.32</a>}, booktitle={14th IEEE International On-Line Testing Symposium (IOLTS’08)}, publisher={IEEE}, author={Hunger, Marc and Hellebrand, Sybille}, year={2008} }","mla":"Hunger, Marc, and Sybille Hellebrand. “Verification and Analysis of Self-Checking Properties through ATPG.” <i>14th IEEE International On-Line Testing Symposium (IOLTS’08)</i>, IEEE, 2008, doi:<a href=\"https://doi.org/10.1109/iolts.2008.32\">10.1109/iolts.2008.32</a>.","short":"M. Hunger, S. Hellebrand, in: 14th IEEE International On-Line Testing Symposium (IOLTS’08), IEEE, Rhodos, Greece, 2008."},"place":"Rhodos, Greece","year":"2008","doi":"10.1109/iolts.2008.32","title":"Verification and Analysis of Self-Checking Properties through ATPG","author":[{"first_name":"Marc","full_name":"Hunger, Marc","last_name":"Hunger"},{"full_name":"Hellebrand, Sybille","id":"209","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","first_name":"Sybille"}],"date_created":"2019-08-28T10:18:11Z","publisher":"IEEE","date_updated":"2022-05-11T16:29:56Z"}]
