[{"year":"2008","place":"Ingolstadt, Germany","citation":{"ama":"Hunger M, Hellebrand S. Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG. In: <i>2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”</i> ; 2008.","chicago":"Hunger, Marc, and Sybille Hellebrand. “Analyse Selbstprüfender Schaltungen – Nachweis von Fehlersicherheit Und Selbsttestbarkeit Mit ATPG.” In <i>2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”</i> Ingolstadt, Germany, 2008.","ieee":"M. Hunger and S. Hellebrand, “Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG,” 2008.","mla":"Hunger, Marc, and Sybille Hellebrand. “Analyse Selbstprüfender Schaltungen – Nachweis von Fehlersicherheit Und Selbsttestbarkeit Mit ATPG.” <i>2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,”</i> 2008.","bibtex":"@inproceedings{Hunger_Hellebrand_2008, place={Ingolstadt, Germany}, title={Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG}, booktitle={2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf”}, author={Hunger, Marc and Hellebrand, Sybille}, year={2008} }","short":"M. Hunger, S. Hellebrand, in: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Ingolstadt, Germany, 2008.","apa":"Hunger, M., &#38; Hellebrand, S. (2008). Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG. <i>2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”</i>"},"title":"Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG","date_updated":"2022-05-11T16:31:25Z","date_created":"2019-08-28T10:35:49Z","author":[{"full_name":"Hunger, Marc","last_name":"Hunger","first_name":"Marc"},{"orcid":"0000-0002-3717-3939","last_name":"Hellebrand","id":"209","full_name":"Hellebrand, Sybille","first_name":"Sybille"}],"status":"public","type":"conference","publication":"2. GMM/GI/ITG-Fachtagung \"Zuverlässigkeit und Entwurf\"","language":[{"iso":"eng"}],"_id":"13031","user_id":"209","department":[{"_id":"48"}]},{"publication":"2. GMM/GI/ITG-Fachtagung \"Zuverlässigkeit und Entwurf\"","type":"conference","status":"public","_id":"13032","department":[{"_id":"48"}],"user_id":"209","language":[{"iso":"eng"}],"place":"Ingolstadt, Germany","year":"2008","citation":{"apa":"Oehler, P., Bosio, A., Di Natale, G., &#38; Hellebrand, S. (2008). Modularer Selbsttest und optimierte Reparaturanalyse. <i>2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”</i>","mla":"Oehler, Philipp, et al. “Modularer Selbsttest Und Optimierte Reparaturanalyse.” <i>2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,”</i> 2008.","short":"P. Oehler, A. Bosio, G. Di Natale, S. Hellebrand, in: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Ingolstadt, Germany, 2008.","bibtex":"@inproceedings{Oehler_Bosio_Di Natale_Hellebrand_2008, place={Ingolstadt, Germany}, title={Modularer Selbsttest und optimierte Reparaturanalyse}, booktitle={2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf”}, author={Oehler, Philipp and Bosio, Alberto and Di Natale, Giorgio and Hellebrand, Sybille}, year={2008} }","chicago":"Oehler, Philipp, Alberto Bosio, Giorgio Di Natale, and Sybille Hellebrand. “Modularer Selbsttest Und Optimierte Reparaturanalyse.” In <i>2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”</i> Ingolstadt, Germany, 2008.","ieee":"P. Oehler, A. Bosio, G. Di Natale, and S. Hellebrand, “Modularer Selbsttest und optimierte Reparaturanalyse,” 2008.","ama":"Oehler P, Bosio A, Di Natale G, Hellebrand S. Modularer Selbsttest und optimierte Reparaturanalyse. In: <i>2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”</i> ; 2008."},"date_updated":"2022-05-11T16:34:03Z","date_created":"2019-08-28T10:35:50Z","author":[{"last_name":"Oehler","full_name":"Oehler, Philipp","first_name":"Philipp"},{"last_name":"Bosio","full_name":"Bosio, Alberto","first_name":"Alberto"},{"first_name":"Giorgio","last_name":"Di Natale","full_name":"Di Natale, Giorgio"},{"last_name":"Hellebrand","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","id":"209","first_name":"Sybille"}],"title":"Modularer Selbsttest und optimierte Reparaturanalyse"},{"status":"public","type":"misc","language":[{"iso":"eng"}],"keyword":["WORKSHOP"],"user_id":"659","department":[{"_id":"48"}],"_id":"13038","citation":{"ieee":"S. Hellebrand, <i>Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing</i>. 5th IEEE East-West Design \\&#38; Test Symposium, Yerevan, Armenia (Invited Talk), 2007.","chicago":"Hellebrand, Sybille. <i>Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing</i>. 5th IEEE East-West Design \\&#38; Test Symposium, Yerevan, Armenia (Invited Talk), 2007.","ama":"Hellebrand S. <i>Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing</i>. 5th IEEE East-West Design \\&#38; Test Symposium, Yerevan, Armenia (Invited Talk); 2007.","apa":"Hellebrand, S. (2007). <i>Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing</i>. 5th IEEE East-West Design \\&#38; Test Symposium, Yerevan, Armenia (Invited Talk).","mla":"Hellebrand, Sybille. <i>Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing</i>. 2007.","bibtex":"@book{Hellebrand_2007, place={5th IEEE East-West Design \\&#38; Test Symposium, Yerevan, Armenia (Invited Talk)}, title={Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing}, author={Hellebrand, Sybille}, year={2007} }","short":"S. Hellebrand, Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing, 5th IEEE East-West Design \\&#38; Test Symposium, Yerevan, Armenia (Invited Talk), 2007."},"place":"5th IEEE East-West Design \\& Test Symposium, Yerevan, Armenia (Invited Talk)","year":"2007","title":"Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing","date_created":"2019-08-28T10:40:47Z","author":[{"id":"209","full_name":"Hellebrand, Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","first_name":"Sybille"}],"date_updated":"2022-01-06T06:51:27Z"},{"language":[{"iso":"eng"}],"keyword":["WORKSHOP"],"department":[{"_id":"48"}],"user_id":"659","_id":"13039","status":"public","type":"misc","title":"An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips","date_created":"2019-08-28T10:41:29Z","author":[{"first_name":"Muhammad","last_name":"Ali","full_name":"Ali, Muhammad"},{"first_name":"Michael","full_name":"Welzl, Michael","last_name":"Welzl"},{"last_name":"Hessler","full_name":"Hessler, Sven","first_name":"Sven"},{"last_name":"Hellebrand","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille","first_name":"Sybille"}],"date_updated":"2022-01-06T06:51:27Z","citation":{"apa":"Ali, M., Welzl, M., Hessler, S., &#38; Hellebrand, S. (2007). <i>An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips</i>. DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster).","mla":"Ali, Muhammad, et al. <i>An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips</i>. 2007.","bibtex":"@book{Ali_Welzl_Hessler_Hellebrand_2007, place={DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster)}, title={An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips}, author={Ali, Muhammad and Welzl, Michael and Hessler, Sven and Hellebrand, Sybille}, year={2007} }","short":"M. Ali, M. Welzl, S. Hessler, S. Hellebrand, An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips, DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster), 2007.","chicago":"Ali, Muhammad, Michael Welzl, Sven Hessler, and Sybille Hellebrand. <i>An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips</i>. DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster), 2007.","ieee":"M. Ali, M. Welzl, S. Hessler, and S. Hellebrand, <i>An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips</i>. DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster), 2007.","ama":"Ali M, Welzl M, Hessler S, Hellebrand S. <i>An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips</i>. DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster); 2007."},"year":"2007","place":"DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster)"},{"date_updated":"2022-01-06T06:51:27Z","author":[{"first_name":"Philipp","full_name":"Oehler, Philipp","last_name":"Oehler"},{"full_name":"Hellebrand, Sybille","id":"209","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","first_name":"Sybille"},{"full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich","first_name":"Hans-Joachim"}],"date_created":"2019-08-28T10:43:12Z","title":"An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy","year":"2007","place":"17th GI/ITG/GMM Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\", Erlangen, Germany","citation":{"apa":"Oehler, P., Hellebrand, S., &#38; Wunderlich, H.-J. (2007). <i>An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy</i>. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany.","mla":"Oehler, Philipp, et al. <i>An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy</i>. 2007.","short":"P. Oehler, S. Hellebrand, H.-J. Wunderlich, An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany, 2007.","bibtex":"@book{Oehler_Hellebrand_Wunderlich_2007, place={17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany}, title={An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy}, author={Oehler, Philipp and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2007} }","ama":"Oehler P, Hellebrand S, Wunderlich H-J. <i>An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy</i>. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany; 2007.","chicago":"Oehler, Philipp, Sybille Hellebrand, and Hans-Joachim Wunderlich. <i>An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy</i>. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany, 2007.","ieee":"P. Oehler, S. Hellebrand, and H.-J. Wunderlich, <i>An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy</i>. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany, 2007."},"_id":"13042","department":[{"_id":"48"}],"user_id":"659","keyword":["WORKSHOP"],"language":[{"iso":"eng"}],"type":"misc","status":"public"},{"place":"ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany","year":"2007","citation":{"ama":"Hellebrand S. <i>Qualitätssicherung Für Nanochips - Wie IT-Produkte Zuverlässig Werden</i>. ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany; 2007.","chicago":"Hellebrand, Sybille. <i>Qualitätssicherung Für Nanochips - Wie IT-Produkte Zuverlässig Werden</i>. ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany, 2007.","ieee":"S. Hellebrand, <i>Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig werden</i>. ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany, 2007.","apa":"Hellebrand, S. (2007). <i>Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig werden</i>. ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany.","bibtex":"@book{Hellebrand_2007, place={ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany}, title={Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig werden}, author={Hellebrand, Sybille}, year={2007} }","mla":"Hellebrand, Sybille. <i>Qualitätssicherung Für Nanochips - Wie IT-Produkte Zuverlässig Werden</i>. 2007.","short":"S. Hellebrand, Qualitätssicherung Für Nanochips - Wie IT-Produkte Zuverlässig Werden, ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany, 2007."},"date_updated":"2022-01-06T06:51:27Z","date_created":"2019-08-28T10:43:54Z","author":[{"first_name":"Sybille","full_name":"Hellebrand, Sybille","id":"209","orcid":"0000-0002-3717-3939","last_name":"Hellebrand"}],"title":"Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig werden","type":"misc","status":"public","_id":"13043","department":[{"_id":"48"}],"user_id":"659","language":[{"iso":"eng"}]},{"author":[{"last_name":"Hellebrand","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","id":"209","first_name":"Sybille"},{"last_name":"G. Zoellin","full_name":"G. Zoellin, Christian","first_name":"Christian"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"},{"last_name":"Ludwig","full_name":"Ludwig, Stefan","first_name":"Stefan"},{"first_name":"Torsten","last_name":"Coym","full_name":"Coym, Torsten"},{"first_name":"Bernd","full_name":"Straube, Bernd","last_name":"Straube"}],"date_created":"2019-08-28T10:18:57Z","publisher":"IEEE","date_updated":"2022-05-11T16:32:38Z","doi":"10.1109/dft.2007.43","title":"A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction","citation":{"chicago":"Hellebrand, Sybille, Christian G. Zoellin, Hans-Joachim Wunderlich, Stefan Ludwig, Torsten Coym, and Bernd Straube. “A Refined Electrical Model for Particle Strikes and Its Impact on SEU Prediction.” In <i>22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07)</i>, 50–58. Rome, Italy: IEEE, 2007. <a href=\"https://doi.org/10.1109/dft.2007.43\">https://doi.org/10.1109/dft.2007.43</a>.","ieee":"S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction,” in <i>22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07)</i>, 2007, pp. 50–58, doi: <a href=\"https://doi.org/10.1109/dft.2007.43\">10.1109/dft.2007.43</a>.","ama":"Hellebrand S, G. Zoellin C, Wunderlich H-J, Ludwig S, Coym T, Straube B. A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. In: <i>22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07)</i>. IEEE; 2007:50-58. doi:<a href=\"https://doi.org/10.1109/dft.2007.43\">10.1109/dft.2007.43</a>","apa":"Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., &#38; Straube, B. (2007). A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. <i>22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07)</i>, 50–58. <a href=\"https://doi.org/10.1109/dft.2007.43\">https://doi.org/10.1109/dft.2007.43</a>","short":"S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, in: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), IEEE, Rome, Italy, 2007, pp. 50–58.","bibtex":"@inproceedings{Hellebrand_G. Zoellin_Wunderlich_Ludwig_Coym_Straube_2007, place={Rome, Italy}, title={A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction}, DOI={<a href=\"https://doi.org/10.1109/dft.2007.43\">10.1109/dft.2007.43</a>}, booktitle={22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07)}, publisher={IEEE}, author={Hellebrand, Sybille and G. Zoellin, Christian and Wunderlich, Hans-Joachim and Ludwig, Stefan and Coym, Torsten and Straube, Bernd}, year={2007}, pages={50–58} }","mla":"Hellebrand, Sybille, et al. “A Refined Electrical Model for Particle Strikes and Its Impact on SEU Prediction.” <i>22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07)</i>, IEEE, 2007, pp. 50–58, doi:<a href=\"https://doi.org/10.1109/dft.2007.43\">10.1109/dft.2007.43</a>."},"page":"50-58","place":"Rome, Italy","year":"2007","user_id":"209","department":[{"_id":"48"}],"_id":"12995","language":[{"iso":"eng"}],"type":"conference","publication":"22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'07)","status":"public"},{"citation":{"short":"P. Oehler, S. Hellebrand, H.-J. Wunderlich, in: 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), IEEE, Krakow, Poland, 2007, pp. 185–190.","bibtex":"@inproceedings{Oehler_Hellebrand_Wunderlich_2007, place={Krakow, Poland}, title={Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair}, DOI={<a href=\"https://doi.org/10.1109/ddecs.2007.4295278\">10.1109/ddecs.2007.4295278</a>}, booktitle={10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07)}, publisher={IEEE}, author={Oehler, Philipp and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2007}, pages={185–190} }","mla":"Oehler, Philipp, et al. “Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair.” <i>10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07)</i>, IEEE, 2007, pp. 185–90, doi:<a href=\"https://doi.org/10.1109/ddecs.2007.4295278\">10.1109/ddecs.2007.4295278</a>.","apa":"Oehler, P., Hellebrand, S., &#38; Wunderlich, H.-J. (2007). Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. <i>10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07)</i>, 185–190. <a href=\"https://doi.org/10.1109/ddecs.2007.4295278\">https://doi.org/10.1109/ddecs.2007.4295278</a>","ama":"Oehler P, Hellebrand S, Wunderlich H-J. Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. In: <i>10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07)</i>. IEEE; 2007:185-190. doi:<a href=\"https://doi.org/10.1109/ddecs.2007.4295278\">10.1109/ddecs.2007.4295278</a>","ieee":"P. Oehler, S. Hellebrand, and H.-J. Wunderlich, “Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair,” in <i>10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07)</i>, 2007, pp. 185–190, doi: <a href=\"https://doi.org/10.1109/ddecs.2007.4295278\">10.1109/ddecs.2007.4295278</a>.","chicago":"Oehler, Philipp, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair.” In <i>10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07)</i>, 185–90. Krakow, Poland: IEEE, 2007. <a href=\"https://doi.org/10.1109/ddecs.2007.4295278\">https://doi.org/10.1109/ddecs.2007.4295278</a>."},"page":"185-190","year":"2007","place":"Krakow, Poland","date_created":"2019-08-28T10:19:52Z","author":[{"last_name":"Oehler","full_name":"Oehler, Philipp","first_name":"Philipp"},{"first_name":"Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","id":"209","full_name":"Hellebrand, Sybille"},{"last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim","first_name":"Hans-Joachim"}],"publisher":"IEEE","date_updated":"2022-05-11T16:34:43Z","doi":"10.1109/ddecs.2007.4295278","title":"Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair","type":"conference","publication":"10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'07)","status":"public","user_id":"209","department":[{"_id":"48"}],"_id":"12996","language":[{"iso":"eng"}]},{"doi":"10.1109/ets.2007.10","title":"An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy","author":[{"last_name":"Oehler","full_name":"Oehler, Philipp","first_name":"Philipp"},{"first_name":"Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","id":"209"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"}],"date_created":"2019-08-28T10:19:53Z","publisher":"IEEE","date_updated":"2022-05-11T16:33:32Z","page":"91-96","citation":{"ieee":"P. Oehler, S. Hellebrand, and H.-J. Wunderlich, “An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy,” in <i>12th IEEE European Test Symposium (ETS’07)</i>, 2007, pp. 91–96, doi: <a href=\"https://doi.org/10.1109/ets.2007.10\">10.1109/ets.2007.10</a>.","chicago":"Oehler, Philipp, Sybille Hellebrand, and Hans-Joachim Wunderlich. “An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy.” In <i>12th IEEE European Test Symposium (ETS’07)</i>, 91–96. Freiburg, Germany: IEEE, 2007. <a href=\"https://doi.org/10.1109/ets.2007.10\">https://doi.org/10.1109/ets.2007.10</a>.","ama":"Oehler P, Hellebrand S, Wunderlich H-J. An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. In: <i>12th IEEE European Test Symposium (ETS’07)</i>. IEEE; 2007:91-96. doi:<a href=\"https://doi.org/10.1109/ets.2007.10\">10.1109/ets.2007.10</a>","bibtex":"@inproceedings{Oehler_Hellebrand_Wunderlich_2007, place={Freiburg, Germany}, title={An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy}, DOI={<a href=\"https://doi.org/10.1109/ets.2007.10\">10.1109/ets.2007.10</a>}, booktitle={12th IEEE European Test Symposium (ETS’07)}, publisher={IEEE}, author={Oehler, Philipp and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2007}, pages={91–96} }","short":"P. Oehler, S. Hellebrand, H.-J. Wunderlich, in: 12th IEEE European Test Symposium (ETS’07), IEEE, Freiburg, Germany, 2007, pp. 91–96.","mla":"Oehler, Philipp, et al. “An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy.” <i>12th IEEE European Test Symposium (ETS’07)</i>, IEEE, 2007, pp. 91–96, doi:<a href=\"https://doi.org/10.1109/ets.2007.10\">10.1109/ets.2007.10</a>.","apa":"Oehler, P., Hellebrand, S., &#38; Wunderlich, H.-J. (2007). An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. <i>12th IEEE European Test Symposium (ETS’07)</i>, 91–96. <a href=\"https://doi.org/10.1109/ets.2007.10\">https://doi.org/10.1109/ets.2007.10</a>"},"place":"Freiburg, Germany","year":"2007","language":[{"iso":"eng"}],"department":[{"_id":"48"}],"user_id":"209","_id":"12997","status":"public","publication":"12th IEEE European Test Symposium (ETS'07)","type":"conference"},{"status":"public","type":"conference","publication":"43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07), (Invited Paper)","language":[{"iso":"eng"}],"user_id":"209","department":[{"_id":"48"}],"_id":"13037","citation":{"ama":"Hellebrand S, G. Zoellin C, Wunderlich H-J, Ludwig S, Coym T, Straube B. Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. In: <i>43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper)</i>. ; 2007.","chicago":"Hellebrand, Sybille, Christian G. Zoellin, Hans-Joachim Wunderlich, Stefan Ludwig, Torsten Coym, and Bernd Straube. “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance.” In <i>43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper)</i>. Bled, Slovenia, 2007.","ieee":"S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance,” 2007.","apa":"Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., &#38; Straube, B. (2007). Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. <i>43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper)</i>.","bibtex":"@inproceedings{Hellebrand_G. Zoellin_Wunderlich_Ludwig_Coym_Straube_2007, place={Bled, Slovenia}, title={Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance}, booktitle={43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper)}, author={Hellebrand, Sybille and G. Zoellin, Christian and Wunderlich, Hans-Joachim and Ludwig, Stefan and Coym, Torsten and Straube, Bernd}, year={2007} }","short":"S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, in: 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper), Bled, Slovenia, 2007.","mla":"Hellebrand, Sybille, et al. “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance.” <i>43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper)</i>, 2007."},"year":"2007","place":"Bled, Slovenia","title":"Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance","date_created":"2019-08-28T10:40:00Z","author":[{"first_name":"Sybille","full_name":"Hellebrand, Sybille","id":"209","orcid":"0000-0002-3717-3939","last_name":"Hellebrand"},{"first_name":"Christian","full_name":"G. Zoellin, Christian","last_name":"G. Zoellin"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"},{"last_name":"Ludwig","full_name":"Ludwig, Stefan","first_name":"Stefan"},{"first_name":"Torsten","full_name":"Coym, Torsten","last_name":"Coym"},{"first_name":"Bernd","last_name":"Straube","full_name":"Straube, Bernd"}],"date_updated":"2022-05-11T16:35:35Z"},{"_id":"13036","department":[{"_id":"48"}],"user_id":"209","language":[{"iso":"eng"}],"publication":"Informacije MIDEM, Ljubljana (Invited Paper)","type":"journal_article","status":"public","date_updated":"2022-05-11T16:36:10Z","volume":37,"date_created":"2019-08-28T10:39:59Z","author":[{"last_name":"Hellebrand","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille","first_name":"Sybille"},{"first_name":"Christian","last_name":"G. Zoellin","full_name":"G. Zoellin, Christian"},{"first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich"},{"last_name":"Ludwig","full_name":"Ludwig, Stefan","first_name":"Stefan"},{"first_name":"Torsten","full_name":"Coym, Torsten","last_name":"Coym"},{"first_name":"Bernd","full_name":"Straube, Bernd","last_name":"Straube"}],"title":"Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance","issue":"4 (124)","year":"2007","page":"212-219","intvolume":"        37","citation":{"ama":"Hellebrand S, G. Zoellin C, Wunderlich H-J, Ludwig S, Coym T, Straube B. Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. <i>Informacije MIDEM, Ljubljana (Invited Paper)</i>. 2007;37(4 (124)):212-219.","ieee":"S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance,” <i>Informacije MIDEM, Ljubljana (Invited Paper)</i>, vol. 37, no. 4 (124), pp. 212–219, 2007.","chicago":"Hellebrand, Sybille, Christian G. Zoellin, Hans-Joachim Wunderlich, Stefan Ludwig, Torsten Coym, and Bernd Straube. “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance.” <i>Informacije MIDEM, Ljubljana (Invited Paper)</i> 37, no. 4 (124) (2007): 212–19.","apa":"Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., &#38; Straube, B. (2007). Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. <i>Informacije MIDEM, Ljubljana (Invited Paper)</i>, <i>37</i>(4 (124)), 212–219.","bibtex":"@article{Hellebrand_G. Zoellin_Wunderlich_Ludwig_Coym_Straube_2007, title={Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance}, volume={37}, number={4 (124)}, journal={Informacije MIDEM, Ljubljana (Invited Paper)}, author={Hellebrand, Sybille and G. Zoellin, Christian and Wunderlich, Hans-Joachim and Ludwig, Stefan and Coym, Torsten and Straube, Bernd}, year={2007}, pages={212–219} }","short":"S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, Informacije MIDEM, Ljubljana (Invited Paper) 37 (2007) 212–219.","mla":"Hellebrand, Sybille, et al. “Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance.” <i>Informacije MIDEM, Ljubljana (Invited Paper)</i>, vol. 37, no. 4 (124), 2007, pp. 212–19."}},{"issue":"2","year":"2007","citation":{"apa":"Ali, M., Hessler, S., Welzl, M., &#38; Hellebrand, S. (2007). An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip. <i>International Journal on High Performance Systems Architecture</i>, <i>1</i>(2), 113–123.","short":"M. Ali, S. Hessler, M. Welzl, S. Hellebrand, International Journal on High Performance Systems Architecture 1 (2007) 113–123.","bibtex":"@article{Ali_Hessler_Welzl_Hellebrand_2007, title={An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip}, volume={1}, number={2}, journal={International Journal on High Performance Systems Architecture}, author={Ali, Muhammad and Hessler, Sven and Welzl, Michael and Hellebrand, Sybille}, year={2007}, pages={113–123} }","mla":"Ali, Muhammad, et al. “An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip.” <i>International Journal on High Performance Systems Architecture</i>, vol. 1, no. 2, 2007, pp. 113–23.","ama":"Ali M, Hessler S, Welzl M, Hellebrand S. An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip. <i>International Journal on High Performance Systems Architecture</i>. 2007;1(2):113-123.","chicago":"Ali, Muhammad, Sven Hessler, Michael Welzl, and Sybille Hellebrand. “An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip.” <i>International Journal on High Performance Systems Architecture</i> 1, no. 2 (2007): 113–23.","ieee":"M. Ali, S. Hessler, M. Welzl, and S. Hellebrand, “An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip,” <i>International Journal on High Performance Systems Architecture</i>, vol. 1, no. 2, pp. 113–123, 2007."},"page":"113-123","intvolume":"         1","date_updated":"2022-05-11T16:37:57Z","author":[{"first_name":"Muhammad","last_name":"Ali","full_name":"Ali, Muhammad"},{"last_name":"Hessler","full_name":"Hessler, Sven","first_name":"Sven"},{"first_name":"Michael","full_name":"Welzl, Michael","last_name":"Welzl"},{"first_name":"Sybille","id":"209","full_name":"Hellebrand, Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939"}],"date_created":"2019-08-28T10:44:52Z","volume":1,"title":"An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip","type":"journal_article","publication":"International Journal on High Performance Systems Architecture","status":"public","_id":"13044","user_id":"209","department":[{"_id":"48"}],"language":[{"iso":"eng"}]},{"_id":"13040","department":[{"_id":"48"}],"user_id":"209","language":[{"iso":"eng"}],"publication":"4th International Conference on Information Technology: New Generations (ITNG'07)","type":"conference","status":"public","date_updated":"2022-05-11T16:36:42Z","author":[{"last_name":"Ali","full_name":"Ali, Muhammad","first_name":"Muhammad"},{"full_name":"Welzl, Michael","last_name":"Welzl","first_name":"Michael"},{"last_name":"Hessler","full_name":"Hessler, Sven","first_name":"Sven"},{"orcid":"0000-0002-3717-3939","last_name":"Hellebrand","id":"209","full_name":"Hellebrand, Sybille","first_name":"Sybille"}],"date_created":"2019-08-28T10:42:27Z","title":"A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip","place":"Las Vegas, Nevada, USA","year":"2007","page":"1027-1032","citation":{"ama":"Ali M, Welzl M, Hessler S, Hellebrand S. A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip. In: <i>4th International Conference on Information Technology: New Generations (ITNG’07)</i>. ; 2007:1027-1032.","ieee":"M. Ali, M. Welzl, S. Hessler, and S. Hellebrand, “A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip,” in <i>4th International Conference on Information Technology: New Generations (ITNG’07)</i>, 2007, pp. 1027–1032.","chicago":"Ali, Muhammad, Michael Welzl, Sven Hessler, and Sybille Hellebrand. “A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip.” In <i>4th International Conference on Information Technology: New Generations (ITNG’07)</i>, 1027–32. Las Vegas, Nevada, USA, 2007.","apa":"Ali, M., Welzl, M., Hessler, S., &#38; Hellebrand, S. (2007). A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip. <i>4th International Conference on Information Technology: New Generations (ITNG’07)</i>, 1027–1032.","short":"M. Ali, M. Welzl, S. Hessler, S. Hellebrand, in: 4th International Conference on Information Technology: New Generations (ITNG’07), Las Vegas, Nevada, USA, 2007, pp. 1027–1032.","mla":"Ali, Muhammad, et al. “A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip.” <i>4th International Conference on Information Technology: New Generations (ITNG’07)</i>, 2007, pp. 1027–32.","bibtex":"@inproceedings{Ali_Welzl_Hessler_Hellebrand_2007, place={Las Vegas, Nevada, USA}, title={A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip}, booktitle={4th International Conference on Information Technology: New Generations (ITNG’07)}, author={Ali, Muhammad and Welzl, Michael and Hessler, Sven and Hellebrand, Sybille}, year={2007}, pages={1027–1032} }"}},{"language":[{"iso":"eng"}],"_id":"13041","department":[{"_id":"48"}],"user_id":"209","status":"public","publication":"1. GMM/GI/ITG-Fachtagung \"Zuverlässigkeit und Entwurf\"","type":"conference","title":"Test und Zuverlässigkeit nanoelektronischer Systeme","date_updated":"2022-05-11T16:37:22Z","author":[{"full_name":"Becker, Bernd","last_name":"Becker","first_name":"Bernd"},{"last_name":"Polian","full_name":"Polian, Ilia","first_name":"Ilia"},{"orcid":"0000-0002-3717-3939","last_name":"Hellebrand","full_name":"Hellebrand, Sybille","id":"209","first_name":"Sybille"},{"first_name":"Bernd","last_name":"Straube","full_name":"Straube, Bernd"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"}],"date_created":"2019-08-28T10:42:28Z","place":"Munich, Germany","year":"2007","citation":{"ama":"Becker B, Polian I, Hellebrand S, Straube B, Wunderlich H-J. Test und Zuverlässigkeit nanoelektronischer Systeme. In: <i>1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”</i> ; 2007.","ieee":"B. Becker, I. Polian, S. Hellebrand, B. Straube, and H.-J. Wunderlich, “Test und Zuverlässigkeit nanoelektronischer Systeme,” 2007.","chicago":"Becker, Bernd, Ilia Polian, Sybille Hellebrand, Bernd Straube, and Hans-Joachim Wunderlich. “Test Und Zuverlässigkeit Nanoelektronischer Systeme.” In <i>1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”</i> Munich, Germany, 2007.","apa":"Becker, B., Polian, I., Hellebrand, S., Straube, B., &#38; Wunderlich, H.-J. (2007). Test und Zuverlässigkeit nanoelektronischer Systeme. <i>1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”</i>","bibtex":"@inproceedings{Becker_Polian_Hellebrand_Straube_Wunderlich_2007, place={Munich, Germany}, title={Test und Zuverlässigkeit nanoelektronischer Systeme}, booktitle={1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf”}, author={Becker, Bernd and Polian, Ilia and Hellebrand, Sybille and Straube, Bernd and Wunderlich, Hans-Joachim}, year={2007} }","short":"B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich, in: 1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Munich, Germany, 2007.","mla":"Becker, Bernd, et al. “Test Und Zuverlässigkeit Nanoelektronischer Systeme.” <i>1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,”</i> 2007."}},{"status":"public","publication":"it - Information Technology","type":"journal_article","language":[{"iso":"eng"}],"department":[{"_id":"48"}],"user_id":"209","_id":"13045","intvolume":"        48","page":"305-311","citation":{"chicago":"Becker, Bernd, Ilia Polian, Sybille Hellebrand, Bernd Straube, and Hans-Joachim Wunderlich. “DFG-Projekt RealTest - Test Und Zuverlässigkeit Nanoelektronischer Systeme.” <i>It - Information Technology</i> 48, no. 5 (2006): 305–11.","ieee":"B. Becker, I. Polian, S. Hellebrand, B. Straube, and H.-J. Wunderlich, “DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme,” <i>it - Information Technology</i>, vol. 48, no. 5, pp. 305–311, 2006.","ama":"Becker B, Polian I, Hellebrand S, Straube B, Wunderlich H-J. DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme. <i>it - Information Technology</i>. 2006;48(5):305-311.","apa":"Becker, B., Polian, I., Hellebrand, S., Straube, B., &#38; Wunderlich, H.-J. (2006). DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme. <i>It - Information Technology</i>, <i>48</i>(5), 305–311.","bibtex":"@article{Becker_Polian_Hellebrand_Straube_Wunderlich_2006, title={DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme}, volume={48}, number={5}, journal={it - Information Technology}, author={Becker, Bernd and Polian, Ilia and Hellebrand, Sybille and Straube, Bernd and Wunderlich, Hans-Joachim}, year={2006}, pages={305–311} }","short":"B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich, It - Information Technology 48 (2006) 305–311.","mla":"Becker, Bernd, et al. “DFG-Projekt RealTest - Test Und Zuverlässigkeit Nanoelektronischer Systeme.” <i>It - Information Technology</i>, vol. 48, no. 5, 2006, pp. 305–11."},"year":"2006","issue":"5","title":"DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme","volume":48,"date_created":"2019-08-28T10:44:53Z","author":[{"last_name":"Becker","full_name":"Becker, Bernd","first_name":"Bernd"},{"last_name":"Polian","full_name":"Polian, Ilia","first_name":"Ilia"},{"orcid":"0000-0002-3717-3939","last_name":"Hellebrand","full_name":"Hellebrand, Sybille","id":"209","first_name":"Sybille"},{"first_name":"Bernd","last_name":"Straube","full_name":"Straube, Bernd"},{"first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich"}],"date_updated":"2022-05-11T16:38:35Z"},{"citation":{"short":"P. Oehler, S. Hellebrand, A Low Power Design for Embedded DRAMs with Online Consistency Checking, Kleinheubachertagung 2005, Miltenberg, Germany, 2005.","bibtex":"@book{Oehler_Hellebrand_2005, place={Kleinheubachertagung 2005, Miltenberg, Germany}, title={A Low Power Design for Embedded DRAMs with Online Consistency Checking}, author={Oehler, Philipp and Hellebrand, Sybille}, year={2005} }","mla":"Oehler, Philipp, and Sybille Hellebrand. <i>A Low Power Design for Embedded DRAMs with Online Consistency Checking</i>. 2005.","apa":"Oehler, P., &#38; Hellebrand, S. (2005). <i>A Low Power Design for Embedded DRAMs with Online Consistency Checking</i>. Kleinheubachertagung 2005, Miltenberg, Germany.","ama":"Oehler P, Hellebrand S. <i>A Low Power Design for Embedded DRAMs with Online Consistency Checking</i>. Kleinheubachertagung 2005, Miltenberg, Germany; 2005.","ieee":"P. Oehler and S. Hellebrand, <i>A Low Power Design for Embedded DRAMs with Online Consistency Checking</i>. Kleinheubachertagung 2005, Miltenberg, Germany, 2005.","chicago":"Oehler, Philipp, and Sybille Hellebrand. <i>A Low Power Design for Embedded DRAMs with Online Consistency Checking</i>. Kleinheubachertagung 2005, Miltenberg, Germany, 2005."},"place":"Kleinheubachertagung 2005, Miltenberg, Germany","year":"2005","author":[{"last_name":"Oehler","full_name":"Oehler, Philipp","first_name":"Philipp"},{"first_name":"Sybille","last_name":"Hellebrand","full_name":"Hellebrand, Sybille"}],"date_created":"2019-08-28T10:45:55Z","date_updated":"2022-01-06T06:51:27Z","title":"A Low Power Design for Embedded DRAMs with Online Consistency Checking","type":"misc","status":"public","user_id":"659","department":[{"_id":"48"}],"_id":"13046","language":[{"iso":"eng"}],"keyword":["WORKSHOP"]},{"status":"public","type":"misc","extern":"1","language":[{"iso":"eng"}],"keyword":["WORKSHOP"],"user_id":"659","department":[{"_id":"48"}],"_id":"13101","citation":{"ama":"Ali M, Welzl M, Hellebrand S. <i>Dynamic Routing: A Prerequisite for Reliable NoCs</i>. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria; 2005.","ieee":"M. Ali, M. Welzl, and S. Hellebrand, <i>Dynamic Routing: A Prerequisite for Reliable NoCs</i>. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.","chicago":"Ali, Muhammad, Michael Welzl, and Sybille Hellebrand. <i>Dynamic Routing: A Prerequisite for Reliable NoCs</i>. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.","bibtex":"@book{Ali_Welzl_Hellebrand_2005, place={17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria}, title={Dynamic Routing: A Prerequisite for Reliable NoCs}, author={Ali, Muhammad and Welzl, Michael and Hellebrand, Sybille}, year={2005} }","short":"M. Ali, M. Welzl, S. Hellebrand, Dynamic Routing: A Prerequisite for Reliable NoCs, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.","mla":"Ali, Muhammad, et al. <i>Dynamic Routing: A Prerequisite for Reliable NoCs</i>. 2005.","apa":"Ali, M., Welzl, M., &#38; Hellebrand, S. (2005). <i>Dynamic Routing: A Prerequisite for Reliable NoCs</i>. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria."},"place":"17th GI/ITG/GMM Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\", Innsbruck, Austria","year":"2005","title":"Dynamic Routing: A Prerequisite for Reliable NoCs","date_created":"2019-08-28T12:22:23Z","author":[{"first_name":"Muhammad","last_name":"Ali","full_name":"Ali, Muhammad"},{"first_name":"Michael","last_name":"Welzl","full_name":"Welzl, Michael"},{"full_name":"Hellebrand, Sybille","id":"209","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","first_name":"Sybille"}],"date_updated":"2022-01-06T06:51:28Z"},{"date_updated":"2022-01-06T06:51:28Z","author":[{"first_name":"Philipp","last_name":"Oehler","full_name":"Oehler, Philipp"},{"full_name":"Hellebrand, Sybille","id":"209","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","first_name":"Sybille"}],"date_created":"2019-08-28T12:23:10Z","title":"Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study","place":"17th GI/ITG/GMM Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\", Innsbruck, Austria","year":"2005","citation":{"ieee":"P. Oehler and S. Hellebrand, <i>Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study</i>. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.","chicago":"Oehler, Philipp, and Sybille Hellebrand. <i>Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study</i>. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.","ama":"Oehler P, Hellebrand S. <i>Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study</i>. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria; 2005.","apa":"Oehler, P., &#38; Hellebrand, S. (2005). <i>Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study</i>. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria.","mla":"Oehler, Philipp, and Sybille Hellebrand. <i>Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study</i>. 2005.","bibtex":"@book{Oehler_Hellebrand_2005, place={17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria}, title={Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study}, author={Oehler, Philipp and Hellebrand, Sybille}, year={2005} }","short":"P. Oehler, S. Hellebrand, Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005."},"_id":"13102","user_id":"659","department":[{"_id":"48"}],"keyword":["WORKSHOP"],"language":[{"iso":"eng"}],"type":"misc","status":"public"},{"language":[{"iso":"eng"}],"_id":"12999","department":[{"_id":"48"}],"user_id":"209","status":"public","publication":"IEEE International Conference on Microelectronics (ICM'05)","type":"conference","title":"Considerations for Fault-Tolerant Networks on Chips","doi":"10.1109/icm.2005.1590063","date_updated":"2022-05-11T16:39:50Z","publisher":"IEEE","author":[{"last_name":"Ali","full_name":"Ali, Muhammad","first_name":"Muhammad"},{"first_name":"Michael","last_name":"Welzl","full_name":"Welzl, Michael"},{"full_name":"Zwicknagl, Martin","last_name":"Zwicknagl","first_name":"Martin"},{"full_name":"Hellebrand, Sybille","id":"209","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","first_name":"Sybille"}],"date_created":"2019-08-28T10:20:55Z","place":"Islamabad, Pakistan","year":"2005","citation":{"mla":"Ali, Muhammad, et al. “Considerations for Fault-Tolerant Networks on Chips.” <i>IEEE International Conference on Microelectronics (ICM’05)</i>, IEEE, 2005, doi:<a href=\"https://doi.org/10.1109/icm.2005.1590063\">10.1109/icm.2005.1590063</a>.","bibtex":"@inproceedings{Ali_Welzl_Zwicknagl_Hellebrand_2005, place={Islamabad, Pakistan}, title={Considerations for Fault-Tolerant Networks on Chips}, DOI={<a href=\"https://doi.org/10.1109/icm.2005.1590063\">10.1109/icm.2005.1590063</a>}, booktitle={IEEE International Conference on Microelectronics (ICM’05)}, publisher={IEEE}, author={Ali, Muhammad and Welzl, Michael and Zwicknagl, Martin and Hellebrand, Sybille}, year={2005} }","short":"M. Ali, M. Welzl, M. Zwicknagl, S. Hellebrand, in: IEEE International Conference on Microelectronics (ICM’05), IEEE, Islamabad, Pakistan, 2005.","apa":"Ali, M., Welzl, M., Zwicknagl, M., &#38; Hellebrand, S. (2005). Considerations for Fault-Tolerant Networks on Chips. <i>IEEE International Conference on Microelectronics (ICM’05)</i>. <a href=\"https://doi.org/10.1109/icm.2005.1590063\">https://doi.org/10.1109/icm.2005.1590063</a>","ama":"Ali M, Welzl M, Zwicknagl M, Hellebrand S. Considerations for Fault-Tolerant Networks on Chips. In: <i>IEEE International Conference on Microelectronics (ICM’05)</i>. IEEE; 2005. doi:<a href=\"https://doi.org/10.1109/icm.2005.1590063\">10.1109/icm.2005.1590063</a>","chicago":"Ali, Muhammad, Michael Welzl, Martin Zwicknagl, and Sybille Hellebrand. “Considerations for Fault-Tolerant Networks on Chips.” In <i>IEEE International Conference on Microelectronics (ICM’05)</i>. Islamabad, Pakistan: IEEE, 2005. <a href=\"https://doi.org/10.1109/icm.2005.1590063\">https://doi.org/10.1109/icm.2005.1590063</a>.","ieee":"M. Ali, M. Welzl, M. Zwicknagl, and S. Hellebrand, “Considerations for Fault-Tolerant Networks on Chips,” 2005, doi: <a href=\"https://doi.org/10.1109/icm.2005.1590063\">10.1109/icm.2005.1590063</a>."}},{"type":"conference","publication":"10th IEEE European Test Symposium (ETS'05)","status":"public","user_id":"209","department":[{"_id":"48"}],"_id":"13000","language":[{"iso":"eng"}],"citation":{"apa":"Oehler, P., &#38; Hellebrand, S. (2005). Low Power Embedded DRAMs with High Quality Error Correcting Capabilities. <i>10th IEEE European Test Symposium (ETS’05)</i>, 148–153. <a href=\"https://doi.org/10.1109/ets.2005.28\">https://doi.org/10.1109/ets.2005.28</a>","mla":"Oehler, Philipp, and Sybille Hellebrand. “Low Power Embedded DRAMs with High Quality Error Correcting Capabilities.” <i>10th IEEE European Test Symposium (ETS’05)</i>, IEEE, 2005, pp. 148–53, doi:<a href=\"https://doi.org/10.1109/ets.2005.28\">10.1109/ets.2005.28</a>.","short":"P. Oehler, S. Hellebrand, in: 10th IEEE European Test Symposium (ETS’05), IEEE, Tallinn, Estonia, 2005, pp. 148–153.","bibtex":"@inproceedings{Oehler_Hellebrand_2005, place={Tallinn, Estonia}, title={Low Power Embedded DRAMs with High Quality Error Correcting Capabilities}, DOI={<a href=\"https://doi.org/10.1109/ets.2005.28\">10.1109/ets.2005.28</a>}, booktitle={10th IEEE European Test Symposium (ETS’05)}, publisher={IEEE}, author={Oehler, Philipp and Hellebrand, Sybille}, year={2005}, pages={148–153} }","ama":"Oehler P, Hellebrand S. Low Power Embedded DRAMs with High Quality Error Correcting Capabilities. In: <i>10th IEEE European Test Symposium (ETS’05)</i>. IEEE; 2005:148-153. doi:<a href=\"https://doi.org/10.1109/ets.2005.28\">10.1109/ets.2005.28</a>","ieee":"P. Oehler and S. Hellebrand, “Low Power Embedded DRAMs with High Quality Error Correcting Capabilities,” in <i>10th IEEE European Test Symposium (ETS’05)</i>, 2005, pp. 148–153, doi: <a href=\"https://doi.org/10.1109/ets.2005.28\">10.1109/ets.2005.28</a>.","chicago":"Oehler, Philipp, and Sybille Hellebrand. “Low Power Embedded DRAMs with High Quality Error Correcting Capabilities.” In <i>10th IEEE European Test Symposium (ETS’05)</i>, 148–53. Tallinn, Estonia: IEEE, 2005. <a href=\"https://doi.org/10.1109/ets.2005.28\">https://doi.org/10.1109/ets.2005.28</a>."},"page":"148-153","place":"Tallinn, Estonia","year":"2005","author":[{"first_name":"Philipp","last_name":"Oehler","full_name":"Oehler, Philipp"},{"first_name":"Sybille","id":"209","full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand"}],"date_created":"2019-08-28T10:20:56Z","publisher":"IEEE","date_updated":"2022-05-11T16:40:36Z","doi":"10.1109/ets.2005.28","title":"Low Power Embedded DRAMs with High Quality Error Correcting Capabilities"}]