---
_id: '19421'
author:
- first_name: Stefan
full_name: Holst, Stefan
last_name: Holst
- first_name: Matthias
full_name: Kampmann, Matthias
id: '10935'
last_name: Kampmann
- first_name: Alexander
full_name: Sprenger, Alexander
id: '22707'
last_name: Sprenger
- first_name: Jan Dennis
full_name: Reimer, Jan Dennis
id: '36703'
last_name: Reimer
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
- first_name: Xiaoqing
full_name: Weng, Xiaoqing
last_name: Weng
citation:
ama: 'Holst S, Kampmann M, Sprenger A, et al. Logic Fault Diagnosis of Hidden Delay
Defects. In: IEEE International Test Conference (ITC’20), November 2020.
; 2020.'
apa: Holst, S., Kampmann, M., Sprenger, A., Reimer, J. D., Hellebrand, S., Wunderlich,
H.-J., & Weng, X. (2020). Logic Fault Diagnosis of Hidden Delay Defects. IEEE
International Test Conference (ITC’20), November 2020.
bibtex: '@inproceedings{Holst_Kampmann_Sprenger_Reimer_Hellebrand_Wunderlich_Weng_2020,
place={Virtual Conference - Originally Washington, DC, USA}, title={Logic Fault
Diagnosis of Hidden Delay Defects}, booktitle={IEEE International Test Conference
(ITC’20), November 2020}, author={Holst, Stefan and Kampmann, Matthias and Sprenger,
Alexander and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim
and Weng, Xiaoqing}, year={2020} }'
chicago: Holst, Stefan, Matthias Kampmann, Alexander Sprenger, Jan Dennis Reimer,
Sybille Hellebrand, Hans-Joachim Wunderlich, and Xiaoqing Weng. “Logic Fault Diagnosis
of Hidden Delay Defects.” In IEEE International Test Conference (ITC’20), November
2020. Virtual Conference - Originally Washington, DC, USA, 2020.
ieee: S. Holst et al., “Logic Fault Diagnosis of Hidden Delay Defects,” 2020.
mla: Holst, Stefan, et al. “Logic Fault Diagnosis of Hidden Delay Defects.” IEEE
International Test Conference (ITC’20), November 2020, 2020.
short: 'S. Holst, M. Kampmann, A. Sprenger, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich,
X. Weng, in: IEEE International Test Conference (ITC’20), November 2020, Virtual
Conference - Originally Washington, DC, USA, 2020.'
date_created: 2020-09-15T13:56:08Z
date_updated: 2022-05-11T17:08:20Z
department:
- _id: '48'
language:
- iso: eng
place: Virtual Conference - Originally Washington, DC, USA
publication: IEEE International Test Conference (ITC'20), November 2020
publication_status: published
status: public
title: Logic Fault Diagnosis of Hidden Delay Defects
type: conference
user_id: '209'
year: '2020'
...
---
_id: '8112'
author:
- first_name: Mohammad Urf
full_name: Maaz, Mohammad Urf
id: '49274'
last_name: Maaz
- first_name: Alexander
full_name: Sprenger, Alexander
id: '22707'
last_name: Sprenger
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Maaz MU, Sprenger A, Hellebrand S. A Hybrid Space Compactor for Varying
X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen” (TuZ’19); 2019.'
apa: 'Maaz, M. U., Sprenger, A., & Hellebrand, S. (2019). A Hybrid Space
Compactor for Varying X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19).'
bibtex: '@book{Maaz_Sprenger_Hellebrand_2019, place={Prien am Chiemsee}, title={A
Hybrid Space Compactor for Varying X-Rates}, publisher={31. Workshop “Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19)}, author={Maaz, Mohammad
Urf and Sprenger, Alexander and Hellebrand, Sybille}, year={2019} }'
chicago: 'Maaz, Mohammad Urf, Alexander Sprenger, and Sybille Hellebrand. A Hybrid
Space Compactor for Varying X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19), 2019.'
ieee: 'M. U. Maaz, A. Sprenger, and S. Hellebrand, A Hybrid Space Compactor for
Varying X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen” (TuZ’19), 2019.'
mla: Maaz, Mohammad Urf, et al. A Hybrid Space Compactor for Varying X-Rates.
31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19),
2019.
short: M.U. Maaz, A. Sprenger, S. Hellebrand, A Hybrid Space Compactor for Varying
X-Rates, 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
(TuZ’19), Prien am Chiemsee, 2019.
date_created: 2019-02-26T15:11:02Z
date_updated: 2022-01-06T07:03:51Z
department:
- _id: '48'
keyword:
- WORKSHOP
language:
- iso: eng
place: Prien am Chiemsee
publisher: 31. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
(TuZ'19)
status: public
title: A Hybrid Space Compactor for Varying X-Rates
type: misc
user_id: '209'
year: '2019'
...
---
_id: '8667'
author:
- first_name: Alexander
full_name: Sprenger, Alexander
id: '22707'
last_name: Sprenger
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: Sprenger A, Hellebrand S. Divide and Compact - Stochastic Space Compaction
for Faster-than-At-Speed Test. Journal of Circuits, Systems and Computers.
2019;28(1):1-23. doi:10.1142/s0218126619400012
apa: Sprenger, A., & Hellebrand, S. (2019). Divide and Compact - Stochastic
Space Compaction for Faster-than-At-Speed Test. Journal of Circuits, Systems
and Computers, 28(1), 1–23. https://doi.org/10.1142/s0218126619400012
bibtex: '@article{Sprenger_Hellebrand_2019, title={Divide and Compact - Stochastic
Space Compaction for Faster-than-At-Speed Test}, volume={28}, DOI={10.1142/s0218126619400012},
number={1}, journal={Journal of Circuits, Systems and Computers}, publisher={World
Scientific Publishing Company}, author={Sprenger, Alexander and Hellebrand, Sybille},
year={2019}, pages={1–23} }'
chicago: 'Sprenger, Alexander, and Sybille Hellebrand. “Divide and Compact - Stochastic
Space Compaction for Faster-than-At-Speed Test.” Journal of Circuits, Systems
and Computers 28, no. 1 (2019): 1–23. https://doi.org/10.1142/s0218126619400012.'
ieee: A. Sprenger and S. Hellebrand, “Divide and Compact - Stochastic Space Compaction
for Faster-than-At-Speed Test,” Journal of Circuits, Systems and Computers,
vol. 28, no. 1, pp. 1–23, 2019.
mla: Sprenger, Alexander, and Sybille Hellebrand. “Divide and Compact - Stochastic
Space Compaction for Faster-than-At-Speed Test.” Journal of Circuits, Systems
and Computers, vol. 28, no. 1, World Scientific Publishing Company, 2019,
pp. 1–23, doi:10.1142/s0218126619400012.
short: A. Sprenger, S. Hellebrand, Journal of Circuits, Systems and Computers 28
(2019) 1–23.
date_created: 2019-03-27T08:57:42Z
date_updated: 2022-01-06T07:03:58Z
department:
- _id: '48'
doi: 10.1142/s0218126619400012
intvolume: ' 28'
issue: '1'
language:
- iso: eng
page: 1-23
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Journal of Circuits, Systems and Computers
publication_identifier:
issn:
- 0218-1266
- 1793-6454
publication_status: published
publisher: World Scientific Publishing Company
status: public
title: Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test
type: journal_article
user_id: '59789'
volume: 28
year: '2019'
...
---
_id: '13048'
abstract:
- lang: eng
text: Marginal hardware introduces severe reliability threats throughout the life
cycle of a system. Although marginalities may not affect the functionality of
a circuit immediately after manufacturing, they can degrade into hard failures
and must be screened out during manufacturing test to prevent early life failures.
Furthermore, their evolution in the field must be proactively monitored by periodic
tests before actual failures occur. In recent years small delay faults have gained
increasing attention as possible indicators of marginal hardware. However, small
delay faults on short paths may be undetectable even with advanced timing aware
ATPG. Faster-than-at-speed test (FAST) can detect such hidden delay faults, but
so far FAST has mainly been restricted to manufacturing test.
author:
- first_name: Matthias
full_name: Kampmann, Matthias
id: '10935'
last_name: Kampmann
- first_name: Michael
full_name: A. Kochte, Michael
last_name: A. Kochte
- first_name: Chang
full_name: Liu, Chang
last_name: Liu
- first_name: Eric
full_name: Schneider, Eric
last_name: Schneider
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: Kampmann M, A. Kochte M, Liu C, Schneider E, Hellebrand S, Wunderlich H-J.
Built-in Test for Hidden Delay Faults. IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems (TCAD). 2019;38(10):1956-1968.
apa: Kampmann, M., A. Kochte, M., Liu, C., Schneider, E., Hellebrand, S., &
Wunderlich, H.-J. (2019). Built-in Test for Hidden Delay Faults. IEEE Transactions
on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 38(10),
1956–1968.
bibtex: '@article{Kampmann_A. Kochte_Liu_Schneider_Hellebrand_Wunderlich_2019, title={Built-in
Test for Hidden Delay Faults}, volume={38}, number={10}, journal={IEEE Transactions
on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}, publisher={IEEE},
author={Kampmann, Matthias and A. Kochte, Michael and Liu, Chang and Schneider,
Eric and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2019}, pages={1956–1968}
}'
chicago: 'Kampmann, Matthias, Michael A. Kochte, Chang Liu, Eric Schneider, Sybille
Hellebrand, and Hans-Joachim Wunderlich. “Built-in Test for Hidden Delay Faults.”
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
(TCAD) 38, no. 10 (2019): 1956–68.'
ieee: M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, and H.-J.
Wunderlich, “Built-in Test for Hidden Delay Faults,” IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems (TCAD), vol. 38, no. 10, pp. 1956–1968,
2019.
mla: Kampmann, Matthias, et al. “Built-in Test for Hidden Delay Faults.” IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD),
vol. 38, no. 10, IEEE, 2019, pp. 1956–68.
short: M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, H.-J. Wunderlich,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
(TCAD) 38 (2019) 1956–1968.
date_created: 2019-08-28T11:44:25Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '48'
intvolume: ' 38'
issue: '10'
language:
- iso: eng
page: 1956 - 1968
publication: IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems (TCAD)
publication_identifier:
eissn:
- 1937-4151
publication_status: published
publisher: IEEE
status: public
title: Built-in Test for Hidden Delay Faults
type: journal_article
user_id: '209'
volume: 38
year: '2019'
...
---
_id: '12918'
abstract:
- lang: eng
text: 'The test for small delay faults is of major importance for predicting potential
early life failures or wearout problems. Typically, a faster-than-at-speed test
(FAST) with sev¬eral different frequencies is used to detect also hidden small
delays, which can only be propagated over short paths. But then the outputs at
the end of long paths may no longer reach their stable values at the nominal observation
time and must be considered as unknown (X-values). Thus, test response compaction
for FAST must be extremely flexible to cope with high X-rates, which also vary
with the test frequencies. Stochastic compaction introduced by Mitra et al. is
controlled by weighted pseudo-random signals allowing for easy adaptation to varying
conditions. As demonstrated in previous work, the pseudo-random control can be
optimized for high fault efficiency or X-reduction, but a given target in fault
efficiency cannot be guaranteed. To close this gap, a hybrid space compactor is
introduced in this paper. It is based on the observation that many faults are
lost in the compaction of relatively few critical test patterns. For these critical
patterns a deterministic compaction phase is added to the test, where the existing
compactor structure is re-used, but controlled by specifically determined control
vectors. '
author:
- first_name: Mohammad Urf
full_name: Maaz, Mohammad Urf
id: '49274'
last_name: Maaz
- first_name: Alexander
full_name: Sprenger, Alexander
id: '22707'
last_name: Sprenger
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Maaz MU, Sprenger A, Hellebrand S. A Hybrid Space Compactor for Adaptive X-Handling.
In: 50th IEEE International Test Conference (ITC). IEEE; 2019:1-8.'
apa: Maaz, M. U., Sprenger, A., & Hellebrand, S. (2019). A Hybrid Space Compactor
for Adaptive X-Handling. 50th IEEE International Test Conference (ITC),
1–8.
bibtex: '@inproceedings{Maaz_Sprenger_Hellebrand_2019, place={Washington, DC, USA},
title={A Hybrid Space Compactor for Adaptive X-Handling}, booktitle={50th IEEE
International Test Conference (ITC)}, publisher={IEEE}, author={Maaz, Mohammad
Urf and Sprenger, Alexander and Hellebrand, Sybille}, year={2019}, pages={1–8}
}'
chicago: 'Maaz, Mohammad Urf, Alexander Sprenger, and Sybille Hellebrand. “A Hybrid
Space Compactor for Adaptive X-Handling.” In 50th IEEE International Test Conference
(ITC), 1–8. Washington, DC, USA: IEEE, 2019.'
ieee: M. U. Maaz, A. Sprenger, and S. Hellebrand, “A Hybrid Space Compactor for
Adaptive X-Handling,” in 50th IEEE International Test Conference (ITC),
Washington, DC, USA, 2019, pp. 1–8.
mla: Maaz, Mohammad Urf, et al. “A Hybrid Space Compactor for Adaptive X-Handling.”
50th IEEE International Test Conference (ITC), IEEE, 2019, pp. 1–8.
short: 'M.U. Maaz, A. Sprenger, S. Hellebrand, in: 50th IEEE International Test
Conference (ITC), IEEE, Washington, DC, USA, 2019, pp. 1–8.'
conference:
end_date: 2019-11-14
location: Washington, DC, USA
name: 50th IEEE International Test Conference (ITC)
start_date: 2019-11-12
date_created: 2019-08-14T06:59:04Z
date_updated: 2022-05-11T17:09:35Z
department:
- _id: '48'
keyword:
- Faster-than-at-speed test
- BIST
- DFT
- Test response compaction
- Stochastic compactor
- X-handling
language:
- iso: eng
page: 1-8
place: Washington, DC, USA
publication: 50th IEEE International Test Conference (ITC)
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: A Hybrid Space Compactor for Adaptive X-Handling
type: conference
user_id: '209'
year: '2019'
...
---
_id: '4576'
author:
- first_name: Alexander
full_name: Sprenger, Alexander
id: '22707'
last_name: Sprenger
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Sprenger A, Hellebrand S. Stochastische Kompaktierung für den Hochgeschwindigkeitstest.
Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen
und Systemen” (TuZ’18); 2018.'
apa: 'Sprenger, A., & Hellebrand, S. (2018). Stochastische Kompaktierung
für den Hochgeschwindigkeitstest. Freiburg, Germany: 30. Workshop “Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18).'
bibtex: '@book{Sprenger_Hellebrand_2018, place={Freiburg, Germany}, title={Stochastische
Kompaktierung für den Hochgeschwindigkeitstest}, publisher={30. Workshop “Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18)}, author={Sprenger,
Alexander and Hellebrand, Sybille}, year={2018} }'
chicago: 'Sprenger, Alexander, and Sybille Hellebrand. Stochastische Kompaktierung
für den Hochgeschwindigkeitstest. Freiburg, Germany: 30. Workshop “Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), 2018.'
ieee: 'A. Sprenger and S. Hellebrand, Stochastische Kompaktierung für den Hochgeschwindigkeitstest.
Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen
und Systemen” (TuZ’18), 2018.'
mla: Sprenger, Alexander, and Sybille Hellebrand. Stochastische Kompaktierung
für den Hochgeschwindigkeitstest. 30. Workshop “Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen” (TuZ’18), 2018.
short: A. Sprenger, S. Hellebrand, Stochastische Kompaktierung für den Hochgeschwindigkeitstest,
30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18),
Freiburg, Germany, 2018.
date_created: 2018-10-02T12:29:44Z
date_updated: 2022-01-06T07:01:13Z
department:
- _id: '48'
keyword:
- WORKSHOP
language:
- iso: ger
place: Freiburg, Germany
publisher: 30. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
(TuZ'18)
status: public
title: Stochastische Kompaktierung für den Hochgeschwindigkeitstest
type: misc
user_id: '22707'
year: '2018'
...
---
_id: '12974'
author:
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Joerg
full_name: Henkel, Joerg
last_name: Henkel
- first_name: Anand
full_name: Raghunathan, Anand
last_name: Raghunathan
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: Hellebrand S, Henkel J, Raghunathan A, Wunderlich H-J. Guest Editors’ Introduction
- Special Issue on Approximate Computing. IEEE Embedded Systems Letters.
2018;10(1):1-1. doi:10.1109/les.2018.2789942
apa: Hellebrand, S., Henkel, J., Raghunathan, A., & Wunderlich, H.-J. (2018).
Guest Editors’ Introduction - Special Issue on Approximate Computing. IEEE
Embedded Systems Letters, 10(1), 1–1. https://doi.org/10.1109/les.2018.2789942
bibtex: '@article{Hellebrand_Henkel_Raghunathan_Wunderlich_2018, title={Guest Editors’
Introduction - Special Issue on Approximate Computing}, volume={10}, DOI={10.1109/les.2018.2789942},
number={1}, journal={IEEE Embedded Systems Letters}, publisher={IEEE}, author={Hellebrand,
Sybille and Henkel, Joerg and Raghunathan, Anand and Wunderlich, Hans-Joachim},
year={2018}, pages={1–1} }'
chicago: 'Hellebrand, Sybille, Joerg Henkel, Anand Raghunathan, and Hans-Joachim
Wunderlich. “Guest Editors’ Introduction - Special Issue on Approximate Computing.”
IEEE Embedded Systems Letters 10, no. 1 (2018): 1–1. https://doi.org/10.1109/les.2018.2789942.'
ieee: S. Hellebrand, J. Henkel, A. Raghunathan, and H.-J. Wunderlich, “Guest Editors’
Introduction - Special Issue on Approximate Computing,” IEEE Embedded Systems
Letters, vol. 10, no. 1, pp. 1–1, 2018.
mla: Hellebrand, Sybille, et al. “Guest Editors’ Introduction - Special Issue on
Approximate Computing.” IEEE Embedded Systems Letters, vol. 10, no. 1,
IEEE, 2018, pp. 1–1, doi:10.1109/les.2018.2789942.
short: S. Hellebrand, J. Henkel, A. Raghunathan, H.-J. Wunderlich, IEEE Embedded
Systems Letters 10 (2018) 1–1.
date_created: 2019-08-28T08:40:58Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '48'
doi: 10.1109/les.2018.2789942
intvolume: ' 10'
issue: '1'
language:
- iso: eng
page: 1-1
publication: IEEE Embedded Systems Letters
publisher: IEEE
status: public
title: Guest Editors' Introduction - Special Issue on Approximate Computing
type: journal_article
user_id: '209'
volume: 10
year: '2018'
...
---
_id: '13057'
author:
- first_name: Matthias
full_name: Kampmann, Matthias
id: '10935'
last_name: Kampmann
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: Kampmann M, Hellebrand S. Design For Small Delay Test - A Simulation Study.
Microelectronics Reliability. 2018;80:124-133.
apa: Kampmann, M., & Hellebrand, S. (2018). Design For Small Delay Test - A
Simulation Study. Microelectronics Reliability, 80, 124–133.
bibtex: '@article{Kampmann_Hellebrand_2018, title={Design For Small Delay Test -
A Simulation Study}, volume={80}, journal={Microelectronics Reliability}, author={Kampmann,
Matthias and Hellebrand, Sybille}, year={2018}, pages={124–133} }'
chicago: 'Kampmann, Matthias, and Sybille Hellebrand. “Design For Small Delay Test
- A Simulation Study.” Microelectronics Reliability 80 (2018): 124–33.'
ieee: M. Kampmann and S. Hellebrand, “Design For Small Delay Test - A Simulation
Study,” Microelectronics Reliability, vol. 80, pp. 124–133, 2018.
mla: Kampmann, Matthias, and Sybille Hellebrand. “Design For Small Delay Test -
A Simulation Study.” Microelectronics Reliability, vol. 80, 2018, pp. 124–33.
short: M. Kampmann, S. Hellebrand, Microelectronics Reliability 80 (2018) 124–133.
date_created: 2019-08-28T11:49:25Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '48'
intvolume: ' 80'
language:
- iso: eng
page: 124-133
publication: Microelectronics Reliability
status: public
title: Design For Small Delay Test - A Simulation Study
type: journal_article
user_id: '659'
volume: 80
year: '2018'
...
---
_id: '13072'
author:
- first_name: Matthias
full_name: Kampmann, Matthias
id: '10935'
last_name: Kampmann
- first_name: Sybille
full_name: Hellebrand, Sybille
last_name: Hellebrand
citation:
ama: Kampmann M, Hellebrand S. Optimized Constraints for Scan-Chain Insertion
for Faster-than-at-Speed Test. 19th Workshop on RTL and High Level Testing
(WRTLT’18), Hefei, Anhui, China; 2018.
apa: Kampmann, M., & Hellebrand, S. (2018). Optimized Constraints for Scan-Chain
Insertion for Faster-than-at-Speed Test. 19th Workshop on RTL and High Level
Testing (WRTLT’18), Hefei, Anhui, China.
bibtex: '@book{Kampmann_Hellebrand_2018, place={19th Workshop on RTL and High Level
Testing (WRTLT’18), Hefei, Anhui, China}, title={Optimized Constraints for Scan-Chain
Insertion for Faster-than-at-Speed Test}, author={Kampmann, Matthias and Hellebrand,
Sybille}, year={2018} }'
chicago: Kampmann, Matthias, and Sybille Hellebrand. Optimized Constraints for
Scan-Chain Insertion for Faster-than-at-Speed Test. 19th Workshop on RTL and
High Level Testing (WRTLT’18), Hefei, Anhui, China, 2018.
ieee: M. Kampmann and S. Hellebrand, Optimized Constraints for Scan-Chain Insertion
for Faster-than-at-Speed Test. 19th Workshop on RTL and High Level Testing
(WRTLT’18), Hefei, Anhui, China, 2018.
mla: Kampmann, Matthias, and Sybille Hellebrand. Optimized Constraints for Scan-Chain
Insertion for Faster-than-at-Speed Test. 2018.
short: M. Kampmann, S. Hellebrand, Optimized Constraints for Scan-Chain Insertion
for Faster-than-at-Speed Test, 19th Workshop on RTL and High Level Testing (WRTLT’18),
Hefei, Anhui, China, 2018.
date_created: 2019-08-28T12:00:28Z
date_updated: 2022-01-06T06:51:28Z
department:
- _id: '48'
keyword:
- WORKSHOP
language:
- iso: eng
place: 19th Workshop on RTL and High Level Testing (WRTLT'18), Hefei, Anhui, China
status: public
title: Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test
type: misc
user_id: '659'
year: '2018'
...
---
_id: '29460'
abstract:
- lang: eng
text: STT-RAM cells can be considered as an alternative or a hybrid addition to
today's SRAM-based cache memories. This is mostly because of their scalability
and low leakage power. Moreover, their data storing mechanism (storing the value
as resistance) makes them very suitable and applicable for multivalue cache architectures.
This feature results in system performance enhancement without any area overhead.
On the other hand, the required two-step read/write procedure in multilevel cells
results in a non-uniform time access and energy and power overhead on the system.
In this paper, we propose a new architecture to dynamically swap data between
soft (fast read access) and hard (slow read access) bits in ML cell. Moreover,
by reconfiguring cache block size, the proposed architecture can switch between
ML and SL modes at runtime. In other words, the swapping method places the hot
part of each cache block into soft-bits and the less accessed part into the hard-bits.
The SL/ML switching method benefits from the low latency and energy of SL mode
and the high storing capacity of ML mode at the same time. Although experimental
results show that our proposed method slightly increases the miss rate compared
with the conventional ML caches, the performance and energy are improved by 4.9%
and 6.5%, respectively. Also, the storage overhead of our method is about 1% that
is negligible.
author:
- first_name: Ramin
full_name: Rezaeizadeh Rookerd, Ramin
last_name: Rezaeizadeh Rookerd
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
- first_name: Zainalabedin
full_name: Navabi, Zainalabedin
last_name: Navabi
citation:
ama: 'Rezaeizadeh Rookerd R, Sadeghi-Kohan S, Navabi Z. Performance and Energy Enhancement
through an Online Single/Multi Level Mode Switching Cache Architecture. In: Proceedings
of the 2018 on Great Lakes Symposium on VLSI. ACM; 2018. doi:10.1145/3194554.3194599'
apa: Rezaeizadeh Rookerd, R., Sadeghi-Kohan, S., & Navabi, Z. (2018). Performance
and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache
Architecture. Proceedings of the 2018 on Great Lakes Symposium on VLSI.
https://doi.org/10.1145/3194554.3194599
bibtex: '@inproceedings{Rezaeizadeh Rookerd_Sadeghi-Kohan_Navabi_2018, title={Performance
and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache
Architecture}, DOI={10.1145/3194554.3194599},
booktitle={Proceedings of the 2018 on Great Lakes Symposium on VLSI}, publisher={ACM},
author={Rezaeizadeh Rookerd, Ramin and Sadeghi-Kohan, Somayeh and Navabi, Zainalabedin},
year={2018} }'
chicago: Rezaeizadeh Rookerd, Ramin, Somayeh Sadeghi-Kohan, and Zainalabedin Navabi.
“Performance and Energy Enhancement through an Online Single/Multi Level Mode
Switching Cache Architecture.” In Proceedings of the 2018 on Great Lakes Symposium
on VLSI. ACM, 2018. https://doi.org/10.1145/3194554.3194599.
ieee: 'R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, and Z. Navabi, “Performance and
Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture,”
2018, doi: 10.1145/3194554.3194599.'
mla: Rezaeizadeh Rookerd, Ramin, et al. “Performance and Energy Enhancement through
an Online Single/Multi Level Mode Switching Cache Architecture.” Proceedings
of the 2018 on Great Lakes Symposium on VLSI, ACM, 2018, doi:10.1145/3194554.3194599.
short: 'R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, Z. Navabi, in: Proceedings of
the 2018 on Great Lakes Symposium on VLSI, ACM, 2018.'
date_created: 2022-01-19T13:42:27Z
date_updated: 2022-01-19T13:44:17Z
department:
- _id: '48'
doi: 10.1145/3194554.3194599
language:
- iso: eng
publication: Proceedings of the 2018 on Great Lakes Symposium on VLSI
publication_status: published
publisher: ACM
status: public
title: Performance and Energy Enhancement through an Online Single/Multi Level Mode
Switching Cache Architecture
type: conference
user_id: '78614'
year: '2018'
...
---
_id: '4575'
author:
- first_name: Alexander
full_name: Sprenger, Alexander
id: '22707'
last_name: Sprenger
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Sprenger A, Hellebrand S. Tuning Stochastic Space Compaction to Faster-than-at-Speed
Test. In: 2018 IEEE 21st International Symposium on Design and Diagnostics
of Electronic Circuits & Systems (DDECS). IEEE; 2018. doi:10.1109/ddecs.2018.00020'
apa: Sprenger, A., & Hellebrand, S. (2018). Tuning Stochastic Space Compaction
to Faster-than-at-Speed Test. 2018 IEEE 21st International Symposium on Design
and Diagnostics of Electronic Circuits & Systems (DDECS). https://doi.org/10.1109/ddecs.2018.00020
bibtex: '@inproceedings{Sprenger_Hellebrand_2018, place={Budapest, Hungary}, title={Tuning
Stochastic Space Compaction to Faster-than-at-Speed Test}, DOI={10.1109/ddecs.2018.00020},
booktitle={2018 IEEE 21st International Symposium on Design and Diagnostics of
Electronic Circuits & Systems (DDECS)}, publisher={IEEE}, author={Sprenger,
Alexander and Hellebrand, Sybille}, year={2018} }'
chicago: 'Sprenger, Alexander, and Sybille Hellebrand. “Tuning Stochastic Space
Compaction to Faster-than-at-Speed Test.” In 2018 IEEE 21st International Symposium
on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Budapest,
Hungary: IEEE, 2018. https://doi.org/10.1109/ddecs.2018.00020.'
ieee: 'A. Sprenger and S. Hellebrand, “Tuning Stochastic Space Compaction to Faster-than-at-Speed
Test,” 2018, doi: 10.1109/ddecs.2018.00020.'
mla: Sprenger, Alexander, and Sybille Hellebrand. “Tuning Stochastic Space Compaction
to Faster-than-at-Speed Test.” 2018 IEEE 21st International Symposium on Design
and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, 2018,
doi:10.1109/ddecs.2018.00020.
short: 'A. Sprenger, S. Hellebrand, in: 2018 IEEE 21st International Symposium on
Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, Budapest,
Hungary, 2018.'
date_created: 2018-10-02T12:18:46Z
date_updated: 2022-05-11T17:10:37Z
department:
- _id: '48'
doi: 10.1109/ddecs.2018.00020
language:
- iso: eng
place: Budapest, Hungary
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic
Circuits & Systems (DDECS)
publication_identifier:
isbn:
- '9781538657546'
publication_status: published
publisher: IEEE
status: public
title: Tuning Stochastic Space Compaction to Faster-than-at-Speed Test
type: conference
user_id: '209'
year: '2018'
...
---
_id: '10575'
author:
- first_name: Chang
full_name: Liu, Chang
last_name: Liu
- first_name: Eric
full_name: Schneider, Eric
last_name: Schneider
- first_name: Matthias
full_name: Kampmann, Matthias
id: '10935'
last_name: Kampmann
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: 'Liu C, Schneider E, Kampmann M, Hellebrand S, Wunderlich H-J. Extending Aging
Monitors for Early Life and Wear-Out Failure Prevention. In: 27th IEEE Asian
Test Symposium (ATS’18). ; 2018. doi:10.1109/ats.2018.00028'
apa: Liu, C., Schneider, E., Kampmann, M., Hellebrand, S., & Wunderlich, H.-J.
(2018). Extending Aging Monitors for Early Life and Wear-Out Failure Prevention.
27th IEEE Asian Test Symposium (ATS’18). https://doi.org/10.1109/ats.2018.00028
bibtex: '@inproceedings{Liu_Schneider_Kampmann_Hellebrand_Wunderlich_2018, title={Extending
Aging Monitors for Early Life and Wear-Out Failure Prevention}, DOI={10.1109/ats.2018.00028},
booktitle={27th IEEE Asian Test Symposium (ATS’18)}, author={Liu, Chang and Schneider,
Eric and Kampmann, Matthias and Hellebrand, Sybille and Wunderlich, Hans-Joachim},
year={2018} }'
chicago: Liu, Chang, Eric Schneider, Matthias Kampmann, Sybille Hellebrand, and
Hans-Joachim Wunderlich. “Extending Aging Monitors for Early Life and Wear-Out
Failure Prevention.” In 27th IEEE Asian Test Symposium (ATS’18), 2018.
https://doi.org/10.1109/ats.2018.00028.
ieee: 'C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, and H.-J. Wunderlich, “Extending
Aging Monitors for Early Life and Wear-Out Failure Prevention,” 2018, doi: 10.1109/ats.2018.00028.'
mla: Liu, Chang, et al. “Extending Aging Monitors for Early Life and Wear-Out Failure
Prevention.” 27th IEEE Asian Test Symposium (ATS’18), 2018, doi:10.1109/ats.2018.00028.
short: 'C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, H.-J. Wunderlich, in:
27th IEEE Asian Test Symposium (ATS’18), 2018.'
date_created: 2019-07-05T08:14:58Z
date_updated: 2022-05-11T17:11:53Z
department:
- _id: '48'
doi: 10.1109/ats.2018.00028
language:
- iso: eng
publication: 27th IEEE Asian Test Symposium (ATS'18)
publication_identifier:
isbn:
- '9781538694664'
publication_status: published
status: public
title: Extending Aging Monitors for Early Life and Wear-Out Failure Prevention
type: conference
user_id: '209'
year: '2018'
...
---
_id: '29459'
abstract:
- lang: eng
text: Transistor and interconnect wearout is accelerated with transistor scaling
resulting in timing variations and consequently reliability challenges in digital
circuits. With the emergence of new issues like Electro-migration these problems
are getting more crucial. Age monitoring methods can be used to predict and deal
with the aging problem. Selecting appropriate locations for placement of aging
monitors is an important issue. In this work we propose a procedure for selection
of appropriate internal nodes that expose smaller overheads to the circuit, using
correlation between nodes and the shareability amongst them. To select internal
nodes, we first prune some nodes based on some attributes and thus provide a near-optimal
solution that can effectively get a number of internal nodes and consider the
effects of electro-migration as well. We have applied our proposed scheme to several
processors and ITC benchmarks and have looked at its effectiveness for these circuits.
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Arash
full_name: Vafaei, Arash
last_name: Vafaei
- first_name: Zainalabedin
full_name: Navabi, Zainalabedin
last_name: Navabi
citation:
ama: 'Sadeghi-Kohan S, Vafaei A, Navabi Z. Near-Optimal Node Selection Procedure
for Aging Monitor Placement. In: 2018 IEEE 24th International Symposium on
On-Line Testing And Robust System Design (IOLTS). IEEE; 2018. doi:10.1109/iolts.2018.8474120'
apa: Sadeghi-Kohan, S., Vafaei, A., & Navabi, Z. (2018). Near-Optimal Node Selection
Procedure for Aging Monitor Placement. 2018 IEEE 24th International Symposium
on On-Line Testing And Robust System Design (IOLTS). https://doi.org/10.1109/iolts.2018.8474120
bibtex: '@inproceedings{Sadeghi-Kohan_Vafaei_Navabi_2018, title={Near-Optimal Node
Selection Procedure for Aging Monitor Placement}, DOI={10.1109/iolts.2018.8474120},
booktitle={2018 IEEE 24th International Symposium on On-Line Testing And Robust
System Design (IOLTS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Vafaei,
Arash and Navabi, Zainalabedin}, year={2018} }'
chicago: Sadeghi-Kohan, Somayeh, Arash Vafaei, and Zainalabedin Navabi. “Near-Optimal
Node Selection Procedure for Aging Monitor Placement.” In 2018 IEEE 24th International
Symposium on On-Line Testing And Robust System Design (IOLTS). IEEE, 2018.
https://doi.org/10.1109/iolts.2018.8474120.
ieee: 'S. Sadeghi-Kohan, A. Vafaei, and Z. Navabi, “Near-Optimal Node Selection
Procedure for Aging Monitor Placement,” 2018, doi: 10.1109/iolts.2018.8474120.'
mla: Sadeghi-Kohan, Somayeh, et al. “Near-Optimal Node Selection Procedure for Aging
Monitor Placement.” 2018 IEEE 24th International Symposium on On-Line Testing
And Robust System Design (IOLTS), IEEE, 2018, doi:10.1109/iolts.2018.8474120.
short: 'S. Sadeghi-Kohan, A. Vafaei, Z. Navabi, in: 2018 IEEE 24th International
Symposium on On-Line Testing And Robust System Design (IOLTS), IEEE, 2018.'
date_created: 2022-01-19T13:35:37Z
date_updated: 2023-08-02T11:36:15Z
department:
- _id: '48'
doi: 10.1109/iolts.2018.8474120
extern: '1'
language:
- iso: eng
publication: 2018 IEEE 24th International Symposium on On-Line Testing And Robust
System Design (IOLTS)
publication_status: published
publisher: IEEE
status: public
title: Near-Optimal Node Selection Procedure for Aging Monitor Placement
type: conference
user_id: '78614'
year: '2018'
...
---
_id: '12973'
author:
- first_name: Jyotirmoy
full_name: Deshmukh, Jyotirmoy
last_name: Deshmukh
- first_name: Wolfgang
full_name: Kunz, Wolfgang
last_name: Kunz
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Deshmukh J, Kunz W, Wunderlich H-J, Hellebrand S. Special Session on Early
Life Failures. In: 35th IEEE VLSI Test Symposium (VTS’17). Caesars Palace,
Las Vegas, Nevada, USA: IEEE; 2017. doi:10.1109/vts.2017.7928933'
apa: 'Deshmukh, J., Kunz, W., Wunderlich, H.-J., & Hellebrand, S. (2017). Special
Session on Early Life Failures. In 35th IEEE VLSI Test Symposium (VTS’17).
Caesars Palace, Las Vegas, Nevada, USA: IEEE. https://doi.org/10.1109/vts.2017.7928933'
bibtex: '@inproceedings{Deshmukh_Kunz_Wunderlich_Hellebrand_2017, place={Caesars
Palace, Las Vegas, Nevada, USA}, title={Special Session on Early Life Failures},
DOI={10.1109/vts.2017.7928933},
booktitle={35th IEEE VLSI Test Symposium (VTS’17)}, publisher={IEEE}, author={Deshmukh,
Jyotirmoy and Kunz, Wolfgang and Wunderlich, Hans-Joachim and Hellebrand, Sybille},
year={2017} }'
chicago: 'Deshmukh, Jyotirmoy, Wolfgang Kunz, Hans-Joachim Wunderlich, and Sybille
Hellebrand. “Special Session on Early Life Failures.” In 35th IEEE VLSI Test
Symposium (VTS’17). Caesars Palace, Las Vegas, Nevada, USA: IEEE, 2017. https://doi.org/10.1109/vts.2017.7928933.'
ieee: J. Deshmukh, W. Kunz, H.-J. Wunderlich, and S. Hellebrand, “Special Session
on Early Life Failures,” in 35th IEEE VLSI Test Symposium (VTS’17), 2017.
mla: Deshmukh, Jyotirmoy, et al. “Special Session on Early Life Failures.” 35th
IEEE VLSI Test Symposium (VTS’17), IEEE, 2017, doi:10.1109/vts.2017.7928933.
short: 'J. Deshmukh, W. Kunz, H.-J. Wunderlich, S. Hellebrand, in: 35th IEEE VLSI
Test Symposium (VTS’17), IEEE, Caesars Palace, Las Vegas, Nevada, USA, 2017.'
date_created: 2019-08-28T08:37:58Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '48'
doi: 10.1109/vts.2017.7928933
language:
- iso: eng
place: Caesars Palace, Las Vegas, Nevada, USA
publication: 35th IEEE VLSI Test Symposium (VTS'17)
publisher: IEEE
status: public
title: Special Session on Early Life Failures
type: conference
user_id: '209'
year: '2017'
...
---
_id: '13078'
author:
- first_name: Matthias
full_name: Kampmann, Matthias
id: '10935'
last_name: Kampmann
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: Kampmann M, Hellebrand S. X-Tolerante Prüfzellengruppierung Für Den Test
Mit Erhöhter Betriebsfrequenz.; 2017.
apa: Kampmann, M., & Hellebrand, S. (2017). X-tolerante Prüfzellengruppierung
für den Test mit erhöhter Betriebsfrequenz.
bibtex: '@book{Kampmann_Hellebrand_2017, place={29. Workshop “Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen” (TuZ’17), Lübeck, Germany}, title={X-tolerante Prüfzellengruppierung
für den Test mit erhöhter Betriebsfrequenz}, author={Kampmann, Matthias and Hellebrand,
Sybille}, year={2017} }'
chicago: Kampmann, Matthias, and Sybille Hellebrand. X-Tolerante Prüfzellengruppierung
Für Den Test Mit Erhöhter Betriebsfrequenz. 29. Workshop “Testmethoden und
Zuverlässigkeit von Schaltungen und Systemen” (TuZ’17), Lübeck, Germany, 2017.
ieee: M. Kampmann and S. Hellebrand, X-tolerante Prüfzellengruppierung für den
Test mit erhöhter Betriebsfrequenz. 29. Workshop “Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen” (TuZ’17), Lübeck, Germany, 2017.
mla: Kampmann, Matthias, and Sybille Hellebrand. X-Tolerante Prüfzellengruppierung
Für Den Test Mit Erhöhter Betriebsfrequenz. 2017.
short: M. Kampmann, S. Hellebrand, X-Tolerante Prüfzellengruppierung Für Den Test
Mit Erhöhter Betriebsfrequenz, 29. Workshop “Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen” (TuZ’17), Lübeck, Germany, 2017.
date_created: 2019-08-28T12:06:26Z
date_updated: 2022-05-11T16:17:41Z
department:
- _id: '48'
keyword:
- WORKSHOP
language:
- iso: eng
place: 29. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
(TuZ'17), Lübeck, Germany
status: public
title: X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz
type: misc
user_id: '209'
year: '2017'
...
---
_id: '10576'
author:
- first_name: Matthias
full_name: Kampmann, Matthias
id: '10935'
last_name: Kampmann
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Kampmann M, Hellebrand S. Design-for-FAST: Supporting X-tolerant compaction
during Faster-than-at-Speed Test. In: 20th IEEE International Symposium on
Design & Diagnostics of Electronic Circuits & Systems (DDECS’17).
IEEE; 2017. doi:10.1109/ddecs.2017.7934564'
apa: 'Kampmann, M., & Hellebrand, S. (2017). Design-for-FAST: Supporting X-tolerant
compaction during Faster-than-at-Speed Test. 20th IEEE International Symposium
on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17).
https://doi.org/10.1109/ddecs.2017.7934564'
bibtex: '@inproceedings{Kampmann_Hellebrand_2017, title={Design-for-FAST: Supporting
X-tolerant compaction during Faster-than-at-Speed Test}, DOI={10.1109/ddecs.2017.7934564},
booktitle={20th IEEE International Symposium on Design & Diagnostics of Electronic
Circuits & Systems (DDECS’17)}, publisher={IEEE}, author={Kampmann, Matthias
and Hellebrand, Sybille}, year={2017} }'
chicago: 'Kampmann, Matthias, and Sybille Hellebrand. “Design-for-FAST: Supporting
X-Tolerant Compaction during Faster-than-at-Speed Test.” In 20th IEEE International
Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17).
IEEE, 2017. https://doi.org/10.1109/ddecs.2017.7934564.'
ieee: 'M. Kampmann and S. Hellebrand, “Design-for-FAST: Supporting X-tolerant compaction
during Faster-than-at-Speed Test,” 2017, doi: 10.1109/ddecs.2017.7934564.'
mla: 'Kampmann, Matthias, and Sybille Hellebrand. “Design-for-FAST: Supporting X-Tolerant
Compaction during Faster-than-at-Speed Test.” 20th IEEE International Symposium
on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17),
IEEE, 2017, doi:10.1109/ddecs.2017.7934564.'
short: 'M. Kampmann, S. Hellebrand, in: 20th IEEE International Symposium on Design
& Diagnostics of Electronic Circuits & Systems (DDECS’17), IEEE, 2017.'
date_created: 2019-07-05T08:23:56Z
date_updated: 2022-05-11T17:14:51Z
department:
- _id: '48'
doi: 10.1109/ddecs.2017.7934564
language:
- iso: eng
publication: 20th IEEE International Symposium on Design & Diagnostics of Electronic
Circuits & Systems (DDECS'17)
publication_identifier:
isbn:
- '9781538604724'
publication_status: published
publisher: IEEE
status: public
title: 'Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed
Test'
type: conference
user_id: '209'
year: '2017'
...
---
_id: '29462'
abstract:
- lang: eng
text: Time-variant age information of different parts of a system can be used for
system-level performance improvement through high-level task scheduling, thus
extending the life-time of the system. Progressive age information should provide
the age state that the system is in, and the rate that it is being aged at. In
this paper, we propose a structure that monitors certain paths of a circuit and
detects its gradual age growth, and provides the aging rate and aging state of
the circuit. The proposed monitors are placed on a selected set of nodes that
represent a timing bottleneck of the system. These monitors sample expected data
on these nodes, and compare them with the expected values. The timing of sampling
changes as the circuit ages and its delay increases. The timing of sampling will
provide a measure of aging advancement of a circuit. To assess the efficacy of
the proposed method and compare it with other state-of-the-art aging monitors,
we use them on selected nodes of the execution unit of different processors, as
well as some circuits from ITC99 benchmarks. The results reveal that the precision
of our proposed method is between 0.12 (ns) to 0.401 (ns). Its Area and power
overhead are negligible and are about 2.13 and 0.69 percent respectively.
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Mehdi
full_name: Kamal, Mehdi
last_name: Kamal
- first_name: Zainalabedin
full_name: Navabi, Zainalabedin
last_name: Navabi
citation:
ama: Sadeghi-Kohan S, Kamal M, Navabi Z. Self-Adjusting Monitor for Measuring Aging
Rate and Advancement. IEEE Transactions on Emerging Topics in Computing.
2017;8(3):627-641. doi:10.1109/tetc.2017.2771441
apa: Sadeghi-Kohan, S., Kamal, M., & Navabi, Z. (2017). Self-Adjusting Monitor
for Measuring Aging Rate and Advancement. IEEE Transactions on Emerging Topics
in Computing, 8(3), 627–641. https://doi.org/10.1109/tetc.2017.2771441
bibtex: '@article{Sadeghi-Kohan_Kamal_Navabi_2017, title={Self-Adjusting Monitor
for Measuring Aging Rate and Advancement}, volume={8}, DOI={10.1109/tetc.2017.2771441},
number={3}, journal={IEEE Transactions on Emerging Topics in Computing}, publisher={Institute
of Electrical and Electronics Engineers (IEEE)}, author={Sadeghi-Kohan, Somayeh
and Kamal, Mehdi and Navabi, Zainalabedin}, year={2017}, pages={627–641} }'
chicago: 'Sadeghi-Kohan, Somayeh, Mehdi Kamal, and Zainalabedin Navabi. “Self-Adjusting
Monitor for Measuring Aging Rate and Advancement.” IEEE Transactions on Emerging
Topics in Computing 8, no. 3 (2017): 627–41. https://doi.org/10.1109/tetc.2017.2771441.'
ieee: 'S. Sadeghi-Kohan, M. Kamal, and Z. Navabi, “Self-Adjusting Monitor for Measuring
Aging Rate and Advancement,” IEEE Transactions on Emerging Topics in Computing,
vol. 8, no. 3, pp. 627–641, 2017, doi: 10.1109/tetc.2017.2771441.'
mla: Sadeghi-Kohan, Somayeh, et al. “Self-Adjusting Monitor for Measuring Aging
Rate and Advancement.” IEEE Transactions on Emerging Topics in Computing,
vol. 8, no. 3, Institute of Electrical and Electronics Engineers (IEEE), 2017,
pp. 627–41, doi:10.1109/tetc.2017.2771441.
short: S. Sadeghi-Kohan, M. Kamal, Z. Navabi, IEEE Transactions on Emerging Topics
in Computing 8 (2017) 627–641.
date_created: 2022-01-19T13:45:51Z
date_updated: 2023-08-02T11:36:30Z
department:
- _id: '48'
doi: 10.1109/tetc.2017.2771441
extern: '1'
intvolume: ' 8'
issue: '3'
keyword:
- Age advancement
- age monitoring clock
- aging rate
- self-adjusting monitors
language:
- iso: eng
page: 627-641
publication: IEEE Transactions on Emerging Topics in Computing
publication_identifier:
issn:
- 2168-6750
- 2376-4562
publication_status: published
publisher: Institute of Electrical and Electronics Engineers (IEEE)
status: public
title: Self-Adjusting Monitor for Measuring Aging Rate and Advancement
type: journal_article
user_id: '78614'
volume: 8
year: '2017'
...
---
_id: '29463'
abstract:
- lang: eng
text: In this paper we propose to think out of the box and discuss an approach for
universal mitigation of Negative Bias Temperature Instability (NBTI) induced aging
untied from the limitations of its modelling. The cost-effective approach exploits
a simple property of a randomized design, i.e., the equalized signal probability
and switching activity at gate inputs. The techniques considered for structural
design randomization involve both the hardware architecture and embedded software
layers. Ultimately, the proposed approach aims at extending the reliable lifetime
of nanoelectronic systems.
author:
- first_name: Maksim
full_name: Jenihhin, Maksim
last_name: Jenihhin
- first_name: Alexander
full_name: Kamkin, Alexander
last_name: Kamkin
- first_name: Zainalabedin
full_name: Navabi, Zainalabedin
last_name: Navabi
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
citation:
ama: 'Jenihhin M, Kamkin A, Navabi Z, Sadeghi-Kohan S. Universal mitigation of NBTI-induced
aging by design randomization. In: 2016 IEEE East-West Design & Test Symposium
(EWDTS). IEEE; 2017. doi:10.1109/ewdts.2016.7807635'
apa: Jenihhin, M., Kamkin, A., Navabi, Z., & Sadeghi-Kohan, S. (2017). Universal
mitigation of NBTI-induced aging by design randomization. 2016 IEEE East-West
Design & Test Symposium (EWDTS). https://doi.org/10.1109/ewdts.2016.7807635
bibtex: '@inproceedings{Jenihhin_Kamkin_Navabi_Sadeghi-Kohan_2017, title={Universal
mitigation of NBTI-induced aging by design randomization}, DOI={10.1109/ewdts.2016.7807635},
booktitle={2016 IEEE East-West Design & Test Symposium (EWDTS)}, publisher={IEEE},
author={Jenihhin, Maksim and Kamkin, Alexander and Navabi, Zainalabedin and Sadeghi-Kohan,
Somayeh}, year={2017} }'
chicago: Jenihhin, Maksim, Alexander Kamkin, Zainalabedin Navabi, and Somayeh Sadeghi-Kohan.
“Universal Mitigation of NBTI-Induced Aging by Design Randomization.” In 2016
IEEE East-West Design & Test Symposium (EWDTS). IEEE, 2017. https://doi.org/10.1109/ewdts.2016.7807635.
ieee: 'M. Jenihhin, A. Kamkin, Z. Navabi, and S. Sadeghi-Kohan, “Universal mitigation
of NBTI-induced aging by design randomization,” 2017, doi: 10.1109/ewdts.2016.7807635.'
mla: Jenihhin, Maksim, et al. “Universal Mitigation of NBTI-Induced Aging by Design
Randomization.” 2016 IEEE East-West Design & Test Symposium (EWDTS),
IEEE, 2017, doi:10.1109/ewdts.2016.7807635.
short: 'M. Jenihhin, A. Kamkin, Z. Navabi, S. Sadeghi-Kohan, in: 2016 IEEE East-West
Design & Test Symposium (EWDTS), IEEE, 2017.'
date_created: 2022-01-19T13:50:13Z
date_updated: 2023-08-02T11:36:43Z
department:
- _id: '48'
doi: 10.1109/ewdts.2016.7807635
extern: '1'
language:
- iso: eng
publication: 2016 IEEE East-West Design & Test Symposium (EWDTS)
publication_status: published
publisher: IEEE
status: public
title: Universal mitigation of NBTI-induced aging by design randomization
type: conference
user_id: '78614'
year: '2017'
...
---
_id: '12975'
author:
- first_name: Matthias
full_name: Kampmann, Matthias
id: '10935'
last_name: Kampmann
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Kampmann M, Hellebrand S. X Marks the Spot: Scan-Flip-Flop Clustering for
Faster-than-at-Speed Test. In: 25th IEEE Asian Test Symposium (ATS’16).
Hiroshima, Japan: IEEE; 2016:1-6. doi:10.1109/ats.2016.20'
apa: 'Kampmann, M., & Hellebrand, S. (2016). X Marks the Spot: Scan-Flip-Flop
Clustering for Faster-than-at-Speed Test. In 25th IEEE Asian Test Symposium
(ATS’16) (pp. 1–6). Hiroshima, Japan: IEEE. https://doi.org/10.1109/ats.2016.20'
bibtex: '@inproceedings{Kampmann_Hellebrand_2016, place={Hiroshima, Japan}, title={X
Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test}, DOI={10.1109/ats.2016.20}, booktitle={25th
IEEE Asian Test Symposium (ATS’16)}, publisher={IEEE}, author={Kampmann, Matthias
and Hellebrand, Sybille}, year={2016}, pages={1–6} }'
chicago: 'Kampmann, Matthias, and Sybille Hellebrand. “X Marks the Spot: Scan-Flip-Flop
Clustering for Faster-than-at-Speed Test.” In 25th IEEE Asian Test Symposium
(ATS’16), 1–6. Hiroshima, Japan: IEEE, 2016. https://doi.org/10.1109/ats.2016.20.'
ieee: 'M. Kampmann and S. Hellebrand, “X Marks the Spot: Scan-Flip-Flop Clustering
for Faster-than-at-Speed Test,” in 25th IEEE Asian Test Symposium (ATS’16),
2016, pp. 1–6.'
mla: 'Kampmann, Matthias, and Sybille Hellebrand. “X Marks the Spot: Scan-Flip-Flop
Clustering for Faster-than-at-Speed Test.” 25th IEEE Asian Test Symposium (ATS’16),
IEEE, 2016, pp. 1–6, doi:10.1109/ats.2016.20.'
short: 'M. Kampmann, S. Hellebrand, in: 25th IEEE Asian Test Symposium (ATS’16),
IEEE, Hiroshima, Japan, 2016, pp. 1–6.'
date_created: 2019-08-28T08:53:04Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '48'
doi: 10.1109/ats.2016.20
language:
- iso: eng
page: 1-6
place: Hiroshima, Japan
publication: 25th IEEE Asian Test Symposium (ATS'16)
publisher: IEEE
status: public
title: 'X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test'
type: conference
user_id: '209'
year: '2016'
...
---
_id: '12976'
author:
- first_name: Matthias
full_name: Kampmann, Matthias
id: '10935'
last_name: Kampmann
- first_name: Michael
full_name: A. Kochte, Michael
last_name: A. Kochte
- first_name: Eric
full_name: Schneider, Eric
last_name: Schneider
- first_name: Thomas
full_name: Indlekofer, Thomas
last_name: Indlekofer
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: 'Kampmann M, A. Kochte M, Schneider E, Indlekofer T, Hellebrand S, Wunderlich
H-J. Optimized Selection of Frequencies for Faster-Than-at-Speed Test. In: 24th
IEEE Asian Test Symposium (ATS’15). Mumbai, India: IEEE; 2015:109-114. doi:10.1109/ats.2015.26'
apa: 'Kampmann, M., A. Kochte, M., Schneider, E., Indlekofer, T., Hellebrand, S.,
& Wunderlich, H.-J. (2015). Optimized Selection of Frequencies for Faster-Than-at-Speed
Test. In 24th IEEE Asian Test Symposium (ATS’15) (pp. 109–114). Mumbai,
India: IEEE. https://doi.org/10.1109/ats.2015.26'
bibtex: '@inproceedings{Kampmann_A. Kochte_Schneider_Indlekofer_Hellebrand_Wunderlich_2015,
place={Mumbai, India}, title={Optimized Selection of Frequencies for Faster-Than-at-Speed
Test}, DOI={10.1109/ats.2015.26},
booktitle={24th IEEE Asian Test Symposium (ATS’15)}, publisher={IEEE}, author={Kampmann,
Matthias and A. Kochte, Michael and Schneider, Eric and Indlekofer, Thomas and
Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2015}, pages={109–114}
}'
chicago: 'Kampmann, Matthias, Michael A. Kochte, Eric Schneider, Thomas Indlekofer,
Sybille Hellebrand, and Hans-Joachim Wunderlich. “Optimized Selection of Frequencies
for Faster-Than-at-Speed Test.” In 24th IEEE Asian Test Symposium (ATS’15),
109–14. Mumbai, India: IEEE, 2015. https://doi.org/10.1109/ats.2015.26.'
ieee: M. Kampmann, M. A. Kochte, E. Schneider, T. Indlekofer, S. Hellebrand, and
H.-J. Wunderlich, “Optimized Selection of Frequencies for Faster-Than-at-Speed
Test,” in 24th IEEE Asian Test Symposium (ATS’15), 2015, pp. 109–114.
mla: Kampmann, Matthias, et al. “Optimized Selection of Frequencies for Faster-Than-at-Speed
Test.” 24th IEEE Asian Test Symposium (ATS’15), IEEE, 2015, pp. 109–14,
doi:10.1109/ats.2015.26.
short: 'M. Kampmann, M. A. Kochte, E. Schneider, T. Indlekofer, S. Hellebrand, H.-J.
Wunderlich, in: 24th IEEE Asian Test Symposium (ATS’15), IEEE, Mumbai, India,
2015, pp. 109–114.'
date_created: 2019-08-28T09:03:08Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '48'
doi: 10.1109/ats.2015.26
language:
- iso: eng
page: 109-114
place: Mumbai, India
publication: 24th IEEE Asian Test Symposium (ATS'15)
publisher: IEEE
status: public
title: Optimized Selection of Frequencies for Faster-Than-at-Speed Test
type: conference
user_id: '209'
year: '2015'
...