@inproceedings{64838, author = {{Jafarzadeh, Hanieh and Reimer, Jan Dennis and Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{To appear in: 27th IEEE Latin American Test Symposium (LATS2026), March 2026}}, title = {{{Validating Statistical Delay Test Generation under Timing Variations via SAT-Based ATPG}}}, year = {{2026}}, } @inproceedings{59218, author = {{Reimer, Jan Dennis and Holst, Stefan and Sadeghi-Kohan, Somayeh and Wunderlich, Hans-Joachim and Hellebrand, Sybille}}, booktitle = {{IEEE International Symposium of Electronics Design Automation (ISEDA'25), May 2025}}, title = {{{ThorSim: Throughput-Oriented Timing Simulation of FinFET Digital Circuits}}}, year = {{2025}}, } @inproceedings{52744, author = {{Jafarzadeh, Hanieh and Klemme, Florian and Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{European Test Symposium, The Hague, Netherlands, May 20-24, 2024}}, location = {{The Hague, NL}}, pages = {{6}}, publisher = {{IEEE}}, title = {{{Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations}}}, year = {{2024}}, } @inproceedings{52742, author = {{Jafarzadeh, Hanieh and Klemme, Florian and Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024}}, location = {{Maceió}}, pages = {{6}}, publisher = {{IEEE}}, title = {{{Vmin Testing under Variations: Defect vs. Fault Coverage}}}, year = {{2024}}, } @inproceedings{52743, author = {{Hellebrand, Sybille and Sadeghi-Kohan, Somayeh and Wunderlich, Hans-Joachim}}, booktitle = {{International Symposium of EDA (ISEDA), Xi'an, China, May 10-13, 2024}}, location = {{Xi'an, China}}, pages = {{1}}, title = {{{Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle}}}, year = {{2024}}, } @inproceedings{52745, author = {{Wunderlich, Hans-Joachim and Jafarzadeh, Hanieh and Hellebrand, Sybille}}, booktitle = {{International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024}}, location = {{Xi’an, China}}, pages = {{1}}, title = {{{Robust Test of Small Delay Faults under PVT-Variations}}}, year = {{2024}}, } @inproceedings{56014, author = {{Jafarzadeh, Hanieh and Klemme, Florian and Reimer, Jan Dennis and Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{In: IEEE International Test Conference (ITC'24), San Diego, CA, USA, November 2024}}, location = {{San Diego, CA, USA}}, publisher = {{IEEE}}, title = {{{Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing}}}, year = {{2024}}, } @inproceedings{46738, author = {{Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{IEEE Asian Test Symposium (ATS'23), October 2023}}, title = {{{Optimizing the Streaming of Sensor Data with Approximate Communication}}}, year = {{2023}}, } @inproceedings{45830, author = {{Jafarzadeh, Hanieh and Klemme, Florian and Reimer, Jan Dennis and Najafi Haghi, Zahra Paria and Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{IEEE International Test Conference (ITC'23), Anaheim, USA, October 2023}}, location = {{Anaheim, USA}}, publisher = {{IEEE}}, title = {{{Robust Pattern Generation for Small Delay Faults under Process Variations}}}, year = {{2023}}, } @inproceedings{46739, author = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)}}, publisher = {{IEEE}}, title = {{{Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication}}}, doi = {{10.1109/dsn-w58399.2023.00056}}, year = {{2023}}, } @inproceedings{19422, author = {{Sprenger, Alexander and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}}, booktitle = {{IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020}}, title = {{{Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study}}}, year = {{2020}}, } @inproceedings{29200, author = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}}, booktitle = {{38th IEEE VLSI Test Symposium (VTS)}}, publisher = {{IEEE}}, title = {{{Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects}}}, doi = {{10.1109/vts48691.2020.9107591}}, year = {{2020}}, } @inproceedings{19421, author = {{Holst, Stefan and Kampmann, Matthias and Sprenger, Alexander and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim and Weng, Xiaoqing}}, booktitle = {{IEEE International Test Conference (ITC'20), November 2020}}, title = {{{Logic Fault Diagnosis of Hidden Delay Defects}}}, year = {{2020}}, } @inproceedings{12918, abstract = {{The test for small delay faults is of major importance for predicting potential early life failures or wearout problems. Typically, a faster-than-at-speed test (FAST) with sev¬eral different frequencies is used to detect also hidden small delays, which can only be propagated over short paths. But then the outputs at the end of long paths may no longer reach their stable values at the nominal observation time and must be considered as unknown (X-values). Thus, test response compaction for FAST must be extremely flexible to cope with high X-rates, which also vary with the test frequencies. Stochastic compaction introduced by Mitra et al. is controlled by weighted pseudo-random signals allowing for easy adaptation to varying conditions. As demonstrated in previous work, the pseudo-random control can be optimized for high fault efficiency or X-reduction, but a given target in fault efficiency cannot be guaranteed. To close this gap, a hybrid space compactor is introduced in this paper. It is based on the observation that many faults are lost in the compaction of relatively few critical test patterns. For these critical patterns a deterministic compaction phase is added to the test, where the existing compactor structure is re-used, but controlled by specifically determined control vectors. }}, author = {{Maaz, Mohammad Urf and Sprenger, Alexander and Hellebrand, Sybille}}, booktitle = {{50th IEEE International Test Conference (ITC)}}, keywords = {{Faster-than-at-speed test, BIST, DFT, Test response compaction, Stochastic compactor, X-handling}}, location = {{Washington, DC, USA}}, pages = {{1--8}}, publisher = {{IEEE}}, title = {{{A Hybrid Space Compactor for Adaptive X-Handling}}}, year = {{2019}}, } @inproceedings{29460, abstract = {{STT-RAM cells can be considered as an alternative or a hybrid addition to today's SRAM-based cache memories. This is mostly because of their scalability and low leakage power. Moreover, their data storing mechanism (storing the value as resistance) makes them very suitable and applicable for multivalue cache architectures. This feature results in system performance enhancement without any area overhead. On the other hand, the required two-step read/write procedure in multilevel cells results in a non-uniform time access and energy and power overhead on the system. In this paper, we propose a new architecture to dynamically swap data between soft (fast read access) and hard (slow read access) bits in ML cell. Moreover, by reconfiguring cache block size, the proposed architecture can switch between ML and SL modes at runtime. In other words, the swapping method places the hot part of each cache block into soft-bits and the less accessed part into the hard-bits. The SL/ML switching method benefits from the low latency and energy of SL mode and the high storing capacity of ML mode at the same time. Although experimental results show that our proposed method slightly increases the miss rate compared with the conventional ML caches, the performance and energy are improved by 4.9% and 6.5%, respectively. Also, the storage overhead of our method is about 1% that is negligible.}}, author = {{Rezaeizadeh Rookerd, Ramin and Sadeghi-Kohan, Somayeh and Navabi, Zainalabedin}}, booktitle = {{Proceedings of the 2018 on Great Lakes Symposium on VLSI}}, publisher = {{ACM}}, title = {{{Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture}}}, doi = {{10.1145/3194554.3194599}}, year = {{2018}}, } @inproceedings{4575, author = {{Sprenger, Alexander and Hellebrand, Sybille}}, booktitle = {{2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)}}, isbn = {{9781538657546}}, publisher = {{IEEE}}, title = {{{Tuning Stochastic Space Compaction to Faster-than-at-Speed Test}}}, doi = {{10.1109/ddecs.2018.00020}}, year = {{2018}}, } @inproceedings{10575, author = {{Liu, Chang and Schneider, Eric and Kampmann, Matthias and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{27th IEEE Asian Test Symposium (ATS'18)}}, isbn = {{9781538694664}}, title = {{{Extending Aging Monitors for Early Life and Wear-Out Failure Prevention}}}, doi = {{10.1109/ats.2018.00028}}, year = {{2018}}, } @inproceedings{29459, abstract = {{Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. With the emergence of new issues like Electro-migration these problems are getting more crucial. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes that expose smaller overheads to the circuit, using correlation between nodes and the shareability amongst them. To select internal nodes, we first prune some nodes based on some attributes and thus provide a near-optimal solution that can effectively get a number of internal nodes and consider the effects of electro-migration as well. We have applied our proposed scheme to several processors and ITC benchmarks and have looked at its effectiveness for these circuits.}}, author = {{Sadeghi-Kohan, Somayeh and Vafaei, Arash and Navabi, Zainalabedin}}, booktitle = {{2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)}}, publisher = {{IEEE}}, title = {{{Near-Optimal Node Selection Procedure for Aging Monitor Placement}}}, doi = {{10.1109/iolts.2018.8474120}}, year = {{2018}}, } @inproceedings{12973, author = {{Deshmukh, Jyotirmoy and Kunz, Wolfgang and Wunderlich, Hans-Joachim and Hellebrand, Sybille}}, booktitle = {{35th IEEE VLSI Test Symposium (VTS'17)}}, publisher = {{IEEE}}, title = {{{Special Session on Early Life Failures}}}, doi = {{10.1109/vts.2017.7928933}}, year = {{2017}}, } @inproceedings{10576, author = {{Kampmann, Matthias and Hellebrand, Sybille}}, booktitle = {{20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS'17)}}, isbn = {{9781538604724}}, publisher = {{IEEE}}, title = {{{Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test}}}, doi = {{10.1109/ddecs.2017.7934564}}, year = {{2017}}, }