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IEEE; 2023.","bibtex":"@inproceedings{Jafarzadeh_Klemme_Reimer_Najafi Haghi_ Amrouch_Hellebrand_ Wunderlich_2023, place={Anaheim, CA, USA}, title={Robust Pattern Generation for Small Delay Faults under Process Variations}, booktitle={IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023}, publisher={IEEE}, author={Jafarzadeh, Hanieh and Klemme, Florian and Reimer, Jan Dennis and Najafi Haghi, Zahra Paria and  Amrouch, Hussam and Hellebrand, Sybille and  Wunderlich, Hans-Joachim}, year={2023} }","mla":"Jafarzadeh, Hanieh, et al. “Robust Pattern Generation for Small Delay Faults under Process Variations.” <i>IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023</i>, IEEE, 2023."},"place":"Anaheim, CA, USA","date_created":"2023-07-03T08:20:17Z","type":"conference","department":[{"_id":"48"}],"status":"public","title":"Robust Pattern Generation for Small Delay Faults under Process Variations","year":"2023","conference":{"end_date":"2023-10-13","location":"Anaheim, USA","name":"IEEE International Test Conference (ITC'23)","start_date":"2023-10-08"},"author":[{"last_name":"Jafarzadeh","first_name":"Hanieh","full_name":"Jafarzadeh, Hanieh"},{"last_name":"Klemme","first_name":"Florian","full_name":"Klemme, Florian"},{"full_name":"Reimer, Jan Dennis","first_name":"Jan Dennis","last_name":"Reimer","id":"36703"},{"first_name":"Zahra Paria","last_name":"Najafi Haghi","full_name":"Najafi Haghi, Zahra Paria"},{"full_name":" Amrouch, Hussam","first_name":"Hussam","last_name":" Amrouch"},{"id":"209","first_name":"Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","full_name":"Hellebrand, Sybille"},{"first_name":"Hans-Joachim","last_name":" Wunderlich","full_name":" Wunderlich, Hans-Joachim"}],"date_updated":"2024-03-22T17:14:02Z","publication_status":"published","_id":"45830","publisher":"IEEE","language":[{"iso":"eng"}],"user_id":"209"},{"author":[{"full_name":"Sadeghi-Kohan, Somayeh","last_name":"Sadeghi-Kohan","orcid":"https://orcid.org/0000-0001-7246-0610","first_name":"Somayeh","id":"78614"},{"id":"209","full_name":"Hellebrand, Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","first_name":"Sybille"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"}],"status":"public","title":"Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication","year":"2023","publication_status":"published","date_updated":"2023-08-26T10:49:07Z","_id":"46739","language":[{"iso":"eng"}],"publisher":"IEEE","user_id":"78614","doi":"10.1109/dsn-w58399.2023.00056","citation":{"mla":"Sadeghi-Kohan, Somayeh, et al. “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication.” <i>2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)</i>, IEEE, 2023, doi:<a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">10.1109/dsn-w58399.2023.00056</a>.","bibtex":"@inproceedings{Sadeghi-Kohan_Hellebrand_Wunderlich_2023, title={Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication}, DOI={<a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">10.1109/dsn-w58399.2023.00056</a>}, booktitle={2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023} }","ama":"Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. In: <i>2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)</i>. IEEE; 2023. doi:<a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">10.1109/dsn-w58399.2023.00056</a>","ieee":"S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication,” 2023, doi: <a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">10.1109/dsn-w58399.2023.00056</a>.","apa":"Sadeghi-Kohan, S., Hellebrand, S., &#38; Wunderlich, H.-J. (2023). Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. <i>2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)</i>. <a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">https://doi.org/10.1109/dsn-w58399.2023.00056</a>","short":"S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, in: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), IEEE, 2023.","chicago":"Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication.” In <i>2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)</i>. IEEE, 2023. <a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">https://doi.org/10.1109/dsn-w58399.2023.00056</a>."},"publication":"2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)","date_created":"2023-08-26T10:48:31Z","department":[{"_id":"48"}],"type":"conference"},{"date_updated":"2022-02-19T14:16:58Z","publication_status":"published","status":"public","year":"2020","title":"Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study","conference":{"start_date":"2020-10-19","end_date":"2020-10-21"},"author":[{"id":"22707","last_name":"Sprenger","first_name":"Alexander","full_name":"Sprenger, Alexander"},{"last_name":"Sadeghi-Kohan","first_name":"Somayeh","full_name":"Sadeghi-Kohan, Somayeh","id":"78614"},{"first_name":"Jan Dennis","last_name":"Reimer","full_name":"Reimer, Jan Dennis","id":"36703"},{"id":"209","full_name":"Hellebrand, Sybille","first_name":"Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand"}],"user_id":"209","_id":"19422","language":[{"iso":"eng"}],"publication":"IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020","citation":{"ama":"Sprenger A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. In: <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>. ; 2020.","bibtex":"@inproceedings{Sprenger_Sadeghi-Kohan_Reimer_Hellebrand_2020, place={Virtual Conference - Originally Frascati (Rome), Italy}, title={Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study}, booktitle={IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020}, author={Sprenger, Alexander and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}, year={2020} }","mla":"Sprenger, Alexander, et al. “Variation-Aware Test for Logic Interconnects Using Neural Networks - A Case Study.” <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>, 2020.","short":"A. Sprenger, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, Virtual Conference - Originally Frascati (Rome), Italy, 2020.","chicago":"Sprenger, Alexander, Somayeh Sadeghi-Kohan, Jan Dennis Reimer, and Sybille Hellebrand. “Variation-Aware Test for Logic Interconnects Using Neural Networks - A Case Study.” In <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>. Virtual Conference - Originally Frascati (Rome), Italy, 2020.","apa":"Sprenger, A., Sadeghi-Kohan, S., Reimer, J. D., &#38; Hellebrand, S. (2020). Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>.","ieee":"A. Sprenger, S. Sadeghi-Kohan, J. D. Reimer, and S. Hellebrand, “Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study,” 2020."},"type":"conference","department":[{"_id":"48"}],"place":"Virtual Conference - Originally Frascati (Rome), Italy","date_created":"2020-09-15T14:03:02Z"},{"doi":"10.1109/vts48691.2020.9107591","user_id":"209","language":[{"iso":"eng"}],"_id":"29200","publisher":"IEEE","date_updated":"2022-05-11T17:06:38Z","publication_status":"published","title":"Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects","year":"2020","status":"public","author":[{"last_name":"Sadeghi-Kohan","first_name":"Somayeh","full_name":"Sadeghi-Kohan, Somayeh","id":"78614"},{"full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","first_name":"Sybille","last_name":"Hellebrand","id":"209"}],"type":"conference","department":[{"_id":"48"}],"place":"Virtual Conference - Originally San Diego, CA, USA","date_created":"2022-01-10T08:38:34Z","publication":"38th IEEE VLSI Test Symposium (VTS)","citation":{"mla":"Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. “Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects.” <i>38th IEEE VLSI Test Symposium (VTS)</i>, IEEE, 2020, doi:<a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">10.1109/vts48691.2020.9107591</a>.","ama":"Sadeghi-Kohan S, Hellebrand S. Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. In: <i>38th IEEE VLSI Test Symposium (VTS)</i>. IEEE; 2020. doi:<a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">10.1109/vts48691.2020.9107591</a>","bibtex":"@inproceedings{Sadeghi-Kohan_Hellebrand_2020, place={Virtual Conference - Originally San Diego, CA, USA}, title={Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects}, DOI={<a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">10.1109/vts48691.2020.9107591</a>}, booktitle={38th IEEE VLSI Test Symposium (VTS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}, year={2020} }","apa":"Sadeghi-Kohan, S., &#38; Hellebrand, S. (2020). Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. <i>38th IEEE VLSI Test Symposium (VTS)</i>. <a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">https://doi.org/10.1109/vts48691.2020.9107591</a>","ieee":"S. Sadeghi-Kohan and S. Hellebrand, “Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects,” 2020, doi: <a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">10.1109/vts48691.2020.9107591</a>.","short":"S. Sadeghi-Kohan, S. Hellebrand, in: 38th IEEE VLSI Test Symposium (VTS), IEEE, Virtual Conference - Originally San Diego, CA, USA, 2020.","chicago":"Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. “Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects.” In <i>38th IEEE VLSI Test Symposium (VTS)</i>. Virtual Conference - Originally San Diego, CA, USA: IEEE, 2020. <a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">https://doi.org/10.1109/vts48691.2020.9107591</a>."}},{"citation":{"mla":"Holst, Stefan, et al. “Logic Fault Diagnosis of Hidden Delay Defects.” <i>IEEE International Test Conference (ITC’20), November 2020</i>, 2020.","apa":"Holst, S., Kampmann, M., Sprenger, A., Reimer, J. D., Hellebrand, S., Wunderlich, H.-J., &#38; Weng, X. (2020). Logic Fault Diagnosis of Hidden Delay Defects. <i>IEEE International Test Conference (ITC’20), November 2020</i>.","ieee":"S. Holst <i>et al.</i>, “Logic Fault Diagnosis of Hidden Delay Defects,” 2020.","short":"S. Holst, M. Kampmann, A. Sprenger, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, X. Weng, in: IEEE International Test Conference (ITC’20), November 2020, Virtual Conference - Originally Washington, DC, USA, 2020.","ama":"Holst S, Kampmann M, Sprenger A, et al. Logic Fault Diagnosis of Hidden Delay Defects. In: <i>IEEE International Test Conference (ITC’20), November 2020</i>. ; 2020.","chicago":"Holst, Stefan, Matthias Kampmann, Alexander Sprenger, Jan Dennis Reimer, Sybille Hellebrand, Hans-Joachim Wunderlich, and Xiaoqing Weng. “Logic Fault Diagnosis of Hidden Delay Defects.” In <i>IEEE International Test Conference (ITC’20), November 2020</i>. Virtual Conference - Originally Washington, DC, USA, 2020.","bibtex":"@inproceedings{Holst_Kampmann_Sprenger_Reimer_Hellebrand_Wunderlich_Weng_2020, place={Virtual Conference - Originally Washington, DC, USA}, title={Logic Fault Diagnosis of Hidden Delay Defects}, booktitle={IEEE International Test Conference (ITC’20), November 2020}, author={Holst, Stefan and Kampmann, Matthias and Sprenger, Alexander and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim and Weng, Xiaoqing}, year={2020} }"},"publication":"IEEE International Test Conference (ITC'20), November 2020","date_created":"2020-09-15T13:56:08Z","place":"Virtual Conference - Originally Washington, DC, USA","department":[{"_id":"48"}],"type":"conference","author":[{"first_name":"Stefan","last_name":"Holst","full_name":"Holst, Stefan"},{"id":"10935","full_name":"Kampmann, Matthias","first_name":"Matthias","last_name":"Kampmann"},{"full_name":"Sprenger, Alexander","first_name":"Alexander","last_name":"Sprenger","id":"22707"},{"id":"36703","full_name":"Reimer, Jan Dennis","first_name":"Jan Dennis","last_name":"Reimer"},{"full_name":"Hellebrand, Sybille","first_name":"Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","id":"209"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"},{"full_name":"Weng, Xiaoqing","first_name":"Xiaoqing","last_name":"Weng"}],"year":"2020","title":"Logic Fault Diagnosis of Hidden Delay Defects","status":"public","publication_status":"published","date_updated":"2022-05-11T17:08:20Z","language":[{"iso":"eng"}],"_id":"19421","user_id":"209"},{"language":[{"iso":"eng"}],"date_updated":"2022-05-11T17:09:35Z","publication_status":"published","year":"2019","title":"A Hybrid Space Compactor for Adaptive X-Handling","author":[{"full_name":"Maaz, Mohammad Urf","last_name":"Maaz","first_name":"Mohammad Urf","id":"49274"},{"id":"22707","full_name":"Sprenger, Alexander","first_name":"Alexander","last_name":"Sprenger"},{"full_name":"Hellebrand, Sybille","last_name":"Hellebrand","first_name":"Sybille","orcid":"0000-0002-3717-3939","id":"209"}],"keyword":["Faster-than-at-speed test","BIST","DFT","Test response compaction","Stochastic compactor","X-handling"],"type":"conference","department":[{"_id":"48"}],"date_created":"2019-08-14T06:59:04Z","abstract":[{"text":"The test for small delay faults is of major importance for predicting potential early life failures or wearout problems. Typically, a faster-than-at-speed test (FAST) with sev¬eral different frequencies is used to detect also hidden small delays, which can only be propagated over short paths. But then the outputs at the end of long paths may no longer reach their stable values at the nominal observation time and must be considered as unknown (X-values). Thus, test response compaction for FAST must be extremely flexible to cope with high X-rates, which also vary with the test frequencies. Stochastic compaction introduced by Mitra et al. is controlled by weighted pseudo-random signals allowing for easy adaptation to varying conditions. As demonstrated in previous work, the pseudo-random control can be optimized for high fault efficiency or X-reduction, but a given target in fault efficiency cannot be guaranteed. To close this gap, a hybrid space compactor is introduced in this paper. It is based on the observation that many faults are lost in the compaction of relatively few critical test patterns. For these critical patterns a deterministic compaction phase is added to the test, where the existing compactor structure is re-used, but controlled by specifically determined control vectors. ","lang":"eng"}],"publication":"50th IEEE International Test Conference (ITC)","user_id":"209","page":"1-8","_id":"12918","publisher":"IEEE","status":"public","conference":{"start_date":"2019-11-12","name":"50th IEEE International Test Conference (ITC)","location":"Washington, DC, USA","end_date":"2019-11-14"},"place":"Washington, DC, USA","quality_controlled":"1","citation":{"ama":"Maaz MU, Sprenger A, Hellebrand S. A Hybrid Space Compactor for Adaptive X-Handling. In: <i>50th IEEE International Test Conference (ITC)</i>. IEEE; 2019:1-8.","bibtex":"@inproceedings{Maaz_Sprenger_Hellebrand_2019, place={Washington, DC, USA}, title={A Hybrid Space Compactor for Adaptive X-Handling}, booktitle={50th IEEE International Test Conference (ITC)}, publisher={IEEE}, author={Maaz, Mohammad Urf and Sprenger, Alexander and Hellebrand, Sybille}, year={2019}, pages={1–8} }","mla":"Maaz, Mohammad Urf, et al. “A Hybrid Space Compactor for Adaptive X-Handling.” <i>50th IEEE International Test Conference (ITC)</i>, IEEE, 2019, pp. 1–8.","chicago":"Maaz, Mohammad Urf, Alexander Sprenger, and Sybille Hellebrand. “A Hybrid Space Compactor for Adaptive X-Handling.” In <i>50th IEEE International Test Conference (ITC)</i>, 1–8. Washington, DC, USA: IEEE, 2019.","short":"M.U. Maaz, A. Sprenger, S. Hellebrand, in: 50th IEEE International Test Conference (ITC), IEEE, Washington, DC, USA, 2019, pp. 1–8.","apa":"Maaz, M. U., Sprenger, A., &#38; Hellebrand, S. (2019). A Hybrid Space Compactor for Adaptive X-Handling. <i>50th IEEE International Test Conference (ITC)</i>, 1–8.","ieee":"M. U. Maaz, A. Sprenger, and S. Hellebrand, “A Hybrid Space Compactor for Adaptive X-Handling,” in <i>50th IEEE International Test Conference (ITC)</i>, Washington, DC, USA, 2019, pp. 1–8."}},{"date_created":"2022-01-19T13:42:27Z","department":[{"_id":"48"}],"type":"conference","citation":{"ama":"Rezaeizadeh Rookerd R, Sadeghi-Kohan S, Navabi Z. Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture. In: <i>Proceedings of the 2018 on Great Lakes Symposium on VLSI</i>. ACM; 2018. doi:<a href=\"https://doi.org/10.1145/3194554.3194599\">10.1145/3194554.3194599</a>","bibtex":"@inproceedings{Rezaeizadeh Rookerd_Sadeghi-Kohan_Navabi_2018, title={Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture}, DOI={<a href=\"https://doi.org/10.1145/3194554.3194599\">10.1145/3194554.3194599</a>}, booktitle={Proceedings of the 2018 on Great Lakes Symposium on VLSI}, publisher={ACM}, author={Rezaeizadeh Rookerd, Ramin and Sadeghi-Kohan, Somayeh and Navabi, Zainalabedin}, year={2018} }","mla":"Rezaeizadeh Rookerd, Ramin, et al. “Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture.” <i>Proceedings of the 2018 on Great Lakes Symposium on VLSI</i>, ACM, 2018, doi:<a href=\"https://doi.org/10.1145/3194554.3194599\">10.1145/3194554.3194599</a>.","short":"R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, Z. Navabi, in: Proceedings of the 2018 on Great Lakes Symposium on VLSI, ACM, 2018.","chicago":"Rezaeizadeh Rookerd, Ramin, Somayeh Sadeghi-Kohan, and Zainalabedin Navabi. “Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture.” In <i>Proceedings of the 2018 on Great Lakes Symposium on VLSI</i>. ACM, 2018. <a href=\"https://doi.org/10.1145/3194554.3194599\">https://doi.org/10.1145/3194554.3194599</a>.","apa":"Rezaeizadeh Rookerd, R., Sadeghi-Kohan, S., &#38; Navabi, Z. (2018). Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture. <i>Proceedings of the 2018 on Great Lakes Symposium on VLSI</i>. <a href=\"https://doi.org/10.1145/3194554.3194599\">https://doi.org/10.1145/3194554.3194599</a>","ieee":"R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, and Z. Navabi, “Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture,” 2018, doi: <a href=\"https://doi.org/10.1145/3194554.3194599\">10.1145/3194554.3194599</a>."},"publication":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","abstract":[{"text":"STT-RAM cells can be considered as an alternative or a hybrid addition to today's SRAM-based cache memories. This is mostly because of their scalability and low leakage power. Moreover, their data storing mechanism (storing the value as resistance) makes them very suitable and applicable for multivalue cache architectures. This feature results in system performance enhancement without any area overhead. On the other hand, the required two-step read/write procedure in multilevel cells results in a non-uniform time access and energy and power overhead on the system. In this paper, we propose a new architecture to dynamically swap data between soft (fast read access) and hard (slow read access) bits in ML cell. Moreover, by reconfiguring cache block size, the proposed architecture can switch between ML and SL modes at runtime. In other words, the swapping method places the hot part of each cache block into soft-bits and the less accessed part into the hard-bits. The SL/ML switching method benefits from the low latency and energy of SL mode and the high storing capacity of ML mode at the same time. Although experimental results show that our proposed method slightly increases the miss rate compared with the conventional ML caches, the performance and energy are improved by 4.9% and 6.5%, respectively. Also, the storage overhead of our method is about 1% that is negligible.","lang":"eng"}],"publisher":"ACM","_id":"29460","language":[{"iso":"eng"}],"doi":"10.1145/3194554.3194599","user_id":"78614","author":[{"full_name":"Rezaeizadeh Rookerd, Ramin","first_name":"Ramin","last_name":"Rezaeizadeh Rookerd"},{"last_name":"Sadeghi-Kohan","first_name":"Somayeh","full_name":"Sadeghi-Kohan, Somayeh","id":"78614"},{"first_name":"Zainalabedin","last_name":"Navabi","full_name":"Navabi, Zainalabedin"}],"year":"2018","status":"public","title":"Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture","date_updated":"2022-01-19T13:44:17Z","publication_status":"published"},{"user_id":"209","doi":"10.1109/ddecs.2018.00020","_id":"4575","publisher":"IEEE","language":[{"iso":"eng"}],"publication_status":"published","date_updated":"2022-05-11T17:10:37Z","status":"public","year":"2018","title":"Tuning Stochastic Space Compaction to Faster-than-at-Speed Test","publication_identifier":{"isbn":["9781538657546"]},"author":[{"full_name":"Sprenger, Alexander","last_name":"Sprenger","first_name":"Alexander","id":"22707"},{"id":"209","full_name":"Hellebrand, Sybille","last_name":"Hellebrand","first_name":"Sybille","orcid":"0000-0002-3717-3939"}],"type":"conference","department":[{"_id":"48"}],"date_created":"2018-10-02T12:18:46Z","place":"Budapest, Hungary","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"publication":"2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","citation":{"mla":"Sprenger, Alexander, and Sybille Hellebrand. “Tuning Stochastic Space Compaction to Faster-than-at-Speed Test.” <i>2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &#38; Systems (DDECS)</i>, IEEE, 2018, doi:<a href=\"https://doi.org/10.1109/ddecs.2018.00020\">10.1109/ddecs.2018.00020</a>.","bibtex":"@inproceedings{Sprenger_Hellebrand_2018, place={Budapest, Hungary}, title={Tuning Stochastic Space Compaction to Faster-than-at-Speed Test}, DOI={<a href=\"https://doi.org/10.1109/ddecs.2018.00020\">10.1109/ddecs.2018.00020</a>}, booktitle={2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &#38; Systems (DDECS)}, publisher={IEEE}, author={Sprenger, Alexander and Hellebrand, Sybille}, year={2018} }","ama":"Sprenger A, Hellebrand S. Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. In: <i>2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &#38; Systems (DDECS)</i>. IEEE; 2018. doi:<a href=\"https://doi.org/10.1109/ddecs.2018.00020\">10.1109/ddecs.2018.00020</a>","ieee":"A. Sprenger and S. Hellebrand, “Tuning Stochastic Space Compaction to Faster-than-at-Speed Test,” 2018, doi: <a href=\"https://doi.org/10.1109/ddecs.2018.00020\">10.1109/ddecs.2018.00020</a>.","apa":"Sprenger, A., &#38; Hellebrand, S. (2018). Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. <i>2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &#38; Systems (DDECS)</i>. <a href=\"https://doi.org/10.1109/ddecs.2018.00020\">https://doi.org/10.1109/ddecs.2018.00020</a>","chicago":"Sprenger, Alexander, and Sybille Hellebrand. “Tuning Stochastic Space Compaction to Faster-than-at-Speed Test.” In <i>2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &#38; Systems (DDECS)</i>. Budapest, Hungary: IEEE, 2018. <a href=\"https://doi.org/10.1109/ddecs.2018.00020\">https://doi.org/10.1109/ddecs.2018.00020</a>.","short":"A. Sprenger, S. Hellebrand, in: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &#38; Systems (DDECS), IEEE, Budapest, Hungary, 2018."}},{"user_id":"209","doi":"10.1109/ats.2018.00028","language":[{"iso":"eng"}],"_id":"10575","publication_status":"published","date_updated":"2022-05-11T17:11:53Z","title":"Extending Aging Monitors for Early Life and Wear-Out Failure Prevention","year":"2018","status":"public","author":[{"full_name":"Liu, Chang","last_name":"Liu","first_name":"Chang"},{"first_name":"Eric","last_name":"Schneider","full_name":"Schneider, Eric"},{"id":"10935","first_name":"Matthias","last_name":"Kampmann","full_name":"Kampmann, Matthias"},{"last_name":"Hellebrand","orcid":"0000-0002-3717-3939","first_name":"Sybille","full_name":"Hellebrand, Sybille","id":"209"},{"full_name":"Wunderlich, Hans-Joachim","first_name":"Hans-Joachim","last_name":"Wunderlich"}],"publication_identifier":{"isbn":["9781538694664"]},"type":"conference","department":[{"_id":"48"}],"date_created":"2019-07-05T08:14:58Z","publication":"27th IEEE Asian Test Symposium (ATS'18)","citation":{"apa":"Liu, C., Schneider, E., Kampmann, M., Hellebrand, S., &#38; Wunderlich, H.-J. (2018). Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. <i>27th IEEE Asian Test Symposium (ATS’18)</i>. <a href=\"https://doi.org/10.1109/ats.2018.00028\">https://doi.org/10.1109/ats.2018.00028</a>","ieee":"C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, and H.-J. Wunderlich, “Extending Aging Monitors for Early Life and Wear-Out Failure Prevention,” 2018, doi: <a href=\"https://doi.org/10.1109/ats.2018.00028\">10.1109/ats.2018.00028</a>.","short":"C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, H.-J. Wunderlich, in: 27th IEEE Asian Test Symposium (ATS’18), 2018.","chicago":"Liu, Chang, Eric Schneider, Matthias Kampmann, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Extending Aging Monitors for Early Life and Wear-Out Failure Prevention.” In <i>27th IEEE Asian Test Symposium (ATS’18)</i>, 2018. <a href=\"https://doi.org/10.1109/ats.2018.00028\">https://doi.org/10.1109/ats.2018.00028</a>.","mla":"Liu, Chang, et al. “Extending Aging Monitors for Early Life and Wear-Out Failure Prevention.” <i>27th IEEE Asian Test Symposium (ATS’18)</i>, 2018, doi:<a href=\"https://doi.org/10.1109/ats.2018.00028\">10.1109/ats.2018.00028</a>.","ama":"Liu C, Schneider E, Kampmann M, Hellebrand S, Wunderlich H-J. Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. In: <i>27th IEEE Asian Test Symposium (ATS’18)</i>. ; 2018. doi:<a href=\"https://doi.org/10.1109/ats.2018.00028\">10.1109/ats.2018.00028</a>","bibtex":"@inproceedings{Liu_Schneider_Kampmann_Hellebrand_Wunderlich_2018, title={Extending Aging Monitors for Early Life and Wear-Out Failure Prevention}, DOI={<a href=\"https://doi.org/10.1109/ats.2018.00028\">10.1109/ats.2018.00028</a>}, booktitle={27th IEEE Asian Test Symposium (ATS’18)}, author={Liu, Chang and Schneider, Eric and Kampmann, Matthias and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2018} }"}},{"publication_status":"published","date_updated":"2023-08-02T11:36:15Z","year":"2018","title":"Near-Optimal Node Selection Procedure for Aging Monitor Placement","status":"public","author":[{"id":"78614","full_name":"Sadeghi-Kohan, Somayeh","first_name":"Somayeh","last_name":"Sadeghi-Kohan","orcid":"https://orcid.org/0000-0001-7246-0610"},{"full_name":"Vafaei, Arash","last_name":"Vafaei","first_name":"Arash"},{"full_name":"Navabi, Zainalabedin","first_name":"Zainalabedin","last_name":"Navabi"}],"user_id":"78614","doi":"10.1109/iolts.2018.8474120","_id":"29459","publisher":"IEEE","language":[{"iso":"eng"}],"extern":"1","abstract":[{"lang":"eng","text":"Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. With the emergence of new issues like Electro-migration these problems are getting more crucial. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes that expose smaller overheads to the circuit, using correlation between nodes and the shareability amongst them. To select internal nodes, we first prune some nodes based on some attributes and thus provide a near-optimal solution that can effectively get a number of internal nodes and consider the effects of electro-migration as well. We have applied our proposed scheme to several processors and ITC benchmarks and have looked at its effectiveness for these circuits."}],"publication":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","citation":{"ieee":"S. Sadeghi-Kohan, A. Vafaei, and Z. Navabi, “Near-Optimal Node Selection Procedure for Aging Monitor Placement,” 2018, doi: <a href=\"https://doi.org/10.1109/iolts.2018.8474120\">10.1109/iolts.2018.8474120</a>.","apa":"Sadeghi-Kohan, S., Vafaei, A., &#38; Navabi, Z. (2018). Near-Optimal Node Selection Procedure for Aging Monitor Placement. <i>2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)</i>. <a href=\"https://doi.org/10.1109/iolts.2018.8474120\">https://doi.org/10.1109/iolts.2018.8474120</a>","short":"S. Sadeghi-Kohan, A. Vafaei, Z. Navabi, in: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), IEEE, 2018.","chicago":"Sadeghi-Kohan, Somayeh, Arash Vafaei, and Zainalabedin Navabi. “Near-Optimal Node Selection Procedure for Aging Monitor Placement.” In <i>2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)</i>. IEEE, 2018. <a href=\"https://doi.org/10.1109/iolts.2018.8474120\">https://doi.org/10.1109/iolts.2018.8474120</a>.","mla":"Sadeghi-Kohan, Somayeh, et al. “Near-Optimal Node Selection Procedure for Aging Monitor Placement.” <i>2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)</i>, IEEE, 2018, doi:<a href=\"https://doi.org/10.1109/iolts.2018.8474120\">10.1109/iolts.2018.8474120</a>.","bibtex":"@inproceedings{Sadeghi-Kohan_Vafaei_Navabi_2018, title={Near-Optimal Node Selection Procedure for Aging Monitor Placement}, DOI={<a href=\"https://doi.org/10.1109/iolts.2018.8474120\">10.1109/iolts.2018.8474120</a>}, booktitle={2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Vafaei, Arash and Navabi, Zainalabedin}, year={2018} }","ama":"Sadeghi-Kohan S, Vafaei A, Navabi Z. Near-Optimal Node Selection Procedure for Aging Monitor Placement. In: <i>2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)</i>. IEEE; 2018. doi:<a href=\"https://doi.org/10.1109/iolts.2018.8474120\">10.1109/iolts.2018.8474120</a>"},"type":"conference","department":[{"_id":"48"}],"date_created":"2022-01-19T13:35:37Z"},{"date_updated":"2022-01-06T06:51:27Z","author":[{"last_name":"Deshmukh","first_name":"Jyotirmoy","full_name":"Deshmukh, Jyotirmoy"},{"full_name":"Kunz, Wolfgang","first_name":"Wolfgang","last_name":"Kunz"},{"last_name":"Wunderlich","first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim"},{"id":"209","full_name":"Hellebrand, Sybille","last_name":"Hellebrand","first_name":"Sybille","orcid":"0000-0002-3717-3939"}],"title":"Special Session on Early Life Failures","year":"2017","status":"public","user_id":"209","doi":"10.1109/vts.2017.7928933","publisher":"IEEE","_id":"12973","language":[{"iso":"eng"}],"citation":{"mla":"Deshmukh, Jyotirmoy, et al. “Special Session on Early Life Failures.” <i>35th IEEE VLSI Test Symposium (VTS’17)</i>, IEEE, 2017, doi:<a href=\"https://doi.org/10.1109/vts.2017.7928933\">10.1109/vts.2017.7928933</a>.","bibtex":"@inproceedings{Deshmukh_Kunz_Wunderlich_Hellebrand_2017, place={Caesars Palace, Las Vegas, Nevada, USA}, title={Special Session on Early Life Failures}, DOI={<a href=\"https://doi.org/10.1109/vts.2017.7928933\">10.1109/vts.2017.7928933</a>}, booktitle={35th IEEE VLSI Test Symposium (VTS’17)}, publisher={IEEE}, author={Deshmukh, Jyotirmoy and Kunz, Wolfgang and Wunderlich, Hans-Joachim and Hellebrand, Sybille}, year={2017} }","ama":"Deshmukh J, Kunz W, Wunderlich H-J, Hellebrand S. Special Session on Early Life Failures. In: <i>35th IEEE VLSI Test Symposium (VTS’17)</i>. Caesars Palace, Las Vegas, Nevada, USA: IEEE; 2017. doi:<a href=\"https://doi.org/10.1109/vts.2017.7928933\">10.1109/vts.2017.7928933</a>","ieee":"J. Deshmukh, W. Kunz, H.-J. Wunderlich, and S. Hellebrand, “Special Session on Early Life Failures,” in <i>35th IEEE VLSI Test Symposium (VTS’17)</i>, 2017.","apa":"Deshmukh, J., Kunz, W., Wunderlich, H.-J., &#38; Hellebrand, S. (2017). Special Session on Early Life Failures. In <i>35th IEEE VLSI Test Symposium (VTS’17)</i>. Caesars Palace, Las Vegas, Nevada, USA: IEEE. <a href=\"https://doi.org/10.1109/vts.2017.7928933\">https://doi.org/10.1109/vts.2017.7928933</a>","short":"J. Deshmukh, W. Kunz, H.-J. Wunderlich, S. Hellebrand, in: 35th IEEE VLSI Test Symposium (VTS’17), IEEE, Caesars Palace, Las Vegas, Nevada, USA, 2017.","chicago":"Deshmukh, Jyotirmoy, Wolfgang Kunz, Hans-Joachim Wunderlich, and Sybille Hellebrand. “Special Session on Early Life Failures.” In <i>35th IEEE VLSI Test Symposium (VTS’17)</i>. Caesars Palace, Las Vegas, Nevada, USA: IEEE, 2017. <a href=\"https://doi.org/10.1109/vts.2017.7928933\">https://doi.org/10.1109/vts.2017.7928933</a>."},"publication":"35th IEEE VLSI Test Symposium (VTS'17)","department":[{"_id":"48"}],"type":"conference","date_created":"2019-08-28T08:37:58Z","place":"Caesars Palace, Las Vegas, Nevada, USA"},{"_id":"10576","publisher":"IEEE","language":[{"iso":"eng"}],"user_id":"209","doi":"10.1109/ddecs.2017.7934564","author":[{"full_name":"Kampmann, Matthias","first_name":"Matthias","last_name":"Kampmann","id":"10935"},{"id":"209","full_name":"Hellebrand, Sybille","first_name":"Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939"}],"publication_identifier":{"isbn":["9781538604724"]},"year":"2017","title":"Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test","status":"public","publication_status":"published","date_updated":"2022-05-11T17:14:51Z","date_created":"2019-07-05T08:23:56Z","department":[{"_id":"48"}],"type":"conference","citation":{"chicago":"Kampmann, Matthias, and Sybille Hellebrand. “Design-for-FAST: Supporting X-Tolerant Compaction during Faster-than-at-Speed Test.” In <i>20th IEEE International Symposium on Design &#38; Diagnostics of Electronic Circuits &#38; Systems (DDECS’17)</i>. IEEE, 2017. <a href=\"https://doi.org/10.1109/ddecs.2017.7934564\">https://doi.org/10.1109/ddecs.2017.7934564</a>.","short":"M. Kampmann, S. Hellebrand, in: 20th IEEE International Symposium on Design &#38; Diagnostics of Electronic Circuits &#38; Systems (DDECS’17), IEEE, 2017.","apa":"Kampmann, M., &#38; Hellebrand, S. (2017). Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. <i>20th IEEE International Symposium on Design &#38; Diagnostics of Electronic Circuits &#38; Systems (DDECS’17)</i>. <a href=\"https://doi.org/10.1109/ddecs.2017.7934564\">https://doi.org/10.1109/ddecs.2017.7934564</a>","ieee":"M. Kampmann and S. Hellebrand, “Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test,” 2017, doi: <a href=\"https://doi.org/10.1109/ddecs.2017.7934564\">10.1109/ddecs.2017.7934564</a>.","ama":"Kampmann M, Hellebrand S. Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. In: <i>20th IEEE International Symposium on Design &#38; Diagnostics of Electronic Circuits &#38; Systems (DDECS’17)</i>. IEEE; 2017. doi:<a href=\"https://doi.org/10.1109/ddecs.2017.7934564\">10.1109/ddecs.2017.7934564</a>","bibtex":"@inproceedings{Kampmann_Hellebrand_2017, title={Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test}, DOI={<a href=\"https://doi.org/10.1109/ddecs.2017.7934564\">10.1109/ddecs.2017.7934564</a>}, booktitle={20th IEEE International Symposium on Design &#38; Diagnostics of Electronic Circuits &#38; Systems (DDECS’17)}, publisher={IEEE}, author={Kampmann, Matthias and Hellebrand, Sybille}, year={2017} }","mla":"Kampmann, Matthias, and Sybille Hellebrand. “Design-for-FAST: Supporting X-Tolerant Compaction during Faster-than-at-Speed Test.” <i>20th IEEE International Symposium on Design &#38; Diagnostics of Electronic Circuits &#38; Systems (DDECS’17)</i>, IEEE, 2017, doi:<a href=\"https://doi.org/10.1109/ddecs.2017.7934564\">10.1109/ddecs.2017.7934564</a>."},"publication":"20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS'17)"}]