---
_id: '64838'
author:
- first_name: Hanieh
full_name: Jafarzadeh, Hanieh
last_name: Jafarzadeh
- first_name: Jan Dennis
full_name: Reimer, Jan Dennis
id: '36703'
last_name: Reimer
- first_name: Hussam
full_name: Amrouch, Hussam
last_name: Amrouch
- first_name: Sybille
full_name: Hellebrand, Sybille
last_name: Hellebrand
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: 'Jafarzadeh H, Reimer JD, Amrouch H, Hellebrand S, Wunderlich H-J. Validating
Statistical Delay Test Generation under Timing Variations via SAT-Based ATPG.
In: To Appear in: 27th IEEE Latin American Test Symposium (LATS2026), March
2026. ; 2026.'
apa: 'Jafarzadeh, H., Reimer, J. D., Amrouch, H., Hellebrand, S., & Wunderlich,
H.-J. (2026). Validating Statistical Delay Test Generation under Timing Variations
via SAT-Based ATPG. To Appear in: 27th IEEE Latin American Test Symposium (LATS2026),
March 2026.'
bibtex: '@inproceedings{Jafarzadeh_Reimer_Amrouch_Hellebrand_Wunderlich_2026, place={Florianopolis,
Brazil}, title={Validating Statistical Delay Test Generation under Timing Variations
via SAT-Based ATPG}, booktitle={To appear in: 27th IEEE Latin American Test Symposium
(LATS2026), March 2026}, author={Jafarzadeh, Hanieh and Reimer, Jan Dennis and
Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2026}
}'
chicago: 'Jafarzadeh, Hanieh, Jan Dennis Reimer, Hussam Amrouch, Sybille Hellebrand,
and Hans-Joachim Wunderlich. “Validating Statistical Delay Test Generation under
Timing Variations via SAT-Based ATPG.” In To Appear in: 27th IEEE Latin American
Test Symposium (LATS2026), March 2026. Florianopolis, Brazil, 2026.'
ieee: H. Jafarzadeh, J. D. Reimer, H. Amrouch, S. Hellebrand, and H.-J. Wunderlich,
“Validating Statistical Delay Test Generation under Timing Variations via SAT-Based
ATPG,” 2026.
mla: 'Jafarzadeh, Hanieh, et al. “Validating Statistical Delay Test Generation under
Timing Variations via SAT-Based ATPG.” To Appear in: 27th IEEE Latin American
Test Symposium (LATS2026), March 2026, 2026.'
short: 'H. Jafarzadeh, J.D. Reimer, H. Amrouch, S. Hellebrand, H.-J. Wunderlich,
in: To Appear in: 27th IEEE Latin American Test Symposium (LATS2026), March 2026,
Florianopolis, Brazil, 2026.'
date_created: 2026-03-04T15:44:27Z
date_updated: 2026-03-04T15:50:59Z
department:
- _id: '48'
language:
- iso: eng
place: Florianopolis, Brazil
publication: 'To appear in: 27th IEEE Latin American Test Symposium (LATS2026), March
2026'
status: public
title: Validating Statistical Delay Test Generation under Timing Variations via SAT-Based
ATPG
type: conference
user_id: '36703'
year: '2026'
...
---
_id: '59218'
author:
- first_name: Jan Dennis
full_name: Reimer, Jan Dennis
id: '36703'
last_name: Reimer
- first_name: Stefan
full_name: Holst, Stefan
last_name: Holst
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
last_name: Sadeghi-Kohan
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
- first_name: Sybille
full_name: Hellebrand, Sybille
last_name: Hellebrand
citation:
ama: 'Reimer JD, Holst S, Sadeghi-Kohan S, Wunderlich H-J, Hellebrand S. ThorSim:
Throughput-Oriented Timing Simulation of FinFET Digital Circuits. In: IEEE
International Symposium of Electronics Design Automation (ISEDA’25), May 2025.
; 2025.'
apa: 'Reimer, J. D., Holst, S., Sadeghi-Kohan, S., Wunderlich, H.-J., & Hellebrand,
S. (2025). ThorSim: Throughput-Oriented Timing Simulation of FinFET Digital Circuits.
IEEE International Symposium of Electronics Design Automation (ISEDA’25), May
2025.'
bibtex: '@inproceedings{Reimer_Holst_Sadeghi-Kohan_Wunderlich_Hellebrand_2025, place={Hong
Kong, China}, title={ThorSim: Throughput-Oriented Timing Simulation of FinFET
Digital Circuits}, booktitle={IEEE International Symposium of Electronics Design
Automation (ISEDA’25), May 2025}, author={Reimer, Jan Dennis and Holst, Stefan
and Sadeghi-Kohan, Somayeh and Wunderlich, Hans-Joachim and Hellebrand, Sybille},
year={2025} }'
chicago: 'Reimer, Jan Dennis, Stefan Holst, Somayeh Sadeghi-Kohan, Hans-Joachim
Wunderlich, and Sybille Hellebrand. “ThorSim: Throughput-Oriented Timing Simulation
of FinFET Digital Circuits.” In IEEE International Symposium of Electronics
Design Automation (ISEDA’25), May 2025. Hong Kong, China, 2025.'
ieee: 'J. D. Reimer, S. Holst, S. Sadeghi-Kohan, H.-J. Wunderlich, and S. Hellebrand,
“ThorSim: Throughput-Oriented Timing Simulation of FinFET Digital Circuits,” 2025.'
mla: 'Reimer, Jan Dennis, et al. “ThorSim: Throughput-Oriented Timing Simulation
of FinFET Digital Circuits.” IEEE International Symposium of Electronics Design
Automation (ISEDA’25), May 2025, 2025.'
short: 'J.D. Reimer, S. Holst, S. Sadeghi-Kohan, H.-J. Wunderlich, S. Hellebrand,
in: IEEE International Symposium of Electronics Design Automation (ISEDA’25),
May 2025, Hong Kong, China, 2025.'
date_created: 2025-03-31T15:57:21Z
date_updated: 2025-11-03T13:30:51Z
department:
- _id: '48'
language:
- iso: eng
place: Hong Kong, China
publication: IEEE International Symposium of Electronics Design Automation (ISEDA'25),
May 2025
status: public
title: 'ThorSim: Throughput-Oriented Timing Simulation of FinFET Digital Circuits'
type: conference
user_id: '36703'
year: '2025'
...
---
_id: '52744'
author:
- first_name: Hanieh
full_name: Jafarzadeh, Hanieh
last_name: Jafarzadeh
- first_name: Florian
full_name: Klemme, Florian
last_name: Klemme
- first_name: Hussam
full_name: Amrouch, Hussam
last_name: Amrouch
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: 'Jafarzadeh H, Klemme F, Amrouch H, Hellebrand S, Wunderlich H-J. Time and
Space Optimized Storage-based BIST under Multiple Voltages and Variations. In:
European Test Symposium, The Hague, Netherlands, May 20-24, 2024. IEEE;
:6.'
apa: Jafarzadeh, H., Klemme, F., Amrouch, H., Hellebrand, S., & Wunderlich,
H.-J. (n.d.). Time and Space Optimized Storage-based BIST under Multiple Voltages
and Variations. European Test Symposium, The Hague, Netherlands, May 20-24,
2024, 6.
bibtex: '@inproceedings{Jafarzadeh_Klemme_Amrouch_Hellebrand_Wunderlich, title={Time
and Space Optimized Storage-based BIST under Multiple Voltages and Variations},
booktitle={European Test Symposium, The Hague, Netherlands, May 20-24, 2024},
publisher={IEEE}, author={Jafarzadeh, Hanieh and Klemme, Florian and Amrouch,
Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, pages={6} }'
chicago: Jafarzadeh, Hanieh, Florian Klemme, Hussam Amrouch, Sybille Hellebrand,
and Hans-Joachim Wunderlich. “Time and Space Optimized Storage-Based BIST under
Multiple Voltages and Variations.” In European Test Symposium, The Hague, Netherlands,
May 20-24, 2024, 6. IEEE, n.d.
ieee: H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, and H.-J. Wunderlich,
“Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations,”
in European Test Symposium, The Hague, Netherlands, May 20-24, 2024, The
Hague, NL, p. 6.
mla: Jafarzadeh, Hanieh, et al. “Time and Space Optimized Storage-Based BIST under
Multiple Voltages and Variations.” European Test Symposium, The Hague, Netherlands,
May 20-24, 2024, IEEE, p. 6.
short: 'H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in:
European Test Symposium, The Hague, Netherlands, May 20-24, 2024, IEEE, n.d.,
p. 6.'
conference:
end_date: 2024-05-24
location: The Hague, NL
name: IEEE European Test Symposium
start_date: 2024-05-20
date_created: 2024-03-22T17:04:25Z
date_updated: 2024-03-22T17:05:29Z
department:
- _id: '48'
language:
- iso: eng
page: '6'
publication: European Test Symposium, The Hague, Netherlands, May 20-24, 2024
publication_status: accepted
publisher: IEEE
quality_controlled: '1'
status: public
title: Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations
type: conference
user_id: '209'
year: '2024'
...
---
_id: '52742'
author:
- first_name: Hanieh
full_name: Jafarzadeh, Hanieh
last_name: Jafarzadeh
- first_name: Florian
full_name: Klemme, Florian
last_name: Klemme
- first_name: Hussam
full_name: Amrouch, Hussam
last_name: Amrouch
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: 'Jafarzadeh H, Klemme F, Amrouch H, Hellebrand S, Wunderlich H-J. Vmin Testing
under Variations: Defect vs. Fault Coverage. In: IEEE Latin American Test Symposium
(LATS), Maceió, Brazil, April 9-12, 2024. IEEE; :6.'
apa: 'Jafarzadeh, H., Klemme, F., Amrouch, H., Hellebrand, S., & Wunderlich,
H.-J. (n.d.). Vmin Testing under Variations: Defect vs. Fault Coverage. IEEE
Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, 6.'
bibtex: '@inproceedings{Jafarzadeh_Klemme_Amrouch_Hellebrand_Wunderlich, title={Vmin
Testing under Variations: Defect vs. Fault Coverage}, booktitle={IEEE Latin American
Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024}, publisher={IEEE}, author={Jafarzadeh,
Hanieh and Klemme, Florian and Amrouch, Hussam and Hellebrand, Sybille and Wunderlich,
Hans-Joachim}, pages={6} }'
chicago: 'Jafarzadeh, Hanieh, Florian Klemme, Hussam Amrouch, Sybille Hellebrand,
and Hans-Joachim Wunderlich. “Vmin Testing under Variations: Defect vs. Fault
Coverage.” In IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April
9-12, 2024, 6. IEEE, n.d.'
ieee: 'H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, and H.-J. Wunderlich,
“Vmin Testing under Variations: Defect vs. Fault Coverage,” in IEEE Latin American
Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, Maceió, p. 6.'
mla: 'Jafarzadeh, Hanieh, et al. “Vmin Testing under Variations: Defect vs. Fault
Coverage.” IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April
9-12, 2024, IEEE, p. 6.'
short: 'H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in:
IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, IEEE,
n.d., p. 6.'
conference:
end_date: 2024-04-12
location: Maceió
name: IEEE Latin American Test Symposium (LATS)
start_date: 2024-04-09
date_created: 2024-03-22T16:49:22Z
date_updated: 2024-03-22T17:06:40Z
department:
- _id: '48'
language:
- iso: eng
page: '6'
publication: IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12,
2024
publication_status: accepted
publisher: IEEE
quality_controlled: '1'
status: public
title: 'Vmin Testing under Variations: Defect vs. Fault Coverage'
type: conference
user_id: '209'
year: '2024'
...
---
_id: '52743'
author:
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: 'Hellebrand S, Sadeghi-Kohan S, Wunderlich H-J. Functional Safety and Reliability
of Interconnects throughout the Silicon Life Cycle. In: International Symposium
of EDA (ISEDA), Xi’an, China, May 10-13, 2024. ; :1.'
apa: Hellebrand, S., Sadeghi-Kohan, S., & Wunderlich, H.-J. (n.d.). Functional
Safety and Reliability of Interconnects throughout the Silicon Life Cycle. International
Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1.
bibtex: '@inproceedings{Hellebrand_Sadeghi-Kohan_Wunderlich, title={Functional Safety
and Reliability of Interconnects throughout the Silicon Life Cycle}, booktitle={International
Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024}, author={Hellebrand,
Sybille and Sadeghi-Kohan, Somayeh and Wunderlich, Hans-Joachim}, pages={1} }'
chicago: Hellebrand, Sybille, Somayeh Sadeghi-Kohan, and Hans-Joachim Wunderlich.
“Functional Safety and Reliability of Interconnects throughout the Silicon Life
Cycle.” In International Symposium of EDA (ISEDA), Xi’an, China, May 10-13,
2024, 1, n.d.
ieee: S. Hellebrand, S. Sadeghi-Kohan, and H.-J. Wunderlich, “Functional Safety
and Reliability of Interconnects throughout the Silicon Life Cycle,” in International
Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, Xi’an, China, p.
1.
mla: Hellebrand, Sybille, et al. “Functional Safety and Reliability of Interconnects
throughout the Silicon Life Cycle.” International Symposium of EDA (ISEDA),
Xi’an, China, May 10-13, 2024, p. 1.
short: 'S. Hellebrand, S. Sadeghi-Kohan, H.-J. Wunderlich, in: International Symposium
of EDA (ISEDA), Xi’an, China, May 10-13, 2024, n.d., p. 1.'
conference:
end_date: 2024-05-13
location: Xi'an, China
name: International Symposium of EDA (ISEDA)
start_date: 2024-05-10
date_created: 2024-03-22T16:57:53Z
date_updated: 2024-03-22T17:06:02Z
department:
- _id: '48'
language:
- iso: eng
page: '1'
publication: International Symposium of EDA (ISEDA), Xi'an, China, May 10-13, 2024
publication_status: accepted
status: public
title: Functional Safety and Reliability of Interconnects throughout the Silicon Life
Cycle
type: conference
user_id: '209'
year: '2024'
...
---
_id: '52745'
author:
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
- first_name: Hanieh
full_name: Jafarzadeh, Hanieh
last_name: Jafarzadeh
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Wunderlich H-J, Jafarzadeh H, Hellebrand S. Robust Test of Small Delay Faults
under PVT-Variations. In: International Symposium of EDA (ISEDA), Xi’an, China,
May 10-13, 2024. ; :1.'
apa: Wunderlich, H.-J., Jafarzadeh, H., & Hellebrand, S. (n.d.). Robust Test
of Small Delay Faults under PVT-Variations. International Symposium of EDA
(ISEDA), Xi’an, China, May 10-13, 2024, 1.
bibtex: '@inproceedings{Wunderlich_Jafarzadeh_Hellebrand, title={Robust Test of
Small Delay Faults under PVT-Variations}, booktitle={International Symposium
of EDA (ISEDA), Xi’an, China, May 10-13, 2024}, author={Wunderlich, Hans-Joachim
and Jafarzadeh, Hanieh and Hellebrand, Sybille}, pages={1} }'
chicago: Wunderlich, Hans-Joachim, Hanieh Jafarzadeh, and Sybille Hellebrand. “Robust
Test of Small Delay Faults under PVT-Variations.” In International Symposium
of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1, n.d.
ieee: H.-J. Wunderlich, H. Jafarzadeh, and S. Hellebrand, “Robust Test of Small
Delay Faults under PVT-Variations,” in International Symposium of EDA (ISEDA),
Xi’an, China, May 10-13, 2024, Xi’an, China, p. 1.
mla: Wunderlich, Hans-Joachim, et al. “Robust Test of Small Delay Faults under
PVT-Variations.” International Symposium of EDA (ISEDA), Xi’an, China, May
10-13, 2024, p. 1.
short: 'H.-J. Wunderlich, H. Jafarzadeh, S. Hellebrand, in: International Symposium
of EDA (ISEDA), Xi’an, China, May 10-13, 2024, n.d., p. 1.'
conference:
end_date: 2024-05-13
location: Xi’an, China
name: International Symposium of EDA (ISEDA)
start_date: 2024-05-10
date_created: 2024-03-22T17:11:03Z
date_updated: 2024-03-22T17:11:16Z
department:
- _id: '48'
language:
- iso: eng
page: '1'
publication: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024
publication_status: accepted
status: public
title: Robust Test of Small Delay Faults under PVT-Variations
type: conference
user_id: '209'
year: '2024'
...
---
_id: '56014'
author:
- first_name: Hanieh
full_name: Jafarzadeh, Hanieh
last_name: Jafarzadeh
- first_name: Florian
full_name: Klemme, Florian
last_name: Klemme
- first_name: Jan Dennis
full_name: Reimer, Jan Dennis
id: '36703'
last_name: Reimer
- first_name: Hussam
full_name: ' Amrouch, Hussam'
last_name: ' Amrouch'
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: 'Jafarzadeh H, Klemme F, Reimer JD, Amrouch H, Hellebrand S, Wunderlich H-J.
Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC)
for Robust Delay Fault Testing. In: In: IEEE International Test Conference
(ITC’24), San Diego, CA, USA, November 2024. IEEE; 2024.'
apa: 'Jafarzadeh, H., Klemme, F., Reimer, J. D., Amrouch, H., Hellebrand, S., &
Wunderlich, H.-J. (2024). Minimizing PVT-Variability by Exploiting the Zero Temperature
Coefficient (ZTC) for Robust Delay Fault Testing. In: IEEE International Test
Conference (ITC’24), San Diego, CA, USA, November 2024. IEEE International
Test Conference (ITC’24), San Diego, CA, USA.'
bibtex: '@inproceedings{Jafarzadeh_Klemme_Reimer_ Amrouch_Hellebrand_Wunderlich_2024,
place={San Diego, CA}, title={Minimizing PVT-Variability by Exploiting the Zero
Temperature Coefficient (ZTC) for Robust Delay Fault Testing}, booktitle={In:
IEEE International Test Conference (ITC’24), San Diego, CA, USA, November 2024},
publisher={IEEE}, author={Jafarzadeh, Hanieh and Klemme, Florian and Reimer, Jan
Dennis and Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim},
year={2024} }'
chicago: 'Jafarzadeh, Hanieh, Florian Klemme, Jan Dennis Reimer, Hussam Amrouch,
Sybille Hellebrand, and Hans-Joachim Wunderlich. “Minimizing PVT-Variability by
Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing.”
In In: IEEE International Test Conference (ITC’24), San Diego, CA, USA, November
2024. San Diego, CA: IEEE, 2024.'
ieee: H. Jafarzadeh, F. Klemme, J. D. Reimer, H. Amrouch, S. Hellebrand, and H.-J.
Wunderlich, “Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient
(ZTC) for Robust Delay Fault Testing,” presented at the IEEE International Test
Conference (ITC’24), San Diego, CA, USA, 2024.
mla: 'Jafarzadeh, Hanieh, et al. “Minimizing PVT-Variability by Exploiting the Zero
Temperature Coefficient (ZTC) for Robust Delay Fault Testing.” In: IEEE International
Test Conference (ITC’24), San Diego, CA, USA, November 2024, IEEE, 2024.'
short: 'H. Jafarzadeh, F. Klemme, J.D. Reimer, H. Amrouch, S. Hellebrand, H.-J.
Wunderlich, in: In: IEEE International Test Conference (ITC’24), San Diego, CA,
USA, November 2024, IEEE, San Diego, CA, 2024.'
conference:
end_date: 2024-11-08
location: San Diego, CA, USA
name: IEEE International Test Conference (ITC'24)
start_date: 2024-11-03
date_created: 2024-09-04T09:25:20Z
date_updated: 2025-03-31T15:57:16Z
department:
- _id: '48'
language:
- iso: eng
place: San Diego, CA
publication: 'In: IEEE International Test Conference (ITC''24), San Diego, CA, USA,
November 2024'
publisher: IEEE
status: public
title: Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC)
for Robust Delay Fault Testing
type: conference
user_id: '36703'
year: '2024'
...
---
_id: '46738'
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Jan Dennis
full_name: Reimer, Jan Dennis
id: '36703'
last_name: Reimer
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: 'Sadeghi-Kohan S, Reimer JD, Hellebrand S, Wunderlich H-J. Optimizing the Streaming
of Sensor Data with Approximate Communication. In: IEEE Asian Test Symposium
(ATS’23), October 2023. ; 2023.'
apa: Sadeghi-Kohan, S., Reimer, J. D., Hellebrand, S., & Wunderlich, H.-J. (2023).
Optimizing the Streaming of Sensor Data with Approximate Communication. IEEE
Asian Test Symposium (ATS’23), October 2023. IEEE Asian Test Symposium (ATS’23).
bibtex: '@inproceedings{Sadeghi-Kohan_Reimer_Hellebrand_Wunderlich_2023, place={Beijing,
China}, title={Optimizing the Streaming of Sensor Data with Approximate Communication},
booktitle={IEEE Asian Test Symposium (ATS’23), October 2023}, author={Sadeghi-Kohan,
Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim},
year={2023} }'
chicago: Sadeghi-Kohan, Somayeh, Jan Dennis Reimer, Sybille Hellebrand, and Hans-Joachim
Wunderlich. “Optimizing the Streaming of Sensor Data with Approximate Communication.”
In IEEE Asian Test Symposium (ATS’23), October 2023. Beijing, China, 2023.
ieee: S. Sadeghi-Kohan, J. D. Reimer, S. Hellebrand, and H.-J. Wunderlich, “Optimizing
the Streaming of Sensor Data with Approximate Communication,” presented at the
IEEE Asian Test Symposium (ATS’23), 2023.
mla: Sadeghi-Kohan, Somayeh, et al. “Optimizing the Streaming of Sensor Data with
Approximate Communication.” IEEE Asian Test Symposium (ATS’23), October 2023,
2023.
short: 'S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, in: IEEE
Asian Test Symposium (ATS’23), October 2023, Beijing, China, 2023.'
conference:
end_date: 2023-10-17
name: IEEE Asian Test Symposium (ATS'23)
start_date: 2023-10-14
date_created: 2023-08-26T08:47:52Z
date_updated: 2024-01-08T08:49:08Z
department:
- _id: '48'
language:
- iso: eng
place: Beijing, China
publication: IEEE Asian Test Symposium (ATS'23), October 2023
status: public
title: Optimizing the Streaming of Sensor Data with Approximate Communication
type: conference
user_id: '36703'
year: '2023'
...
---
_id: '45830'
author:
- first_name: Hanieh
full_name: Jafarzadeh, Hanieh
last_name: Jafarzadeh
- first_name: Florian
full_name: Klemme, Florian
last_name: Klemme
- first_name: Jan Dennis
full_name: Reimer, Jan Dennis
id: '36703'
last_name: Reimer
- first_name: Zahra Paria
full_name: Najafi Haghi, Zahra Paria
last_name: Najafi Haghi
- first_name: Hussam
full_name: ' Amrouch, Hussam'
last_name: ' Amrouch'
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: ' Wunderlich, Hans-Joachim'
last_name: ' Wunderlich'
citation:
ama: 'Jafarzadeh H, Klemme F, Reimer JD, et al. Robust Pattern Generation for Small
Delay Faults under Process Variations. In: IEEE International Test Conference
(ITC’23), Anaheim, USA, October 2023. IEEE; 2023.'
apa: Jafarzadeh, H., Klemme, F., Reimer, J. D., Najafi Haghi, Z. P., Amrouch, H.,
Hellebrand, S., & Wunderlich, H.-J. (2023). Robust Pattern Generation for
Small Delay Faults under Process Variations. IEEE International Test Conference
(ITC’23), Anaheim, USA, October 2023. IEEE International Test Conference (ITC’23),
Anaheim, USA.
bibtex: '@inproceedings{Jafarzadeh_Klemme_Reimer_Najafi Haghi_ Amrouch_Hellebrand_
Wunderlich_2023, place={Anaheim, CA, USA}, title={Robust Pattern Generation for
Small Delay Faults under Process Variations}, booktitle={IEEE International Test
Conference (ITC’23), Anaheim, USA, October 2023}, publisher={IEEE}, author={Jafarzadeh,
Hanieh and Klemme, Florian and Reimer, Jan Dennis and Najafi Haghi, Zahra Paria
and Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023}
}'
chicago: 'Jafarzadeh, Hanieh, Florian Klemme, Jan Dennis Reimer, Zahra Paria Najafi
Haghi, Hussam Amrouch, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Robust
Pattern Generation for Small Delay Faults under Process Variations.” In IEEE
International Test Conference (ITC’23), Anaheim, USA, October 2023. Anaheim,
CA, USA: IEEE, 2023.'
ieee: H. Jafarzadeh et al., “Robust Pattern Generation for Small Delay Faults
under Process Variations,” presented at the IEEE International Test Conference
(ITC’23), Anaheim, USA, 2023.
mla: Jafarzadeh, Hanieh, et al. “Robust Pattern Generation for Small Delay Faults
under Process Variations.” IEEE International Test Conference (ITC’23), Anaheim,
USA, October 2023, IEEE, 2023.
short: 'H. Jafarzadeh, F. Klemme, J.D. Reimer, Z.P. Najafi Haghi, H. Amrouch, S.
Hellebrand, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’23),
Anaheim, USA, October 2023, IEEE, Anaheim, CA, USA, 2023.'
conference:
end_date: 2023-10-13
location: Anaheim, USA
name: IEEE International Test Conference (ITC'23)
start_date: 2023-10-08
date_created: 2023-07-03T08:20:17Z
date_updated: 2024-03-22T17:14:02Z
department:
- _id: '48'
language:
- iso: eng
place: Anaheim, CA, USA
publication: IEEE International Test Conference (ITC'23), Anaheim, USA, October 2023
publication_status: published
publisher: IEEE
status: public
title: Robust Pattern Generation for Small Delay Faults under Process Variations
type: conference
user_id: '209'
year: '2023'
...
---
_id: '46739'
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: 'Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Low Power Streaming of Sensor
Data Using Gray Code-Based Approximate Communication. In: 2023 53rd Annual
IEEE/IFIP International Conference on Dependable Systems and Networks Workshops
(DSN-W). IEEE; 2023. doi:10.1109/dsn-w58399.2023.00056'
apa: Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2023). Low Power
Streaming of Sensor Data Using Gray Code-Based Approximate Communication. 2023
53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks
Workshops (DSN-W). https://doi.org/10.1109/dsn-w58399.2023.00056
bibtex: '@inproceedings{Sadeghi-Kohan_Hellebrand_Wunderlich_2023, title={Low Power
Streaming of Sensor Data Using Gray Code-Based Approximate Communication}, DOI={10.1109/dsn-w58399.2023.00056},
booktitle={2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems
and Networks Workshops (DSN-W)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh
and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023} }'
chicago: Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich.
“Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication.”
In 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems
and Networks Workshops (DSN-W). IEEE, 2023. https://doi.org/10.1109/dsn-w58399.2023.00056.
ieee: 'S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Low Power Streaming
of Sensor Data Using Gray Code-Based Approximate Communication,” 2023, doi: 10.1109/dsn-w58399.2023.00056.'
mla: Sadeghi-Kohan, Somayeh, et al. “Low Power Streaming of Sensor Data Using Gray
Code-Based Approximate Communication.” 2023 53rd Annual IEEE/IFIP International
Conference on Dependable Systems and Networks Workshops (DSN-W), IEEE, 2023,
doi:10.1109/dsn-w58399.2023.00056.
short: 'S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, in: 2023 53rd Annual
IEEE/IFIP International Conference on Dependable Systems and Networks Workshops
(DSN-W), IEEE, 2023.'
date_created: 2023-08-26T10:48:31Z
date_updated: 2023-08-26T10:49:07Z
department:
- _id: '48'
doi: 10.1109/dsn-w58399.2023.00056
language:
- iso: eng
publication: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems
and Networks Workshops (DSN-W)
publication_status: published
publisher: IEEE
status: public
title: Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication
type: conference
user_id: '78614'
year: '2023'
...
---
_id: '19422'
author:
- first_name: Alexander
full_name: Sprenger, Alexander
id: '22707'
last_name: Sprenger
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
- first_name: Jan Dennis
full_name: Reimer, Jan Dennis
id: '36703'
last_name: Reimer
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Sprenger A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Variation-Aware Test
for Logic Interconnects using Neural Networks - A Case Study. In: IEEE International
Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20),
October 2020. ; 2020.'
apa: Sprenger, A., Sadeghi-Kohan, S., Reimer, J. D., & Hellebrand, S. (2020).
Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study.
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology
Systems (DFT’20), October 2020.
bibtex: '@inproceedings{Sprenger_Sadeghi-Kohan_Reimer_Hellebrand_2020, place={Virtual
Conference - Originally Frascati (Rome), Italy}, title={Variation-Aware Test for
Logic Interconnects using Neural Networks - A Case Study}, booktitle={IEEE International
Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20),
October 2020}, author={Sprenger, Alexander and Sadeghi-Kohan, Somayeh and Reimer,
Jan Dennis and Hellebrand, Sybille}, year={2020} }'
chicago: Sprenger, Alexander, Somayeh Sadeghi-Kohan, Jan Dennis Reimer, and Sybille
Hellebrand. “Variation-Aware Test for Logic Interconnects Using Neural Networks
- A Case Study.” In IEEE International Symposium on Defect and Fault Tolerance
in VLSI and Nanotechnology Systems (DFT’20), October 2020. Virtual Conference
- Originally Frascati (Rome), Italy, 2020.
ieee: A. Sprenger, S. Sadeghi-Kohan, J. D. Reimer, and S. Hellebrand, “Variation-Aware
Test for Logic Interconnects using Neural Networks - A Case Study,” 2020.
mla: Sprenger, Alexander, et al. “Variation-Aware Test for Logic Interconnects Using
Neural Networks - A Case Study.” IEEE International Symposium on Defect and
Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020,
2020.
short: 'A. Sprenger, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: IEEE International
Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20),
October 2020, Virtual Conference - Originally Frascati (Rome), Italy, 2020.'
conference:
end_date: 2020-10-21
start_date: 2020-10-19
date_created: 2020-09-15T14:03:02Z
date_updated: 2022-02-19T14:16:58Z
department:
- _id: '48'
language:
- iso: eng
place: Virtual Conference - Originally Frascati (Rome), Italy
publication: IEEE International Symposium on Defect and Fault Tolerance in VLSI and
Nanotechnology Systems (DFT’20), October 2020
publication_status: published
status: public
title: Variation-Aware Test for Logic Interconnects using Neural Networks - A Case
Study
type: conference
user_id: '209'
year: '2020'
...
---
_id: '29200'
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Sadeghi-Kohan S, Hellebrand S. Dynamic Multi-Frequency Test Method for Hidden
Interconnect Defects. In: 38th IEEE VLSI Test Symposium (VTS). IEEE; 2020.
doi:10.1109/vts48691.2020.9107591'
apa: Sadeghi-Kohan, S., & Hellebrand, S. (2020). Dynamic Multi-Frequency Test
Method for Hidden Interconnect Defects. 38th IEEE VLSI Test Symposium (VTS).
https://doi.org/10.1109/vts48691.2020.9107591
bibtex: '@inproceedings{Sadeghi-Kohan_Hellebrand_2020, place={Virtual Conference
- Originally San Diego, CA, USA}, title={Dynamic Multi-Frequency Test Method for
Hidden Interconnect Defects}, DOI={10.1109/vts48691.2020.9107591},
booktitle={38th IEEE VLSI Test Symposium (VTS)}, publisher={IEEE}, author={Sadeghi-Kohan,
Somayeh and Hellebrand, Sybille}, year={2020} }'
chicago: 'Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. “Dynamic Multi-Frequency
Test Method for Hidden Interconnect Defects.” In 38th IEEE VLSI Test Symposium
(VTS). Virtual Conference - Originally San Diego, CA, USA: IEEE, 2020. https://doi.org/10.1109/vts48691.2020.9107591.'
ieee: 'S. Sadeghi-Kohan and S. Hellebrand, “Dynamic Multi-Frequency Test Method
for Hidden Interconnect Defects,” 2020, doi: 10.1109/vts48691.2020.9107591.'
mla: Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. “Dynamic Multi-Frequency Test
Method for Hidden Interconnect Defects.” 38th IEEE VLSI Test Symposium (VTS),
IEEE, 2020, doi:10.1109/vts48691.2020.9107591.
short: 'S. Sadeghi-Kohan, S. Hellebrand, in: 38th IEEE VLSI Test Symposium (VTS),
IEEE, Virtual Conference - Originally San Diego, CA, USA, 2020.'
date_created: 2022-01-10T08:38:34Z
date_updated: 2022-05-11T17:06:38Z
department:
- _id: '48'
doi: 10.1109/vts48691.2020.9107591
language:
- iso: eng
place: Virtual Conference - Originally San Diego, CA, USA
publication: 38th IEEE VLSI Test Symposium (VTS)
publication_status: published
publisher: IEEE
status: public
title: Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects
type: conference
user_id: '209'
year: '2020'
...
---
_id: '19421'
author:
- first_name: Stefan
full_name: Holst, Stefan
last_name: Holst
- first_name: Matthias
full_name: Kampmann, Matthias
id: '10935'
last_name: Kampmann
- first_name: Alexander
full_name: Sprenger, Alexander
id: '22707'
last_name: Sprenger
- first_name: Jan Dennis
full_name: Reimer, Jan Dennis
id: '36703'
last_name: Reimer
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
- first_name: Xiaoqing
full_name: Weng, Xiaoqing
last_name: Weng
citation:
ama: 'Holst S, Kampmann M, Sprenger A, et al. Logic Fault Diagnosis of Hidden Delay
Defects. In: IEEE International Test Conference (ITC’20), November 2020.
; 2020.'
apa: Holst, S., Kampmann, M., Sprenger, A., Reimer, J. D., Hellebrand, S., Wunderlich,
H.-J., & Weng, X. (2020). Logic Fault Diagnosis of Hidden Delay Defects. IEEE
International Test Conference (ITC’20), November 2020.
bibtex: '@inproceedings{Holst_Kampmann_Sprenger_Reimer_Hellebrand_Wunderlich_Weng_2020,
place={Virtual Conference - Originally Washington, DC, USA}, title={Logic Fault
Diagnosis of Hidden Delay Defects}, booktitle={IEEE International Test Conference
(ITC’20), November 2020}, author={Holst, Stefan and Kampmann, Matthias and Sprenger,
Alexander and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim
and Weng, Xiaoqing}, year={2020} }'
chicago: Holst, Stefan, Matthias Kampmann, Alexander Sprenger, Jan Dennis Reimer,
Sybille Hellebrand, Hans-Joachim Wunderlich, and Xiaoqing Weng. “Logic Fault Diagnosis
of Hidden Delay Defects.” In IEEE International Test Conference (ITC’20), November
2020. Virtual Conference - Originally Washington, DC, USA, 2020.
ieee: S. Holst et al., “Logic Fault Diagnosis of Hidden Delay Defects,” 2020.
mla: Holst, Stefan, et al. “Logic Fault Diagnosis of Hidden Delay Defects.” IEEE
International Test Conference (ITC’20), November 2020, 2020.
short: 'S. Holst, M. Kampmann, A. Sprenger, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich,
X. Weng, in: IEEE International Test Conference (ITC’20), November 2020, Virtual
Conference - Originally Washington, DC, USA, 2020.'
date_created: 2020-09-15T13:56:08Z
date_updated: 2022-05-11T17:08:20Z
department:
- _id: '48'
language:
- iso: eng
place: Virtual Conference - Originally Washington, DC, USA
publication: IEEE International Test Conference (ITC'20), November 2020
publication_status: published
status: public
title: Logic Fault Diagnosis of Hidden Delay Defects
type: conference
user_id: '209'
year: '2020'
...
---
_id: '12918'
abstract:
- lang: eng
text: 'The test for small delay faults is of major importance for predicting potential
early life failures or wearout problems. Typically, a faster-than-at-speed test
(FAST) with sev¬eral different frequencies is used to detect also hidden small
delays, which can only be propagated over short paths. But then the outputs at
the end of long paths may no longer reach their stable values at the nominal observation
time and must be considered as unknown (X-values). Thus, test response compaction
for FAST must be extremely flexible to cope with high X-rates, which also vary
with the test frequencies. Stochastic compaction introduced by Mitra et al. is
controlled by weighted pseudo-random signals allowing for easy adaptation to varying
conditions. As demonstrated in previous work, the pseudo-random control can be
optimized for high fault efficiency or X-reduction, but a given target in fault
efficiency cannot be guaranteed. To close this gap, a hybrid space compactor is
introduced in this paper. It is based on the observation that many faults are
lost in the compaction of relatively few critical test patterns. For these critical
patterns a deterministic compaction phase is added to the test, where the existing
compactor structure is re-used, but controlled by specifically determined control
vectors. '
author:
- first_name: Mohammad Urf
full_name: Maaz, Mohammad Urf
id: '49274'
last_name: Maaz
- first_name: Alexander
full_name: Sprenger, Alexander
id: '22707'
last_name: Sprenger
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Maaz MU, Sprenger A, Hellebrand S. A Hybrid Space Compactor for Adaptive X-Handling.
In: 50th IEEE International Test Conference (ITC). IEEE; 2019:1-8.'
apa: Maaz, M. U., Sprenger, A., & Hellebrand, S. (2019). A Hybrid Space Compactor
for Adaptive X-Handling. 50th IEEE International Test Conference (ITC),
1–8.
bibtex: '@inproceedings{Maaz_Sprenger_Hellebrand_2019, place={Washington, DC, USA},
title={A Hybrid Space Compactor for Adaptive X-Handling}, booktitle={50th IEEE
International Test Conference (ITC)}, publisher={IEEE}, author={Maaz, Mohammad
Urf and Sprenger, Alexander and Hellebrand, Sybille}, year={2019}, pages={1–8}
}'
chicago: 'Maaz, Mohammad Urf, Alexander Sprenger, and Sybille Hellebrand. “A Hybrid
Space Compactor for Adaptive X-Handling.” In 50th IEEE International Test Conference
(ITC), 1–8. Washington, DC, USA: IEEE, 2019.'
ieee: M. U. Maaz, A. Sprenger, and S. Hellebrand, “A Hybrid Space Compactor for
Adaptive X-Handling,” in 50th IEEE International Test Conference (ITC),
Washington, DC, USA, 2019, pp. 1–8.
mla: Maaz, Mohammad Urf, et al. “A Hybrid Space Compactor for Adaptive X-Handling.”
50th IEEE International Test Conference (ITC), IEEE, 2019, pp. 1–8.
short: 'M.U. Maaz, A. Sprenger, S. Hellebrand, in: 50th IEEE International Test
Conference (ITC), IEEE, Washington, DC, USA, 2019, pp. 1–8.'
conference:
end_date: 2019-11-14
location: Washington, DC, USA
name: 50th IEEE International Test Conference (ITC)
start_date: 2019-11-12
date_created: 2019-08-14T06:59:04Z
date_updated: 2022-05-11T17:09:35Z
department:
- _id: '48'
keyword:
- Faster-than-at-speed test
- BIST
- DFT
- Test response compaction
- Stochastic compactor
- X-handling
language:
- iso: eng
page: 1-8
place: Washington, DC, USA
publication: 50th IEEE International Test Conference (ITC)
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: A Hybrid Space Compactor for Adaptive X-Handling
type: conference
user_id: '209'
year: '2019'
...
---
_id: '29460'
abstract:
- lang: eng
text: STT-RAM cells can be considered as an alternative or a hybrid addition to
today's SRAM-based cache memories. This is mostly because of their scalability
and low leakage power. Moreover, their data storing mechanism (storing the value
as resistance) makes them very suitable and applicable for multivalue cache architectures.
This feature results in system performance enhancement without any area overhead.
On the other hand, the required two-step read/write procedure in multilevel cells
results in a non-uniform time access and energy and power overhead on the system.
In this paper, we propose a new architecture to dynamically swap data between
soft (fast read access) and hard (slow read access) bits in ML cell. Moreover,
by reconfiguring cache block size, the proposed architecture can switch between
ML and SL modes at runtime. In other words, the swapping method places the hot
part of each cache block into soft-bits and the less accessed part into the hard-bits.
The SL/ML switching method benefits from the low latency and energy of SL mode
and the high storing capacity of ML mode at the same time. Although experimental
results show that our proposed method slightly increases the miss rate compared
with the conventional ML caches, the performance and energy are improved by 4.9%
and 6.5%, respectively. Also, the storage overhead of our method is about 1% that
is negligible.
author:
- first_name: Ramin
full_name: Rezaeizadeh Rookerd, Ramin
last_name: Rezaeizadeh Rookerd
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
- first_name: Zainalabedin
full_name: Navabi, Zainalabedin
last_name: Navabi
citation:
ama: 'Rezaeizadeh Rookerd R, Sadeghi-Kohan S, Navabi Z. Performance and Energy Enhancement
through an Online Single/Multi Level Mode Switching Cache Architecture. In: Proceedings
of the 2018 on Great Lakes Symposium on VLSI. ACM; 2018. doi:10.1145/3194554.3194599'
apa: Rezaeizadeh Rookerd, R., Sadeghi-Kohan, S., & Navabi, Z. (2018). Performance
and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache
Architecture. Proceedings of the 2018 on Great Lakes Symposium on VLSI.
https://doi.org/10.1145/3194554.3194599
bibtex: '@inproceedings{Rezaeizadeh Rookerd_Sadeghi-Kohan_Navabi_2018, title={Performance
and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache
Architecture}, DOI={10.1145/3194554.3194599},
booktitle={Proceedings of the 2018 on Great Lakes Symposium on VLSI}, publisher={ACM},
author={Rezaeizadeh Rookerd, Ramin and Sadeghi-Kohan, Somayeh and Navabi, Zainalabedin},
year={2018} }'
chicago: Rezaeizadeh Rookerd, Ramin, Somayeh Sadeghi-Kohan, and Zainalabedin Navabi.
“Performance and Energy Enhancement through an Online Single/Multi Level Mode
Switching Cache Architecture.” In Proceedings of the 2018 on Great Lakes Symposium
on VLSI. ACM, 2018. https://doi.org/10.1145/3194554.3194599.
ieee: 'R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, and Z. Navabi, “Performance and
Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture,”
2018, doi: 10.1145/3194554.3194599.'
mla: Rezaeizadeh Rookerd, Ramin, et al. “Performance and Energy Enhancement through
an Online Single/Multi Level Mode Switching Cache Architecture.” Proceedings
of the 2018 on Great Lakes Symposium on VLSI, ACM, 2018, doi:10.1145/3194554.3194599.
short: 'R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, Z. Navabi, in: Proceedings of
the 2018 on Great Lakes Symposium on VLSI, ACM, 2018.'
date_created: 2022-01-19T13:42:27Z
date_updated: 2022-01-19T13:44:17Z
department:
- _id: '48'
doi: 10.1145/3194554.3194599
language:
- iso: eng
publication: Proceedings of the 2018 on Great Lakes Symposium on VLSI
publication_status: published
publisher: ACM
status: public
title: Performance and Energy Enhancement through an Online Single/Multi Level Mode
Switching Cache Architecture
type: conference
user_id: '78614'
year: '2018'
...
---
_id: '4575'
author:
- first_name: Alexander
full_name: Sprenger, Alexander
id: '22707'
last_name: Sprenger
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Sprenger A, Hellebrand S. Tuning Stochastic Space Compaction to Faster-than-at-Speed
Test. In: 2018 IEEE 21st International Symposium on Design and Diagnostics
of Electronic Circuits & Systems (DDECS). IEEE; 2018. doi:10.1109/ddecs.2018.00020'
apa: Sprenger, A., & Hellebrand, S. (2018). Tuning Stochastic Space Compaction
to Faster-than-at-Speed Test. 2018 IEEE 21st International Symposium on Design
and Diagnostics of Electronic Circuits & Systems (DDECS). https://doi.org/10.1109/ddecs.2018.00020
bibtex: '@inproceedings{Sprenger_Hellebrand_2018, place={Budapest, Hungary}, title={Tuning
Stochastic Space Compaction to Faster-than-at-Speed Test}, DOI={10.1109/ddecs.2018.00020},
booktitle={2018 IEEE 21st International Symposium on Design and Diagnostics of
Electronic Circuits & Systems (DDECS)}, publisher={IEEE}, author={Sprenger,
Alexander and Hellebrand, Sybille}, year={2018} }'
chicago: 'Sprenger, Alexander, and Sybille Hellebrand. “Tuning Stochastic Space
Compaction to Faster-than-at-Speed Test.” In 2018 IEEE 21st International Symposium
on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Budapest,
Hungary: IEEE, 2018. https://doi.org/10.1109/ddecs.2018.00020.'
ieee: 'A. Sprenger and S. Hellebrand, “Tuning Stochastic Space Compaction to Faster-than-at-Speed
Test,” 2018, doi: 10.1109/ddecs.2018.00020.'
mla: Sprenger, Alexander, and Sybille Hellebrand. “Tuning Stochastic Space Compaction
to Faster-than-at-Speed Test.” 2018 IEEE 21st International Symposium on Design
and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, 2018,
doi:10.1109/ddecs.2018.00020.
short: 'A. Sprenger, S. Hellebrand, in: 2018 IEEE 21st International Symposium on
Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, Budapest,
Hungary, 2018.'
date_created: 2018-10-02T12:18:46Z
date_updated: 2022-05-11T17:10:37Z
department:
- _id: '48'
doi: 10.1109/ddecs.2018.00020
language:
- iso: eng
place: Budapest, Hungary
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic
Circuits & Systems (DDECS)
publication_identifier:
isbn:
- '9781538657546'
publication_status: published
publisher: IEEE
status: public
title: Tuning Stochastic Space Compaction to Faster-than-at-Speed Test
type: conference
user_id: '209'
year: '2018'
...
---
_id: '10575'
author:
- first_name: Chang
full_name: Liu, Chang
last_name: Liu
- first_name: Eric
full_name: Schneider, Eric
last_name: Schneider
- first_name: Matthias
full_name: Kampmann, Matthias
id: '10935'
last_name: Kampmann
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: 'Liu C, Schneider E, Kampmann M, Hellebrand S, Wunderlich H-J. Extending Aging
Monitors for Early Life and Wear-Out Failure Prevention. In: 27th IEEE Asian
Test Symposium (ATS’18). ; 2018. doi:10.1109/ats.2018.00028'
apa: Liu, C., Schneider, E., Kampmann, M., Hellebrand, S., & Wunderlich, H.-J.
(2018). Extending Aging Monitors for Early Life and Wear-Out Failure Prevention.
27th IEEE Asian Test Symposium (ATS’18). https://doi.org/10.1109/ats.2018.00028
bibtex: '@inproceedings{Liu_Schneider_Kampmann_Hellebrand_Wunderlich_2018, title={Extending
Aging Monitors for Early Life and Wear-Out Failure Prevention}, DOI={10.1109/ats.2018.00028},
booktitle={27th IEEE Asian Test Symposium (ATS’18)}, author={Liu, Chang and Schneider,
Eric and Kampmann, Matthias and Hellebrand, Sybille and Wunderlich, Hans-Joachim},
year={2018} }'
chicago: Liu, Chang, Eric Schneider, Matthias Kampmann, Sybille Hellebrand, and
Hans-Joachim Wunderlich. “Extending Aging Monitors for Early Life and Wear-Out
Failure Prevention.” In 27th IEEE Asian Test Symposium (ATS’18), 2018.
https://doi.org/10.1109/ats.2018.00028.
ieee: 'C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, and H.-J. Wunderlich, “Extending
Aging Monitors for Early Life and Wear-Out Failure Prevention,” 2018, doi: 10.1109/ats.2018.00028.'
mla: Liu, Chang, et al. “Extending Aging Monitors for Early Life and Wear-Out Failure
Prevention.” 27th IEEE Asian Test Symposium (ATS’18), 2018, doi:10.1109/ats.2018.00028.
short: 'C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, H.-J. Wunderlich, in:
27th IEEE Asian Test Symposium (ATS’18), 2018.'
date_created: 2019-07-05T08:14:58Z
date_updated: 2022-05-11T17:11:53Z
department:
- _id: '48'
doi: 10.1109/ats.2018.00028
language:
- iso: eng
publication: 27th IEEE Asian Test Symposium (ATS'18)
publication_identifier:
isbn:
- '9781538694664'
publication_status: published
status: public
title: Extending Aging Monitors for Early Life and Wear-Out Failure Prevention
type: conference
user_id: '209'
year: '2018'
...
---
_id: '29459'
abstract:
- lang: eng
text: Transistor and interconnect wearout is accelerated with transistor scaling
resulting in timing variations and consequently reliability challenges in digital
circuits. With the emergence of new issues like Electro-migration these problems
are getting more crucial. Age monitoring methods can be used to predict and deal
with the aging problem. Selecting appropriate locations for placement of aging
monitors is an important issue. In this work we propose a procedure for selection
of appropriate internal nodes that expose smaller overheads to the circuit, using
correlation between nodes and the shareability amongst them. To select internal
nodes, we first prune some nodes based on some attributes and thus provide a near-optimal
solution that can effectively get a number of internal nodes and consider the
effects of electro-migration as well. We have applied our proposed scheme to several
processors and ITC benchmarks and have looked at its effectiveness for these circuits.
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Arash
full_name: Vafaei, Arash
last_name: Vafaei
- first_name: Zainalabedin
full_name: Navabi, Zainalabedin
last_name: Navabi
citation:
ama: 'Sadeghi-Kohan S, Vafaei A, Navabi Z. Near-Optimal Node Selection Procedure
for Aging Monitor Placement. In: 2018 IEEE 24th International Symposium on
On-Line Testing And Robust System Design (IOLTS). IEEE; 2018. doi:10.1109/iolts.2018.8474120'
apa: Sadeghi-Kohan, S., Vafaei, A., & Navabi, Z. (2018). Near-Optimal Node Selection
Procedure for Aging Monitor Placement. 2018 IEEE 24th International Symposium
on On-Line Testing And Robust System Design (IOLTS). https://doi.org/10.1109/iolts.2018.8474120
bibtex: '@inproceedings{Sadeghi-Kohan_Vafaei_Navabi_2018, title={Near-Optimal Node
Selection Procedure for Aging Monitor Placement}, DOI={10.1109/iolts.2018.8474120},
booktitle={2018 IEEE 24th International Symposium on On-Line Testing And Robust
System Design (IOLTS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Vafaei,
Arash and Navabi, Zainalabedin}, year={2018} }'
chicago: Sadeghi-Kohan, Somayeh, Arash Vafaei, and Zainalabedin Navabi. “Near-Optimal
Node Selection Procedure for Aging Monitor Placement.” In 2018 IEEE 24th International
Symposium on On-Line Testing And Robust System Design (IOLTS). IEEE, 2018.
https://doi.org/10.1109/iolts.2018.8474120.
ieee: 'S. Sadeghi-Kohan, A. Vafaei, and Z. Navabi, “Near-Optimal Node Selection
Procedure for Aging Monitor Placement,” 2018, doi: 10.1109/iolts.2018.8474120.'
mla: Sadeghi-Kohan, Somayeh, et al. “Near-Optimal Node Selection Procedure for Aging
Monitor Placement.” 2018 IEEE 24th International Symposium on On-Line Testing
And Robust System Design (IOLTS), IEEE, 2018, doi:10.1109/iolts.2018.8474120.
short: 'S. Sadeghi-Kohan, A. Vafaei, Z. Navabi, in: 2018 IEEE 24th International
Symposium on On-Line Testing And Robust System Design (IOLTS), IEEE, 2018.'
date_created: 2022-01-19T13:35:37Z
date_updated: 2023-08-02T11:36:15Z
department:
- _id: '48'
doi: 10.1109/iolts.2018.8474120
extern: '1'
language:
- iso: eng
publication: 2018 IEEE 24th International Symposium on On-Line Testing And Robust
System Design (IOLTS)
publication_status: published
publisher: IEEE
status: public
title: Near-Optimal Node Selection Procedure for Aging Monitor Placement
type: conference
user_id: '78614'
year: '2018'
...
---
_id: '12973'
author:
- first_name: Jyotirmoy
full_name: Deshmukh, Jyotirmoy
last_name: Deshmukh
- first_name: Wolfgang
full_name: Kunz, Wolfgang
last_name: Kunz
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Deshmukh J, Kunz W, Wunderlich H-J, Hellebrand S. Special Session on Early
Life Failures. In: 35th IEEE VLSI Test Symposium (VTS’17). Caesars Palace,
Las Vegas, Nevada, USA: IEEE; 2017. doi:10.1109/vts.2017.7928933'
apa: 'Deshmukh, J., Kunz, W., Wunderlich, H.-J., & Hellebrand, S. (2017). Special
Session on Early Life Failures. In 35th IEEE VLSI Test Symposium (VTS’17).
Caesars Palace, Las Vegas, Nevada, USA: IEEE. https://doi.org/10.1109/vts.2017.7928933'
bibtex: '@inproceedings{Deshmukh_Kunz_Wunderlich_Hellebrand_2017, place={Caesars
Palace, Las Vegas, Nevada, USA}, title={Special Session on Early Life Failures},
DOI={10.1109/vts.2017.7928933},
booktitle={35th IEEE VLSI Test Symposium (VTS’17)}, publisher={IEEE}, author={Deshmukh,
Jyotirmoy and Kunz, Wolfgang and Wunderlich, Hans-Joachim and Hellebrand, Sybille},
year={2017} }'
chicago: 'Deshmukh, Jyotirmoy, Wolfgang Kunz, Hans-Joachim Wunderlich, and Sybille
Hellebrand. “Special Session on Early Life Failures.” In 35th IEEE VLSI Test
Symposium (VTS’17). Caesars Palace, Las Vegas, Nevada, USA: IEEE, 2017. https://doi.org/10.1109/vts.2017.7928933.'
ieee: J. Deshmukh, W. Kunz, H.-J. Wunderlich, and S. Hellebrand, “Special Session
on Early Life Failures,” in 35th IEEE VLSI Test Symposium (VTS’17), 2017.
mla: Deshmukh, Jyotirmoy, et al. “Special Session on Early Life Failures.” 35th
IEEE VLSI Test Symposium (VTS’17), IEEE, 2017, doi:10.1109/vts.2017.7928933.
short: 'J. Deshmukh, W. Kunz, H.-J. Wunderlich, S. Hellebrand, in: 35th IEEE VLSI
Test Symposium (VTS’17), IEEE, Caesars Palace, Las Vegas, Nevada, USA, 2017.'
date_created: 2019-08-28T08:37:58Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '48'
doi: 10.1109/vts.2017.7928933
language:
- iso: eng
place: Caesars Palace, Las Vegas, Nevada, USA
publication: 35th IEEE VLSI Test Symposium (VTS'17)
publisher: IEEE
status: public
title: Special Session on Early Life Failures
type: conference
user_id: '209'
year: '2017'
...
---
_id: '10576'
author:
- first_name: Matthias
full_name: Kampmann, Matthias
id: '10935'
last_name: Kampmann
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Kampmann M, Hellebrand S. Design-for-FAST: Supporting X-tolerant compaction
during Faster-than-at-Speed Test. In: 20th IEEE International Symposium on
Design & Diagnostics of Electronic Circuits & Systems (DDECS’17).
IEEE; 2017. doi:10.1109/ddecs.2017.7934564'
apa: 'Kampmann, M., & Hellebrand, S. (2017). Design-for-FAST: Supporting X-tolerant
compaction during Faster-than-at-Speed Test. 20th IEEE International Symposium
on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17).
https://doi.org/10.1109/ddecs.2017.7934564'
bibtex: '@inproceedings{Kampmann_Hellebrand_2017, title={Design-for-FAST: Supporting
X-tolerant compaction during Faster-than-at-Speed Test}, DOI={10.1109/ddecs.2017.7934564},
booktitle={20th IEEE International Symposium on Design & Diagnostics of Electronic
Circuits & Systems (DDECS’17)}, publisher={IEEE}, author={Kampmann, Matthias
and Hellebrand, Sybille}, year={2017} }'
chicago: 'Kampmann, Matthias, and Sybille Hellebrand. “Design-for-FAST: Supporting
X-Tolerant Compaction during Faster-than-at-Speed Test.” In 20th IEEE International
Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17).
IEEE, 2017. https://doi.org/10.1109/ddecs.2017.7934564.'
ieee: 'M. Kampmann and S. Hellebrand, “Design-for-FAST: Supporting X-tolerant compaction
during Faster-than-at-Speed Test,” 2017, doi: 10.1109/ddecs.2017.7934564.'
mla: 'Kampmann, Matthias, and Sybille Hellebrand. “Design-for-FAST: Supporting X-Tolerant
Compaction during Faster-than-at-Speed Test.” 20th IEEE International Symposium
on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17),
IEEE, 2017, doi:10.1109/ddecs.2017.7934564.'
short: 'M. Kampmann, S. Hellebrand, in: 20th IEEE International Symposium on Design
& Diagnostics of Electronic Circuits & Systems (DDECS’17), IEEE, 2017.'
date_created: 2019-07-05T08:23:56Z
date_updated: 2022-05-11T17:14:51Z
department:
- _id: '48'
doi: 10.1109/ddecs.2017.7934564
language:
- iso: eng
publication: 20th IEEE International Symposium on Design & Diagnostics of Electronic
Circuits & Systems (DDECS'17)
publication_identifier:
isbn:
- '9781538604724'
publication_status: published
publisher: IEEE
status: public
title: 'Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed
Test'
type: conference
user_id: '209'
year: '2017'
...