[{"conference":{"name":"ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS)","location":"Berlin"},"title":"Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems","author":[{"last_name":"Becker","full_name":"Becker, Markus","first_name":"Markus"},{"first_name":"Christoph","full_name":"Kuznik, Christoph","last_name":"Kuznik"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"}],"place":"Berlin","doi":"10.1109/ICCPS.2014.6843726","abstract":[{"text":"This paper presents an advanced eight levels spanning SystemC based virtual platform methodology and framework - referred to as HeroeS 3 - providing smooth application to platform mapping and continuous co-refinement of a virtual prototype with its physical environment model. For heterogeneity support, various SystemC extensions are combined covering continuous/discrete models of computation and different communication abstractions, such as analog mixed-signal models, abstract RTOS/HAL/middleware models, TLM bus models, and QEMU wrappers. We enable dependability assessment by Fault Effect Modeling (FEM) at the virtual prototype in order to avoid risking physical injury or damage. Also, simulation results are deterministic and can be evaluated interactively or offline. We apply FEM to both the physical environment model and the different abstractions of the virtual prototype. Currently, we focus on sensor failures and application control flow errors.","lang":"eng"}],"citation":{"mla":"Becker, Markus, et al. <i>Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems</i>. IEEE, 2014, doi:<a href=\"https://doi.org/10.1109/ICCPS.2014.6843726\">10.1109/ICCPS.2014.6843726</a>.","bibtex":"@inproceedings{Becker_Kuznik_Müller_2014, place={Berlin}, title={Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems}, DOI={<a href=\"https://doi.org/10.1109/ICCPS.2014.6843726\">10.1109/ICCPS.2014.6843726</a>}, publisher={IEEE}, author={Becker, Markus and Kuznik, Christoph and Müller, Wolfgang}, year={2014} }","short":"M. Becker, C. Kuznik, W. Müller, in: IEEE, Berlin, 2014.","apa":"Becker, M., Kuznik, C., &#38; Müller, W. (2014). <i>Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems</i>. ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS), Berlin. <a href=\"https://doi.org/10.1109/ICCPS.2014.6843726\">https://doi.org/10.1109/ICCPS.2014.6843726</a>","ama":"Becker M, Kuznik C, Müller W. Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems. In: IEEE; 2014. doi:<a href=\"https://doi.org/10.1109/ICCPS.2014.6843726\">10.1109/ICCPS.2014.6843726</a>","chicago":"Becker, Markus, Christoph Kuznik, and Wolfgang Müller. “Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems.” Berlin: IEEE, 2014. <a href=\"https://doi.org/10.1109/ICCPS.2014.6843726\">https://doi.org/10.1109/ICCPS.2014.6843726</a>.","ieee":"M. Becker, C. Kuznik, and W. Müller, “Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems,” presented at the ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS), Berlin, 2014, doi: <a href=\"https://doi.org/10.1109/ICCPS.2014.6843726\">10.1109/ICCPS.2014.6843726</a>."},"user_id":"5786","keyword":["Computational modeling","Finite element analysis","Prototypes","Abstracts","Software","Fault tolerance","Fault tolerant systems"],"department":[{"_id":"58"}],"date_created":"2023-01-16T11:57:08Z","publisher":"IEEE","type":"conference","year":"2014","language":[{"iso":"eng"}],"status":"public","_id":"36918","date_updated":"2023-01-16T11:57:22Z"},{"date_created":"2023-01-16T11:43:50Z","language":[{"iso":"eng"}],"type":"conference","year":"2014","status":"public","_id":"36917","date_updated":"2023-01-16T11:44:06Z","title":"An Assisted Single Source Verification Metric Model Code Generation Methodology","conference":{"name":"Proceedings of the Electronic System Level Synthesis Conference (ESLSyn)"},"author":[{"last_name":"Kuznik","first_name":"Christoph","full_name":"Kuznik, Christoph"},{"id":"16243","last_name":"Müller","first_name":"Wolfgang","full_name":"Müller, Wolfgang"},{"first_name":"Gilles Bertrand","full_name":"Defo, Gilles Bertrand","last_name":"Defo"}],"place":"San Francisco, USA","abstract":[{"text":"The ever-increasing complexity of heterogeneous electronic systems demand for intensified abstraction and automation efforts to improve design, verification and validation productivity, especially in earlier phases of system engineering. Within the verification activity various metrics can be applied to determine functional correctness or the overall progress. Here, a supporting verification methodology defining high-level verification planning down to the actual metric code development is essential. Moreover, an advanced assistance for the designer, such as a tooling infrastructure to automatize and accelerate the metric code implementation, is needed to minimize the influence of errorprone manual coding. In this article we present a single-source verification metric code-generation methodology for improved coverage automation. We determine (i) a suitable metric model for model-based capture of verification metrics as well as (ii) an assisted model-based processing and generation flow of the verification environment and metric skeletons. We apply our method to a SystemC case-study, in doing so, targeting metric code implementation productivity and consistency enhancement.","lang":"eng"}],"citation":{"chicago":"Kuznik, Christoph, Wolfgang Müller, and Gilles Bertrand Defo. “An Assisted Single Source Verification Metric Model Code Generation Methodology.” San Francisco, USA, 2014.","ieee":"C. Kuznik, W. Müller, and G. B. Defo, “An Assisted Single Source Verification Metric Model Code Generation Methodology,” presented at the Proceedings of the Electronic System Level Synthesis Conference (ESLSyn), 2014.","apa":"Kuznik, C., Müller, W., &#38; Defo, G. B. (2014). <i>An Assisted Single Source Verification Metric Model Code Generation Methodology</i>. Proceedings of the Electronic System Level Synthesis Conference (ESLSyn).","ama":"Kuznik C, Müller W, Defo GB. An Assisted Single Source Verification Metric Model Code Generation Methodology. In: ; 2014.","short":"C. Kuznik, W. Müller, G.B. Defo, in: San Francisco, USA, 2014.","mla":"Kuznik, Christoph, et al. <i>An Assisted Single Source Verification Metric Model Code Generation Methodology</i>. 2014.","bibtex":"@inproceedings{Kuznik_Müller_Defo_2014, place={San Francisco, USA}, title={An Assisted Single Source Verification Metric Model Code Generation Methodology}, author={Kuznik, Christoph and Müller, Wolfgang and Defo, Gilles Bertrand}, year={2014} }"},"keyword":["System Design","Verification"],"user_id":"5786","department":[{"_id":"58"}]},{"abstract":[{"text":"Zur Sicherstellung hoher Zuverlässigkeits- und Fehlertoleranzwerte von Schaltungen und ganzen Systemen finden vermehrt Test- und Verifikationsmethoden Anwendung die einen virtuellen Prototypen (VP) des Systems bereits frühzeitig im Entwurfsablauf einem Stresstest unterziehen. Hierbei werden speziell für die Domäne relevante Fehlerinjektoren verwendet (Digital, Mixed-Signal, Mechanik) die anhand von Fehlermodellen geeignete Testfälle erzeugen und in das System über Stimuli bzw. direkt injizieren. Jede effektive Anwendung einer Methode bedingt jedoch auch das Vorhandensein einer zugrundeliegenden Methodik. In diesem Beitrag wird die System Verification Methodology (SVM) vorgestellt werden, eine universell einsetzbare und erweiterbare Infrastruktur zur Beschreibung von Testumgebungen auf Basis der SystemC Sprache und Simulationskernels.","lang":"eng"}],"author":[{"first_name":"Christoph","full_name":"Kuznik, Christoph","last_name":"Kuznik"},{"full_name":"Müller, Wolfgang","first_name":"Wolfgang","last_name":"Müller","id":"16243"}],"title":"Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM","department":[{"_id":"58"}],"user_id":"5786","citation":{"ieee":"C. Kuznik and W. Müller, “Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM,” 2014.","chicago":"Kuznik, Christoph, and Wolfgang Müller. “Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM.” In <i>26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen</i>, 2014.","apa":"Kuznik, C., &#38; Müller, W. (2014). Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM. <i>26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen</i>.","ama":"Kuznik C, Müller W. Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM. In: <i>26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen</i>. ; 2014.","short":"C. Kuznik, W. Müller, in: 26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, 2014.","bibtex":"@inproceedings{Kuznik_Müller_2014, title={Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM}, booktitle={26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen}, author={Kuznik, Christoph and Müller, Wolfgang}, year={2014} }","mla":"Kuznik, Christoph, and Wolfgang Müller. “Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM.” <i>26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen</i>, 2014."},"status":"public","year":"2014","type":"conference","language":[{"iso":"ger"}],"publication":"26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen","date_created":"2021-09-30T10:26:58Z","date_updated":"2023-01-16T11:46:54Z","_id":"25166"},{"user_id":"5786","citation":{"ama":"Kuznik C, Defo BG, Müller W. Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung. In: <i>17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) </i>. ; 2014.","apa":"Kuznik, C., Defo, B. G., &#38; Müller, W. (2014). Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung. <i>17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) </i>.","ieee":"C. Kuznik, B. G. Defo, and W. Müller, “Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung,” 2014.","chicago":"Kuznik, Christoph, Bertrand Gilles Defo, and Wolfgang Müller. “Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung.” In <i>17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) </i>, 2014.","bibtex":"@inproceedings{Kuznik_Defo_Müller_2014, title={Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung}, booktitle={17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) }, author={Kuznik, Christoph and Defo, Bertrand Gilles and Müller, Wolfgang}, year={2014} }","mla":"Kuznik, Christoph, et al. “Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung.” <i>17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) </i>, 2014.","short":"C. Kuznik, B.G. Defo, W. Müller, in: 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) , 2014."},"department":[{"_id":"58"}],"author":[{"first_name":"Christoph","full_name":"Kuznik, Christoph","last_name":"Kuznik"},{"full_name":"Defo, Bertrand Gilles","first_name":"Bertrand Gilles","last_name":"Defo"},{"id":"16243","last_name":"Müller","full_name":"Müller, Wolfgang","first_name":"Wolfgang"}],"title":"Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung","_id":"25163","date_updated":"2023-01-16T11:45:51Z","publication":"17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) ","date_created":"2021-09-30T10:11:13Z","status":"public","year":"2014","type":"conference","language":[{"iso":"ger"}]},{"publication":"Electronic System Level Synthesis Conference (ESLSyn)","date_created":"2021-09-30T08:05:38Z","year":"2014","type":"journal_article","language":[{"iso":"eng"}],"status":"public","_id":"25151","date_updated":"2023-01-16T11:44:46Z","title":"An Assisted Single Source Verification Metric Model Code Generation Methodology","author":[{"full_name":"Kuznik, Christoph","first_name":"Christoph","last_name":"Kuznik"},{"last_name":"Defo","first_name":"Bertrand Gilles","full_name":"Defo, Bertrand Gilles"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","last_name":"Müller","id":"16243"}],"citation":{"ama":"Kuznik C, Defo BG, Müller W. An Assisted Single Source Verification Metric Model Code Generation Methodology. <i>Electronic System Level Synthesis Conference (ESLSyn)</i>. Published online 2014.","apa":"Kuznik, C., Defo, B. G., &#38; Müller, W. (2014). An Assisted Single Source Verification Metric Model Code Generation Methodology. <i>Electronic System Level Synthesis Conference (ESLSyn)</i>.","chicago":"Kuznik, Christoph, Bertrand Gilles Defo, and Wolfgang Müller. “An Assisted Single Source Verification Metric Model Code Generation Methodology.” <i>Electronic System Level Synthesis Conference (ESLSyn)</i>, 2014.","ieee":"C. Kuznik, B. G. Defo, and W. Müller, “An Assisted Single Source Verification Metric Model Code Generation Methodology,” <i>Electronic System Level Synthesis Conference (ESLSyn)</i>, 2014.","mla":"Kuznik, Christoph, et al. “An Assisted Single Source Verification Metric Model Code Generation Methodology.” <i>Electronic System Level Synthesis Conference (ESLSyn)</i>, 2014.","bibtex":"@article{Kuznik_Defo_Müller_2014, title={An Assisted Single Source Verification Metric Model Code Generation Methodology}, journal={Electronic System Level Synthesis Conference (ESLSyn)}, author={Kuznik, Christoph and Defo, Bertrand Gilles and Müller, Wolfgang}, year={2014} }","short":"C. Kuznik, B.G. Defo, W. Müller, Electronic System Level Synthesis Conference (ESLSyn) (2014)."},"user_id":"5786","department":[{"_id":"58"}]},{"date_created":"2021-09-14T07:06:58Z","related_material":{"link":[{"url":"https://ieeexplore.ieee.org/document/6648461","relation":"confirmation"}]},"publication":"IEEE JOURNAL OF SOLID-STATE CIRCUITS","status":"public","language":[{"iso":"eng"}],"year":"2014","type":"journal_article","publication_identifier":{"eissn":["1558-173X"]},"volume":"Vol.49","page":"452-470","_id":"24310","issue":"No.2","date_updated":"2023-01-25T11:03:36Z","author":[{"full_name":"Awny, Ahmed","first_name":"Ahmed","last_name":"Awny"},{"first_name":"Lothar","full_name":"Möller, Lothar","last_name":"Möller"},{"last_name":"Junio","full_name":"Junio, Josef","first_name":"Josef"},{"last_name":"Scheytt","id":"37144","first_name":"Christoph","full_name":"Scheytt, Christoph","orcid":"https://orcid.org/0000-0002-5950-6618"},{"first_name":"Andreas","full_name":"Thiede, Andreas","id":"538","last_name":"Thiede"}],"title":"Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer","abstract":[{"text":"A millimeter wave frequency mixed-signal design of a 1-tap half-rate look-ahead decision feedback equalizer for 80 Gb/s short-reach optical communication systems is presented. On-wafer tests are developed to determine the maximum operating bit rate of the equalizer. Results are also presented for intersymbol interference mitigation at 80 Gb/s for a 20 GHz bandwidth-limited channel. Further improvements on the architecture of the 80 Gb/s equalizer are discussed and used in the design and on-wafer measurement of a 110 Gb/s equalizer. The equalizers are designed in a 0.13 μm SiGe:C BiCMOS technology. The 80 and 110 Gb/s versions dissipate 4 and 5.75 W, respectively and occupy 2 and 2.56 mm 2 , respectively.","lang":"eng"}],"doi":"10.1109/JSSC.2013.2285385","user_id":"158","citation":{"apa":"Awny, A., Möller, L., Junio, J., Scheytt, C., &#38; Thiede, A. (2014). Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer. <i>IEEE JOURNAL OF SOLID-STATE CIRCUITS</i>, <i>Vol.49</i>(No.2), 452–470. <a href=\"https://doi.org/10.1109/JSSC.2013.2285385\">https://doi.org/10.1109/JSSC.2013.2285385</a>","ama":"Awny A, Möller L, Junio J, Scheytt C, Thiede A. Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer. <i>IEEE JOURNAL OF SOLID-STATE CIRCUITS</i>. 2014;Vol.49(No.2):452-470. doi:<a href=\"https://doi.org/10.1109/JSSC.2013.2285385\">10.1109/JSSC.2013.2285385</a>","ieee":"A. Awny, L. Möller, J. Junio, C. Scheytt, and A. Thiede, “Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer,” <i>IEEE JOURNAL OF SOLID-STATE CIRCUITS</i>, vol. Vol.49, no. No.2, pp. 452–470, 2014, doi: <a href=\"https://doi.org/10.1109/JSSC.2013.2285385\">10.1109/JSSC.2013.2285385</a>.","chicago":"Awny, Ahmed, Lothar Möller, Josef Junio, Christoph Scheytt, and Andreas Thiede. “Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer.” <i>IEEE JOURNAL OF SOLID-STATE CIRCUITS</i> Vol.49, no. No.2 (2014): 452–70. <a href=\"https://doi.org/10.1109/JSSC.2013.2285385\">https://doi.org/10.1109/JSSC.2013.2285385</a>.","bibtex":"@article{Awny_Möller_Junio_Scheytt_Thiede_2014, title={Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer}, volume={Vol.49}, DOI={<a href=\"https://doi.org/10.1109/JSSC.2013.2285385\">10.1109/JSSC.2013.2285385</a>}, number={No.2}, journal={IEEE JOURNAL OF SOLID-STATE CIRCUITS}, author={Awny, Ahmed and Möller, Lothar and Junio, Josef and Scheytt, Christoph and Thiede, Andreas}, year={2014}, pages={452–470} }","mla":"Awny, Ahmed, et al. “Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer.” <i>IEEE JOURNAL OF SOLID-STATE CIRCUITS</i>, vol. Vol.49, no. No.2, 2014, pp. 452–70, doi:<a href=\"https://doi.org/10.1109/JSSC.2013.2285385\">10.1109/JSSC.2013.2285385</a>.","short":"A. Awny, L. Möller, J. Junio, C. Scheytt, A. Thiede, IEEE JOURNAL OF SOLID-STATE CIRCUITS Vol.49 (2014) 452–470."},"department":[{"_id":"58"},{"_id":"51"}]},{"department":[{"_id":"58"}],"keyword":["System Design","Verification"],"user_id":"15931","citation":{"chicago":"Koppelmann, Bastian, Bernd Messidat, Markus Becker, Wolfgang Müller, and J. Christoph Scheytt. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” In <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>. München, 2014.","ieee":"B. Koppelmann, B. Messidat, M. Becker, W. Müller, and J. C. Scheytt, “Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” 2014.","apa":"Koppelmann, B., Messidat, B., Becker, M., Müller, W., &#38; Scheytt, J. C. (2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>.","ama":"Koppelmann B, Messidat B, Becker M, Müller W, Scheytt JC. Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. In: <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>. ; 2014.","short":"B. Koppelmann, B. Messidat, M. Becker, W. Müller, J.C. Scheytt, in: Proceedings of the Design and Verification Conference Europe (DVCON Europe), München, 2014.","mla":"Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>, 2014.","bibtex":"@inproceedings{Koppelmann_Messidat_Becker_Müller_Scheytt_2014, place={München}, title={Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}, booktitle={Proceedings of the Design and Verification Conference Europe (DVCON Europe)}, author={Koppelmann, Bastian and Messidat, Bernd and Becker, Markus and Müller, Wolfgang and Scheytt, J. Christoph}, year={2014} }"},"abstract":[{"text":"In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation.","lang":"eng"}],"place":"München","author":[{"first_name":"Bastian","full_name":"Koppelmann, Bastian","id":"25260","last_name":"Koppelmann"},{"full_name":"Messidat, Bernd","first_name":"Bernd","last_name":"Messidat"},{"last_name":"Becker","first_name":"Markus","full_name":"Becker, Markus"},{"id":"16243","last_name":"Müller","first_name":"Wolfgang","full_name":"Müller, Wolfgang"},{"orcid":"https://orcid.org/0000-0002-5950-6618","id":"37144","last_name":"Scheytt","first_name":"J. Christoph","full_name":"Scheytt, J. Christoph"}],"title":"Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU","date_updated":"2023-02-01T08:12:02Z","_id":"34585","status":"public","language":[{"iso":"eng"}],"year":"2014","type":"conference","date_created":"2022-12-20T10:48:25Z","publication":"Proceedings of the Design and Verification Conference Europe (DVCON Europe)"},{"title":"Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU","author":[{"last_name":"Koppelmann","id":"25260","full_name":"Koppelmann, Bastian","first_name":"Bastian"},{"last_name":"Messidat","first_name":"Bernd","full_name":"Messidat, Bernd"},{"first_name":"Christoph","full_name":"Kuznik, Christoph","last_name":"Kuznik"},{"full_name":"Müller, Wolfgang","first_name":"Wolfgang","last_name":"Müller","id":"16243"},{"last_name":"Becker","first_name":"Markus","full_name":"Becker, Markus"},{"id":"37144","last_name":"Scheytt","full_name":"Scheytt, J. Christoph","first_name":"J. Christoph","orcid":"https://orcid.org/0000-0002-5950-6618"}],"place":"München","abstract":[{"text":"In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation.","lang":"eng"}],"citation":{"short":"B. Koppelmann, B. Messidat, C. Kuznik, W. Müller, M. Becker, J.C. Scheytt, in: Proceedings of the Design and Verification Conference Europe (DVCON Europe), München, 2014.","mla":"Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>, 2014.","bibtex":"@inproceedings{Koppelmann_Messidat_Kuznik_Müller_Becker_Scheytt_2014, place={München}, title={Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}, booktitle={Proceedings of the Design and Verification Conference Europe (DVCON Europe)}, author={Koppelmann, Bastian and Messidat, Bernd and Kuznik, Christoph and Müller, Wolfgang and Becker, Markus and Scheytt, J. Christoph}, year={2014} }","chicago":"Koppelmann, Bastian, Bernd Messidat, Christoph Kuznik, Wolfgang Müller, Markus Becker, and J. Christoph Scheytt. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” In <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>. München, 2014.","ieee":"B. Koppelmann, B. Messidat, C. Kuznik, W. Müller, M. Becker, and J. C. Scheytt, “Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” 2014.","ama":"Koppelmann B, Messidat B, Kuznik C, Müller W, Becker M, Scheytt JC. Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. In: <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>. ; 2014.","apa":"Koppelmann, B., Messidat, B., Kuznik, C., Müller, W., Becker, M., &#38; Scheytt, J. C. (2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>."},"user_id":"16243","keyword":["System Design","Verification"],"department":[{"_id":"58"}],"publication":"Proceedings of the Design and Verification Conference Europe (DVCON Europe)","date_created":"2022-12-20T10:45:38Z","type":"conference","year":"2014","language":[{"iso":"eng"}],"status":"public","_id":"34583","date_updated":"2025-02-26T14:42:18Z"},{"author":[{"full_name":"Laemmle, Benjamin","first_name":"Benjamin","last_name":"Laemmle"},{"last_name":"Schmalz","first_name":"Klaus","full_name":"Schmalz, Klaus"},{"full_name":"Borngräber, Johannes","first_name":"Johannes","last_name":"Borngräber"},{"last_name":"Scheytt","id":"37144","full_name":"Scheytt, Christoph","first_name":"Christoph"},{"last_name":"Weigel","full_name":"Weigel, Robert","first_name":"Robert"},{"last_name":"Koelpin","first_name":"Alexander","full_name":"Koelpin, Alexander"},{"last_name":"Kissinger","first_name":"Dietmar","full_name":"Kissinger, Dietmar"}],"conference":{"start_date":"2013.01.21","end_date":"2013.01.23"},"title":"A fully integrated 120-GHz six-port receiver front-end in a 130-nm SiGe BiCMOS technology","abstract":[{"lang":"eng","text":"A fully integrated six-port receiver front-end at 120 GHz center frequency including a low-noise-amplifier, a passive six-port network, a VCO, and four direct converters is presented in this publication. The overall architecture of the designed six-port receiver is analyzed and fundamental theory of the receiver given. The design of the six-port building blocks is described and measurement results are presented. All circuits have been fabricated in a 0.13μm 300-GHz f T SiGe BiCMOS technology. The fully integrated receiver consumes 85.9 rnA from a 3.3-V supply and occupies an area of 1.03mm 2 . The receiver includes a VCO with a center frequency of 117.15 GHz, a tuning range of 2.7 GHz, and a phase noise of -86 dBc/Hz at 1 MHz offset. The LNA shows a gain of 12 dB, a 3-dB bandwidth of 30 GHz at a power consumption of 9.2 rnA. The six-port core has a conversion gain of 3.6 dB, a P 1dB of -12 dBm, and a power consumption of 28 rnA. The overall receiver shows a conversion gain of 2.4 dB at 120 GHz and P 1dB of -17 dBm."}],"doi":"10.1109/SiRF.2013.6489455","user_id":"15931","citation":{"short":"B. Laemmle, K. Schmalz, J. Borngräber, C. Scheytt, R. Weigel, A. Koelpin, D. Kissinger, in: Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On, 2013.","bibtex":"@inproceedings{Laemmle_Schmalz_Borngräber_Scheytt_Weigel_Koelpin_Kissinger_2013, title={A fully integrated 120-GHz six-port receiver front-end in a 130-nm SiGe BiCMOS technology}, DOI={<a href=\"https://doi.org/10.1109/SiRF.2013.6489455\">10.1109/SiRF.2013.6489455</a>}, booktitle={Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on}, author={Laemmle, Benjamin and Schmalz, Klaus and Borngräber, Johannes and Scheytt, Christoph and Weigel, Robert and Koelpin, Alexander and Kissinger, Dietmar}, year={2013} }","mla":"Laemmle, Benjamin, et al. “A Fully Integrated 120-GHz Six-Port Receiver Front-End in a 130-Nm SiGe BiCMOS Technology.” <i>Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On</i>, 2013, doi:<a href=\"https://doi.org/10.1109/SiRF.2013.6489455\">10.1109/SiRF.2013.6489455</a>.","ieee":"B. Laemmle <i>et al.</i>, “A fully integrated 120-GHz six-port receiver front-end in a 130-nm SiGe BiCMOS technology,” 2013, doi: <a href=\"https://doi.org/10.1109/SiRF.2013.6489455\">10.1109/SiRF.2013.6489455</a>.","chicago":"Laemmle, Benjamin, Klaus Schmalz, Johannes Borngräber, Christoph Scheytt, Robert Weigel, Alexander Koelpin, and Dietmar Kissinger. “A Fully Integrated 120-GHz Six-Port Receiver Front-End in a 130-Nm SiGe BiCMOS Technology.” In <i>Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On</i>, 2013. <a href=\"https://doi.org/10.1109/SiRF.2013.6489455\">https://doi.org/10.1109/SiRF.2013.6489455</a>.","ama":"Laemmle B, Schmalz K, Borngräber J, et al. A fully integrated 120-GHz six-port receiver front-end in a 130-nm SiGe BiCMOS technology. In: <i>Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On</i>. ; 2013. doi:<a href=\"https://doi.org/10.1109/SiRF.2013.6489455\">10.1109/SiRF.2013.6489455</a>","apa":"Laemmle, B., Schmalz, K., Borngräber, J., Scheytt, C., Weigel, R., Koelpin, A., &#38; Kissinger, D. (2013). A fully integrated 120-GHz six-port receiver front-end in a 130-nm SiGe BiCMOS technology. <i>Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On</i>. <a href=\"https://doi.org/10.1109/SiRF.2013.6489455\">https://doi.org/10.1109/SiRF.2013.6489455</a>"},"department":[{"_id":"58"}],"publication":"Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on","date_created":"2021-09-14T09:22:35Z","related_material":{"link":[{"relation":"confirmation","url":"https://ieeexplore.ieee.org/document/6489455"}]},"status":"public","year":"2013","type":"conference","publication_identifier":{"eisbn":["978-1-4673-1553-1"]},"language":[{"iso":"eng"}],"_id":"24356","date_updated":"2022-02-17T09:02:41Z"},{"related_material":{"link":[{"relation":"confirmation","url":"https://ieeexplore.ieee.org/document/6489443"}]},"date_created":"2021-09-14T09:22:33Z","publication":"Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on","status":"public","language":[{"iso":"eng"}],"type":"conference","year":"2013","publication_identifier":{"eisbn":["978-1-4673-1553-1"]},"_id":"24355","page":"93-95","date_updated":"2022-02-17T09:01:16Z","author":[{"last_name":"Digel","full_name":"Digel, Johannes","first_name":"Johannes"},{"last_name":"Masini","full_name":"Masini, Michelangelo","first_name":"Michelangelo"},{"last_name":"Grözing","first_name":"Markus","full_name":"Grözing, Markus"},{"last_name":"Berroth","full_name":"Berroth, Manfred","first_name":"Manfred"},{"first_name":"Gunter","full_name":"Fischer, Gunter","last_name":"Fischer"},{"last_name":"Olonbayar","first_name":"Sonom","full_name":"Olonbayar, Sonom"},{"last_name":"Gustat","full_name":"Gustat, Hans","first_name":"Hans"},{"full_name":"Scheytt, Christoph","first_name":"Christoph","last_name":"Scheytt","id":"37144"}],"title":"Integrator and digitizer for a non-coherent IR-UWB receiver","conference":{"end_date":"2013.01.23","start_date":"2013.01.21"},"doi":"10.1109/SiRF.2013.6489443","abstract":[{"text":"Impulse-radio ultra-wideband systems (IR-UWB) provide short-range wireless communication and precise localization simultaneously. Especially non-coherent IR-UWB reduces the system complexity which enables the design of low-power receivers. This paper presents an integrating digitizer which integrates rectified baseband pulses of an IR-UWB signal and provides the digitized data to the digital baseband of the receiver. The integrator is composed of two time-interleaved (TI) operational amplifiers with capacitive feedback. With this structure, the integrator can be periodically reset without introducing a dead time between two integration periods. The analog-to-digital conversion is performed by a 6 bit 62.4 MS/s successive approximation register analog-to-digital converter (SAR ADC). The integrating digitizer chip is realized in a 250 nm SiGe:C BiCMOS technology from IHP.","lang":"eng"}],"user_id":"15931","citation":{"mla":"Digel, Johannes, et al. “Integrator and Digitizer for a Non-Coherent IR-UWB Receiver.” <i>Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On</i>, 2013, pp. 93–95, doi:<a href=\"https://doi.org/10.1109/SiRF.2013.6489443\">10.1109/SiRF.2013.6489443</a>.","apa":"Digel, J., Masini, M., Grözing, M., Berroth, M., Fischer, G., Olonbayar, S., Gustat, H., &#38; Scheytt, C. (2013). Integrator and digitizer for a non-coherent IR-UWB receiver. <i>Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On</i>, 93–95. <a href=\"https://doi.org/10.1109/SiRF.2013.6489443\">https://doi.org/10.1109/SiRF.2013.6489443</a>","bibtex":"@inproceedings{Digel_Masini_Grözing_Berroth_Fischer_Olonbayar_Gustat_Scheytt_2013, title={Integrator and digitizer for a non-coherent IR-UWB receiver}, DOI={<a href=\"https://doi.org/10.1109/SiRF.2013.6489443\">10.1109/SiRF.2013.6489443</a>}, booktitle={Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on}, author={Digel, Johannes and Masini, Michelangelo and Grözing, Markus and Berroth, Manfred and Fischer, Gunter and Olonbayar, Sonom and Gustat, Hans and Scheytt, Christoph}, year={2013}, pages={93–95} }","ama":"Digel J, Masini M, Grözing M, et al. Integrator and digitizer for a non-coherent IR-UWB receiver. In: <i>Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On</i>. ; 2013:93-95. doi:<a href=\"https://doi.org/10.1109/SiRF.2013.6489443\">10.1109/SiRF.2013.6489443</a>","short":"J. Digel, M. Masini, M. Grözing, M. Berroth, G. Fischer, S. Olonbayar, H. Gustat, C. Scheytt, in: Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On, 2013, pp. 93–95.","chicago":"Digel, Johannes, Michelangelo Masini, Markus Grözing, Manfred Berroth, Gunter Fischer, Sonom Olonbayar, Hans Gustat, and Christoph Scheytt. “Integrator and Digitizer for a Non-Coherent IR-UWB Receiver.” In <i>Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On</i>, 93–95, 2013. <a href=\"https://doi.org/10.1109/SiRF.2013.6489443\">https://doi.org/10.1109/SiRF.2013.6489443</a>.","ieee":"J. Digel <i>et al.</i>, “Integrator and digitizer for a non-coherent IR-UWB receiver,” in <i>Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on</i>, 2013, pp. 93–95, doi: <a href=\"https://doi.org/10.1109/SiRF.2013.6489443\">10.1109/SiRF.2013.6489443</a>."},"department":[{"_id":"58"}]},{"citation":{"bibtex":"@inproceedings{Sun_Marinkovic_Fischer_Winkler_Debski_Beer_Zwick_Girma_Hasch_Scheytt_2013, title={A low-cost miniature 120GHz SiP FMCW/CW radar sensor with software linearization}, DOI={<a href=\"https://doi.org/10.1109/ISSCC.2013.6487676\">10.1109/ISSCC.2013.6487676</a>}, booktitle={Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International}, author={Sun, Yaoming and Marinkovic, Miroslav and Fischer, Gunter and Winkler, Wolfgang and Debski, Wojciech and Beer, Stefan and Zwick, Thomas and Girma, Mekdes Gebresilassie and Hasch, Jürgen and Scheytt, Christoph}, year={2013}, pages={148–149} }","mla":"Sun, Yaoming, et al. “A Low-Cost Miniature 120GHz SiP FMCW/CW Radar Sensor with Software Linearization.” <i>Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International</i>, 2013, pp. 148–49, doi:<a href=\"https://doi.org/10.1109/ISSCC.2013.6487676\">10.1109/ISSCC.2013.6487676</a>.","short":"Y. Sun, M. Marinkovic, G. Fischer, W. Winkler, W. Debski, S. Beer, T. Zwick, M.G. Girma, J. Hasch, C. Scheytt, in: Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International, 2013, pp. 148–149.","ama":"Sun Y, Marinkovic M, Fischer G, et al. A low-cost miniature 120GHz SiP FMCW/CW radar sensor with software linearization. In: <i>Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International</i>. ; 2013:148-149. doi:<a href=\"https://doi.org/10.1109/ISSCC.2013.6487676\">10.1109/ISSCC.2013.6487676</a>","apa":"Sun, Y., Marinkovic, M., Fischer, G., Winkler, W., Debski, W., Beer, S., Zwick, T., Girma, M. G., Hasch, J., &#38; Scheytt, C. (2013). A low-cost miniature 120GHz SiP FMCW/CW radar sensor with software linearization. <i>Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International</i>, 148–149. <a href=\"https://doi.org/10.1109/ISSCC.2013.6487676\">https://doi.org/10.1109/ISSCC.2013.6487676</a>","ieee":"Y. Sun <i>et al.</i>, “A low-cost miniature 120GHz SiP FMCW/CW radar sensor with software linearization,” in <i>Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International</i>, 2013, pp. 148–149, doi: <a href=\"https://doi.org/10.1109/ISSCC.2013.6487676\">10.1109/ISSCC.2013.6487676</a>.","chicago":"Sun, Yaoming, Miroslav Marinkovic, Gunter Fischer, Wolfgang Winkler, Wojciech Debski, Stefan Beer, Thomas Zwick, Mekdes Gebresilassie Girma, Jürgen Hasch, and Christoph Scheytt. “A Low-Cost Miniature 120GHz SiP FMCW/CW Radar Sensor with Software Linearization.” In <i>Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International</i>, 148–49, 2013. <a href=\"https://doi.org/10.1109/ISSCC.2013.6487676\">https://doi.org/10.1109/ISSCC.2013.6487676</a>."},"user_id":"15931","department":[{"_id":"58"}],"title":"A low-cost miniature 120GHz SiP FMCW/CW radar sensor with software linearization","conference":{"end_date":"2013.02.21","start_date":"2013.02.17"},"author":[{"last_name":"Sun","first_name":"Yaoming","full_name":"Sun, Yaoming"},{"last_name":"Marinkovic","first_name":"Miroslav","full_name":"Marinkovic, Miroslav"},{"first_name":"Gunter","full_name":"Fischer, Gunter","last_name":"Fischer"},{"last_name":"Winkler","full_name":"Winkler, Wolfgang","first_name":"Wolfgang"},{"full_name":"Debski, Wojciech","first_name":"Wojciech","last_name":"Debski"},{"full_name":"Beer, Stefan","first_name":"Stefan","last_name":"Beer"},{"last_name":"Zwick","first_name":"Thomas","full_name":"Zwick, Thomas"},{"last_name":"Girma","full_name":"Girma, Mekdes Gebresilassie","first_name":"Mekdes Gebresilassie"},{"last_name":"Hasch","first_name":"Jürgen","full_name":"Hasch, Jürgen"},{"first_name":"Christoph","full_name":"Scheytt, Christoph","id":"37144","last_name":"Scheytt"}],"abstract":[{"lang":"eng","text":"This paper presents an integrated mixed-signal 120GHz FMCW/CW radar chipset in a 0.13μm SiGe BiCMOS technology. It features on-chip MMW built-in-self-test (BIST) circuits, a harmonic transceiver, software linearization (SWL) circuits and a digital interface. This chipset has been tested in a low-cost package, where the antennas are integrated. Above 100GHz, our transceiver has achieved state-ofthe-art integration level and receiver linearity, and DC power consumption."}],"doi":"10.1109/ISSCC.2013.6487676","page":"148-149","_id":"24353","date_updated":"2022-02-17T08:57:43Z","date_created":"2021-09-14T09:22:31Z","related_material":{"link":[{"url":"https://ieeexplore.ieee.org/document/6487676","relation":"confirmation"}]},"publication":"Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International","language":[{"iso":"eng"}],"year":"2013","publication_identifier":{"eisbn":["978-1-4673-4516-3"]},"type":"conference","status":"public"},{"place":"Austin TX","doi":"10.1109/SiRF.2013.6489494","abstract":[{"text":"Complex integrated 122 and 245 GHz SiGe BiCMOS transceiver ICs as well as an efficient broadband on-chip antenna are presented. The ICs target radar and sensing applications for the ISM bands at 122 and 245 GHz. Due to high level of integration and basic mm-wave self-testing production as well as test cost are dramatically reduced. Furthermore a compact and efficient on-chip antenna allows for chip-on-board mounting without RF interfaces.","lang":"eng"}],"conference":{"start_date":"2013.01.21","end_date":"2013.01.23"},"title":"Towards mm-wave System-On-Chip with integrated antennas for low-cost 122 and 245 GHz radar sensors","author":[{"full_name":"Scheytt, Christoph","first_name":"Christoph","last_name":"Scheytt","id":"37144"},{"full_name":"Sun, Yaoming","first_name":"Yaoming","last_name":"Sun"},{"last_name":"Schmalz","first_name":"Klaus","full_name":"Schmalz, Klaus"},{"last_name":"Mao","first_name":"Yanfei","full_name":"Mao, Yanfei"},{"last_name":"Wang","first_name":"Ruoyu","full_name":"Wang, Ruoyu"},{"last_name":"Debski","full_name":"Debski, Wojciech","first_name":"Wojciech"},{"last_name":"Winkler","first_name":"Wolfgang","full_name":"Winkler, Wolfgang"}],"department":[{"_id":"58"}],"citation":{"ama":"Scheytt C, Sun Y, Schmalz K, et al. Towards mm-wave System-On-Chip with integrated antennas for low-cost 122 and 245 GHz radar sensors. In: <i>Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On</i>. ; 2013:246-248. doi:<a href=\"https://doi.org/10.1109/SiRF.2013.6489494\">10.1109/SiRF.2013.6489494</a>","apa":"Scheytt, C., Sun, Y., Schmalz, K., Mao, Y., Wang, R., Debski, W., &#38; Winkler, W. (2013). Towards mm-wave System-On-Chip with integrated antennas for low-cost 122 and 245 GHz radar sensors. <i>Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On</i>, 246–248. <a href=\"https://doi.org/10.1109/SiRF.2013.6489494\">https://doi.org/10.1109/SiRF.2013.6489494</a>","chicago":"Scheytt, Christoph, Yaoming Sun, Klaus Schmalz, Yanfei Mao, Ruoyu Wang, Wojciech Debski, and Wolfgang Winkler. “Towards Mm-Wave System-On-Chip with Integrated Antennas for Low-Cost 122 and 245 GHz Radar Sensors.” In <i>Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On</i>, 246–48. Austin TX, 2013. <a href=\"https://doi.org/10.1109/SiRF.2013.6489494\">https://doi.org/10.1109/SiRF.2013.6489494</a>.","ieee":"C. Scheytt <i>et al.</i>, “Towards mm-wave System-On-Chip with integrated antennas for low-cost 122 and 245 GHz radar sensors,” in <i>Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on</i>, 2013, pp. 246–248, doi: <a href=\"https://doi.org/10.1109/SiRF.2013.6489494\">10.1109/SiRF.2013.6489494</a>.","mla":"Scheytt, Christoph, et al. “Towards Mm-Wave System-On-Chip with Integrated Antennas for Low-Cost 122 and 245 GHz Radar Sensors.” <i>Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On</i>, 2013, pp. 246–48, doi:<a href=\"https://doi.org/10.1109/SiRF.2013.6489494\">10.1109/SiRF.2013.6489494</a>.","bibtex":"@inproceedings{Scheytt_Sun_Schmalz_Mao_Wang_Debski_Winkler_2013, place={Austin TX}, title={Towards mm-wave System-On-Chip with integrated antennas for low-cost 122 and 245 GHz radar sensors}, DOI={<a href=\"https://doi.org/10.1109/SiRF.2013.6489494\">10.1109/SiRF.2013.6489494</a>}, booktitle={Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on}, author={Scheytt, Christoph and Sun, Yaoming and Schmalz, Klaus and Mao, Yanfei and Wang, Ruoyu and Debski, Wojciech and Winkler, Wolfgang}, year={2013}, pages={246–248} }","short":"C. Scheytt, Y. Sun, K. Schmalz, Y. Mao, R. Wang, W. Debski, W. Winkler, in: Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On, Austin TX, 2013, pp. 246–248."},"user_id":"15931","type":"conference","year":"2013","publication_identifier":{"eisbn":["978-1-4673-1553-1"]},"language":[{"iso":"eng"}],"status":"public","publication":"Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on","related_material":{"link":[{"url":"https://ieeexplore.ieee.org/document/6489494","relation":"confirmation"}]},"date_created":"2021-09-14T09:22:36Z","date_updated":"2022-02-17T09:03:54Z","_id":"24357","page":"246-248"},{"language":[{"iso":"eng"}],"year":"2013","type":"conference","status":"public","date_created":"2021-09-14T09:22:32Z","related_material":{"link":[{"url":"https://ieeexplore.ieee.org/document/6489451","relation":"confirmation"}]},"publication":"Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on","date_updated":"2022-02-17T08:59:40Z","_id":"24354","abstract":[{"text":"In this paper, a 6-bit true modular programmable frequency divider with division ratios ranging from 64 to 127 is reported. It is composed of a divider chain of 6 divide-by-2/3 cells, and ECL stages that are introduced as synchronization circuits for programming inputs. The synchronization circuits have CMOS input for compatibility with programming circuits. The stand-alone divider chain is functional up to an input clock frequency of 49 GHz. The combination of the divider chain with synchronization circuits is functional up to 44 GHz. The 6 stage divider draws 34 mA current from a 2.7 V supply. The synchronization circuits draw 30 mA from a 3 V supply. The circuit is fabricated in a 0.13 μm SiGe BiCMOS technology, and is well suited for millimeter-wave phase-locked loop (PLL) circuits which require fine frequency resolution.","lang":"eng"}],"doi":"10.1109/SiRF.2013.6489451","title":"49 GHz 6-bit programmable divider in SiGe BiCMOS","conference":{"end_date":"2013.01.23","start_date":"2013.01.21"},"author":[{"full_name":"Ergintav, Arzu","first_name":"Arzu","last_name":"Ergintav"},{"first_name":"Yaoming","full_name":"Sun, Yaoming","last_name":"Sun"},{"full_name":"Scheytt, Christoph","first_name":"Christoph","last_name":"Scheytt","id":"37144"},{"last_name":"Gürbüz","first_name":"Yasar","full_name":"Gürbüz, Yasar"}],"department":[{"_id":"58"}],"citation":{"apa":"Ergintav, A., Sun, Y., Scheytt, C., &#38; Gürbüz, Y. (2013). 49 GHz 6-bit programmable divider in SiGe BiCMOS. <i>Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On</i>. <a href=\"https://doi.org/10.1109/SiRF.2013.6489451\">https://doi.org/10.1109/SiRF.2013.6489451</a>","ama":"Ergintav A, Sun Y, Scheytt C, Gürbüz Y. 49 GHz 6-bit programmable divider in SiGe BiCMOS. In: <i>Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On</i>. ; 2013. doi:<a href=\"https://doi.org/10.1109/SiRF.2013.6489451\">10.1109/SiRF.2013.6489451</a>","chicago":"Ergintav, Arzu, Yaoming Sun, Christoph Scheytt, and Yasar Gürbüz. “49 GHz 6-Bit Programmable Divider in SiGe BiCMOS.” In <i>Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On</i>, 2013. <a href=\"https://doi.org/10.1109/SiRF.2013.6489451\">https://doi.org/10.1109/SiRF.2013.6489451</a>.","ieee":"A. Ergintav, Y. Sun, C. Scheytt, and Y. Gürbüz, “49 GHz 6-bit programmable divider in SiGe BiCMOS,” 2013, doi: <a href=\"https://doi.org/10.1109/SiRF.2013.6489451\">10.1109/SiRF.2013.6489451</a>.","mla":"Ergintav, Arzu, et al. “49 GHz 6-Bit Programmable Divider in SiGe BiCMOS.” <i>Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On</i>, 2013, doi:<a href=\"https://doi.org/10.1109/SiRF.2013.6489451\">10.1109/SiRF.2013.6489451</a>.","bibtex":"@inproceedings{Ergintav_Sun_Scheytt_Gürbüz_2013, title={49 GHz 6-bit programmable divider in SiGe BiCMOS}, DOI={<a href=\"https://doi.org/10.1109/SiRF.2013.6489451\">10.1109/SiRF.2013.6489451</a>}, booktitle={Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on}, author={Ergintav, Arzu and Sun, Yaoming and Scheytt, Christoph and Gürbüz, Yasar}, year={2013} }","short":"A. Ergintav, Y. Sun, C. Scheytt, Y. Gürbüz, in: Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On, 2013."},"user_id":"15931"},{"citation":{"ieee":"Y. Mao, K. Schmalz, J. Borngräber, and C. Scheytt, “245 GHz subharmonic receivers in SiGe,” 2013, doi: <a href=\"https://doi.org/10.1109/RFIC.2013.6569533\">10.1109/RFIC.2013.6569533</a>.","chicago":"Mao, Yanfei, Klaus Schmalz, Johannes Borngräber, and Christoph Scheytt. “245 GHz Subharmonic Receivers in SiGe.” In <i>2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium</i>. Seattle, Washington, 2013. <a href=\"https://doi.org/10.1109/RFIC.2013.6569533\">https://doi.org/10.1109/RFIC.2013.6569533</a>.","ama":"Mao Y, Schmalz K, Borngräber J, Scheytt C. 245 GHz subharmonic receivers in SiGe. In: <i>2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium</i>. ; 2013. doi:<a href=\"https://doi.org/10.1109/RFIC.2013.6569533\">10.1109/RFIC.2013.6569533</a>","apa":"Mao, Y., Schmalz, K., Borngräber, J., &#38; Scheytt, C. (2013). 245 GHz subharmonic receivers in SiGe. <i>2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium</i>. <a href=\"https://doi.org/10.1109/RFIC.2013.6569533\">https://doi.org/10.1109/RFIC.2013.6569533</a>","short":"Y. Mao, K. Schmalz, J. Borngräber, C. Scheytt, in: 2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Seattle, Washington, 2013.","bibtex":"@inproceedings{Mao_Schmalz_Borngräber_Scheytt_2013, place={Seattle, Washington}, title={245 GHz subharmonic receivers in SiGe}, DOI={<a href=\"https://doi.org/10.1109/RFIC.2013.6569533\">10.1109/RFIC.2013.6569533</a>}, booktitle={2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium}, author={Mao, Yanfei and Schmalz, Klaus and Borngräber, Johannes and Scheytt, Christoph}, year={2013} }","mla":"Mao, Yanfei, et al. “245 GHz Subharmonic Receivers in SiGe.” <i>2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium</i>, 2013, doi:<a href=\"https://doi.org/10.1109/RFIC.2013.6569533\">10.1109/RFIC.2013.6569533</a>."},"user_id":"15931","department":[{"_id":"58"}],"conference":{"end_date":"2013.06.04","start_date":"2013.06.02"},"title":"245 GHz subharmonic receivers in SiGe","author":[{"last_name":"Mao","first_name":"Yanfei","full_name":"Mao, Yanfei"},{"first_name":"Klaus","full_name":"Schmalz, Klaus","last_name":"Schmalz"},{"full_name":"Borngräber, Johannes","first_name":"Johannes","last_name":"Borngräber"},{"id":"37144","last_name":"Scheytt","full_name":"Scheytt, Christoph","first_name":"Christoph"}],"place":"Seattle, Washington","abstract":[{"text":"Two subharmonic receivers for 245 GHz spectroscopy sensor applications in the 245 GHz ISM band have been proposed. One receiver consists of an 2nd APDP (antiparallel diode pair) passive SHM (subharmonic mixer), a 120 GHz push-push VCO with 1/64 divider, and a 120 GHz PA (power amplifier). The other consists of a single-ended four-stage CB (common base) LNA, an 2 nd APDP passive SHM, an IF amplifier, a 120 GHz push-push VCO with 1/64 divider, and a 120 GHz PA. The receivers are fabricated in a SiGe:C BiCMOS technology with f T /f max =300/500 GHz. The measured conversion gain are -17 dB rsp. 10.6 dB at 245 GHz with 3-dB bandwidths of 13 GHz rsp. 14 GHz, and the single-side band noise figure are 17 dB rsp. 20 dB; the two receivers dissipates a power of 213 mW and 312 mW, respectively.","lang":"eng"}],"doi":"10.1109/RFIC.2013.6569533","_id":"24361","date_updated":"2022-02-17T09:14:10Z","publication":"2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","related_material":{"link":[{"url":"https://ieeexplore.ieee.org/document/6569533","relation":"confirmation"}]},"date_created":"2021-09-14T09:22:41Z","type":"conference","year":"2013","publication_identifier":{"eisbn":["978-1-4673-6062-3"]},"language":[{"iso":"eng"}],"status":"public"},{"_id":"24358","date_updated":"2022-02-17T09:05:42Z","related_material":{"link":[{"url":"https://ieeexplore.ieee.org/document/6569589","relation":"confirmation"}]},"date_created":"2021-09-14T09:22:37Z","publication":"2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium,","language":[{"iso":"eng"}],"publication_identifier":{"eisbn":["978-1-4673-6062-3"]},"type":"conference","year":"2013","status":"public","citation":{"chicago":"Elkhouly, Mohamed, Yanfei Mao, Chafik Meliani, Frank Ellinger, and Christoph Scheytt. “A 240 GHz Direct Conversion IQ Receiver in 0.13 Μm SiGe BiCMOS Technology.” In <i>2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium,</i>. Seattle, Washington, 2013. <a href=\"https://doi.org/10.1109/RFIC.2013.6569589\">https://doi.org/10.1109/RFIC.2013.6569589</a>.","ieee":"M. Elkhouly, Y. Mao, C. Meliani, F. Ellinger, and C. Scheytt, “A 240 GHz Direct Conversion IQ Receiver in 0.13 µm SiGe BiCMOS technology,” 2013, doi: <a href=\"https://doi.org/10.1109/RFIC.2013.6569589\">10.1109/RFIC.2013.6569589</a>.","apa":"Elkhouly, M., Mao, Y., Meliani, C., Ellinger, F., &#38; Scheytt, C. (2013). A 240 GHz Direct Conversion IQ Receiver in 0.13 µm SiGe BiCMOS technology. <i>2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium,</i>. <a href=\"https://doi.org/10.1109/RFIC.2013.6569589\">https://doi.org/10.1109/RFIC.2013.6569589</a>","ama":"Elkhouly M, Mao Y, Meliani C, Ellinger F, Scheytt C. A 240 GHz Direct Conversion IQ Receiver in 0.13 µm SiGe BiCMOS technology. In: <i>2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium,</i>. ; 2013. doi:<a href=\"https://doi.org/10.1109/RFIC.2013.6569589\">10.1109/RFIC.2013.6569589</a>","short":"M. Elkhouly, Y. Mao, C. Meliani, F. Ellinger, C. Scheytt, in: 2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Seattle, Washington, 2013.","mla":"Elkhouly, Mohamed, et al. “A 240 GHz Direct Conversion IQ Receiver in 0.13 Μm SiGe BiCMOS Technology.” <i>2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium,</i> 2013, doi:<a href=\"https://doi.org/10.1109/RFIC.2013.6569589\">10.1109/RFIC.2013.6569589</a>.","bibtex":"@inproceedings{Elkhouly_Mao_Meliani_Ellinger_Scheytt_2013, place={Seattle, Washington}, title={A 240 GHz Direct Conversion IQ Receiver in 0.13 µm SiGe BiCMOS technology}, DOI={<a href=\"https://doi.org/10.1109/RFIC.2013.6569589\">10.1109/RFIC.2013.6569589</a>}, booktitle={2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium,}, author={Elkhouly, Mohamed and Mao, Yanfei and Meliani, Chafik and Ellinger, Frank and Scheytt, Christoph}, year={2013} }"},"user_id":"15931","department":[{"_id":"58"}],"title":"A 240 GHz Direct Conversion IQ Receiver in 0.13 µm SiGe BiCMOS technology","conference":{"end_date":"2013.06.04","start_date":"2013.06.02"},"author":[{"full_name":"Elkhouly, Mohamed","first_name":"Mohamed","last_name":"Elkhouly"},{"first_name":"Yanfei","full_name":"Mao, Yanfei","last_name":"Mao"},{"first_name":"Chafik","full_name":"Meliani, Chafik","last_name":"Meliani"},{"full_name":"Ellinger, Frank","first_name":"Frank","last_name":"Ellinger"},{"first_name":"Christoph","full_name":"Scheytt, Christoph","id":"37144","last_name":"Scheytt"}],"place":"Seattle, Washington","abstract":[{"lang":"eng","text":"A 240 GHz direct conversion IQ receiver manufactured in 0.13 SiGe BiCMOS technology with f T /f max of 300/500 GHz is presented. The receiver consists of a four stage LNA, an active power divider, an LO IQ generation network, and direct down-conversion fundamental mixers. The integrated IQ receiver yields a conversion gain of 18 dB, an 18 dB simulated DSB NF, and a 3 dB bandwidth of 25 GHz. The required 245 GHz LO power is in the order of -10 dBm. The receiver exhibits an IQ amplitude and phase imbalance of 1 dB and 3° respectively. It draws 135 mA from the 3.5 V supply and 20 mA from 2 V."}],"doi":"10.1109/RFIC.2013.6569589"},{"place":"Seattle, Washington","doi":"10.1109/MWSYM.2013.6697429","abstract":[{"text":"A subharmonic receiver for 245 GHz spectroscopy sensor applications have been proposed. The receiver consists of a CB (common base) LNA, 2 nd transconductance SHM (subharmonic mixer) and a 120 GHz push-push VCO with 1/64 divider. The receiver is fabricated in f T /f max =300/500 GHz SiGe: C BiCMOS technology. Its measured single-ended gain is 14.3 dB at 245 GHz with tuning range of 15 GHz, and the single-side band noise figure is 19 dB. The input 1-dB compression point is at -24 dBm. The receiver dissipates a power of 200 mW.","lang":"eng"}],"conference":{"end_date":"2013.06.07","start_date":"2013.06.02"},"title":"245 GHz Subharmonic Receiver in SiGe","author":[{"full_name":"Mao, Yanfei","first_name":"Yanfei","last_name":"Mao"},{"first_name":"Klaus","full_name":"Schmalz, Klaus","last_name":"Schmalz"},{"last_name":"Borngräber","first_name":"Johannes","full_name":"Borngräber, Johannes"},{"id":"37144","last_name":"Scheytt","full_name":"Scheytt, Christoph","first_name":"Christoph"},{"full_name":"Meliani, Chafik","first_name":"Chafik","last_name":"Meliani"}],"department":[{"_id":"58"}],"citation":{"bibtex":"@inproceedings{Mao_Schmalz_Borngräber_Scheytt_Meliani_2013, place={Seattle, Washington}, title={245 GHz Subharmonic Receiver in SiGe}, DOI={<a href=\"https://doi.org/10.1109/MWSYM.2013.6697429\">10.1109/MWSYM.2013.6697429</a>}, booktitle={IEEE International Microwave Symposium, Advances in Low Noise Amplifiers and Receivers}, author={Mao, Yanfei and Schmalz, Klaus and Borngräber, Johannes and Scheytt, Christoph and Meliani, Chafik}, year={2013} }","ama":"Mao Y, Schmalz K, Borngräber J, Scheytt C, Meliani C. 245 GHz Subharmonic Receiver in SiGe. In: <i>IEEE International Microwave Symposium, Advances in Low Noise Amplifiers and Receivers</i>. ; 2013. doi:<a href=\"https://doi.org/10.1109/MWSYM.2013.6697429\">10.1109/MWSYM.2013.6697429</a>","apa":"Mao, Y., Schmalz, K., Borngräber, J., Scheytt, C., &#38; Meliani, C. (2013). 245 GHz Subharmonic Receiver in SiGe. <i>IEEE International Microwave Symposium, Advances in Low Noise Amplifiers and Receivers</i>. <a href=\"https://doi.org/10.1109/MWSYM.2013.6697429\">https://doi.org/10.1109/MWSYM.2013.6697429</a>","mla":"Mao, Yanfei, et al. “245 GHz Subharmonic Receiver in SiGe.” <i>IEEE International Microwave Symposium, Advances in Low Noise Amplifiers and Receivers</i>, 2013, doi:<a href=\"https://doi.org/10.1109/MWSYM.2013.6697429\">10.1109/MWSYM.2013.6697429</a>.","ieee":"Y. Mao, K. Schmalz, J. Borngräber, C. Scheytt, and C. Meliani, “245 GHz Subharmonic Receiver in SiGe,” 2013, doi: <a href=\"https://doi.org/10.1109/MWSYM.2013.6697429\">10.1109/MWSYM.2013.6697429</a>.","short":"Y. Mao, K. Schmalz, J. Borngräber, C. Scheytt, C. Meliani, in: IEEE International Microwave Symposium, Advances in Low Noise Amplifiers and Receivers, Seattle, Washington, 2013.","chicago":"Mao, Yanfei, Klaus Schmalz, Johannes Borngräber, Christoph Scheytt, and Chafik Meliani. “245 GHz Subharmonic Receiver in SiGe.” In <i>IEEE International Microwave Symposium, Advances in Low Noise Amplifiers and Receivers</i>. Seattle, Washington, 2013. <a href=\"https://doi.org/10.1109/MWSYM.2013.6697429\">https://doi.org/10.1109/MWSYM.2013.6697429</a>."},"user_id":"15931","type":"conference","publication_identifier":{"eisbn":["978-1-4673-6176-7"]},"year":"2013","language":[{"iso":"eng"}],"status":"public","publication":"IEEE International Microwave Symposium, Advances in Low Noise Amplifiers and Receivers","date_created":"2021-09-14T09:22:42Z","related_material":{"link":[{"relation":"confirmation","url":"https://ieeexplore.ieee.org/document/6697429"}]},"date_updated":"2022-02-17T09:23:50Z","_id":"24362"},{"user_id":"15931","citation":{"short":"C. Scheytt, in: IEEE International Conference on Communications, Budapest, 2013.","chicago":"Scheytt, Christoph. “Wireless 100Gb/s Using A Powerand.” In <i>IEEE International Conference on Communications</i>. Budapest, 2013.","ieee":"C. Scheytt, “Wireless 100Gb/s Using A Powerand,” 2013.","mla":"Scheytt, Christoph. “Wireless 100Gb/s Using A Powerand.” <i>IEEE International Conference on Communications</i>, 2013.","ama":"Scheytt C. Wireless 100Gb/s Using A Powerand. In: <i>IEEE International Conference on Communications</i>. ; 2013.","bibtex":"@inproceedings{Scheytt_2013, place={Budapest}, title={Wireless 100Gb/s Using A Powerand}, booktitle={IEEE International Conference on Communications}, author={Scheytt, Christoph}, year={2013} }","apa":"Scheytt, C. (2013). Wireless 100Gb/s Using A Powerand. <i>IEEE International Conference on Communications</i>."},"department":[{"_id":"58"}],"author":[{"first_name":"Christoph","full_name":"Scheytt, Christoph","id":"37144","last_name":"Scheytt"}],"title":"Wireless 100Gb/s Using A Powerand","place":"Budapest","_id":"24360","date_updated":"2022-02-17T09:12:09Z","publication":"IEEE International Conference on Communications","date_created":"2021-09-14T09:22:40Z","related_material":{"link":[{"url":"https://www.wireless100gb.de/publication/ICC2013-Panel_P5_Christoph_Scheytt.pdf","relation":"confirmation"}]},"status":"public","type":"conference","year":"2013","language":[{"iso":"eng"}]},{"author":[{"full_name":"Scheytt, Christoph","first_name":"Christoph","id":"37144","last_name":"Scheytt"}],"title":"Hardware-Effizientes Mixed-Signal Entzerrfilter","department":[{"_id":"58"}],"user_id":"15931","citation":{"short":"C. Scheytt, Hardware-Effizientes Mixed-Signal Entzerrfilter, 2013.","mla":"Scheytt, Christoph. <i>Hardware-Effizientes Mixed-Signal Entzerrfilter</i>. 2013.","bibtex":"@book{Scheytt_2013, title={Hardware-Effizientes Mixed-Signal Entzerrfilter}, author={Scheytt, Christoph}, year={2013} }","chicago":"Scheytt, Christoph. <i>Hardware-Effizientes Mixed-Signal Entzerrfilter</i>, 2013.","ieee":"C. Scheytt, <i>Hardware-Effizientes Mixed-Signal Entzerrfilter</i>. 2013.","ama":"Scheytt C. <i>Hardware-Effizientes Mixed-Signal Entzerrfilter</i>.; 2013.","apa":"Scheytt, C. (2013). <i>Hardware-Effizientes Mixed-Signal Entzerrfilter</i>."},"status":"public","language":[{"iso":"eng"}],"year":"2013","type":"misc","date_created":"2021-09-14T09:22:39Z","date_updated":"2022-02-17T09:09:43Z","_id":"24359"},{"place":"Nürnberg Convention Center","author":[{"id":"37144","last_name":"Scheytt","full_name":"Scheytt, Christoph","first_name":"Christoph"},{"full_name":"Sun, Yaoming","first_name":"Yaoming","last_name":"Sun"},{"last_name":"Schmalz","first_name":"Klaus","full_name":"Schmalz, Klaus"},{"first_name":"Yanfei","full_name":"Mao, Yanfei","last_name":"Mao"},{"first_name":"Ruoyu","full_name":"Wang, Ruoyu","last_name":"Wang"},{"last_name":"Debski","first_name":"Wojciech","full_name":"Debski, Wojciech"},{"full_name":"Winkler, Wolfgang","first_name":"Wolfgang","last_name":"Winkler"}],"title":"mm-Wave System-On-Chip Design in 0,13µm SiGe BiCMOS","department":[{"_id":"58"}],"user_id":"15931","citation":{"bibtex":"@inproceedings{Scheytt_Sun_Schmalz_Mao_Wang_Debski_Winkler_2013, place={Nürnberg Convention Center}, title={mm-Wave System-On-Chip Design in 0,13µm SiGe BiCMOS}, booktitle={W 06 (EuMC &#38; EuMIC)}, author={Scheytt, Christoph and Sun, Yaoming and Schmalz, Klaus and Mao, Yanfei and Wang, Ruoyu and Debski, Wojciech and Winkler, Wolfgang}, year={2013} }","mla":"Scheytt, Christoph, et al. “Mm-Wave System-On-Chip Design in 0,13µm SiGe BiCMOS.” <i>W 06 (EuMC &#38; EuMIC)</i>, 2013.","short":"C. Scheytt, Y. Sun, K. Schmalz, Y. Mao, R. Wang, W. Debski, W. Winkler, in: W 06 (EuMC &#38; EuMIC), Nürnberg Convention Center, 2013.","ama":"Scheytt C, Sun Y, Schmalz K, et al. mm-Wave System-On-Chip Design in 0,13µm SiGe BiCMOS. In: <i>W 06 (EuMC &#38; EuMIC)</i>. ; 2013.","apa":"Scheytt, C., Sun, Y., Schmalz, K., Mao, Y., Wang, R., Debski, W., &#38; Winkler, W. (2013). mm-Wave System-On-Chip Design in 0,13µm SiGe BiCMOS. <i>W 06 (EuMC &#38; EuMIC)</i>.","ieee":"C. Scheytt <i>et al.</i>, “mm-Wave System-On-Chip Design in 0,13µm SiGe BiCMOS,” 2013.","chicago":"Scheytt, Christoph, Yaoming Sun, Klaus Schmalz, Yanfei Mao, Ruoyu Wang, Wojciech Debski, and Wolfgang Winkler. “Mm-Wave System-On-Chip Design in 0,13µm SiGe BiCMOS.” In <i>W 06 (EuMC &#38; EuMIC)</i>. Nürnberg Convention Center, 2013."},"status":"public","language":[{"iso":"eng"}],"type":"conference","year":"2013","related_material":{"link":[{"relation":"confirmation","url":"https://www.eumweek.com/archive/eumweek2013/2013/default.html"}]},"date_created":"2021-09-14T09:22:13Z","publication":"W 06 (EuMC & EuMIC)","date_updated":"2022-01-10T10:46:14Z","_id":"24339"},{"title":"Design and Analysis of Down-Conversion Gate/Base-Pumped Harmonic Mixers Using Novel Reduced-Size 180 ^\\circ Hybrid With Different Input Frequencies ","author":[{"last_name":"Kuo","first_name":"Jhe-Jia","full_name":"Kuo, Jhe-Jia"},{"first_name":"Chun-Hsien","full_name":"Lien, Chun-Hsien","last_name":"Lien"},{"full_name":"Tsai, Zuo-Min","first_name":"Zuo-Min","last_name":"Tsai"},{"full_name":"Lin, Kun-You","first_name":"Kun-You","last_name":"Lin"},{"last_name":"Schmalz","first_name":"Klaus","full_name":"Schmalz, Klaus"},{"full_name":"Scheytt, Christoph","first_name":"Christoph","last_name":"Scheytt","id":"37144"},{"first_name":"Huei","full_name":"Wang, Huei","last_name":"Wang"}],"abstract":[{"text":"In this paper, a novel 180°hybrid with different input frequencies is proposed to combine RF and local oscillator (LO) signals with different frequencies in a gate/base-pumped harmonic mixer. The detailed analysis and design procedures are presented in this paper. To further reduce the chip size, the multilayer metallization above the lossy silicon substrate is employed to implement the hybrid. A V-band down-converted 2× harmonic mixer in 90-nm CMOS process and a D-band down-converted 4× harmonic mixer in the 130-nm SiGe process are designed, fabricated, and measured to verify the concept. The 2× harmonic mixer possesses 0-dB conversion gain at 60 GHz with 0-dBm LO power with merely 2.4-mW dc power. The 4× harmonic mixer achieves 0.5-dB conversion gain at 120 GHz with 2-dBm LO power and 27.3-mW dc power. With the proposed reduced-size 180° hybrid, gate/base-pumped harmonic mixers are very attractive in transceivers demanding low LO frequency and power.","lang":"eng"}],"intvolume":"        60","doi":"10.1109/TMTT.2012.2202039","citation":{"bibtex":"@article{Kuo_Lien_Tsai_Lin_Schmalz_Scheytt_Wang_2013, title={Design and Analysis of Down-Conversion Gate/Base-Pumped Harmonic Mixers Using Novel Reduced-Size 180 ^\\circ Hybrid With Different Input Frequencies }, volume={60}, DOI={<a href=\"https://doi.org/10.1109/TMTT.2012.2202039\">10.1109/TMTT.2012.2202039</a>}, number={8}, journal={Microwave Theory and Techniques, IEEE Transactions on}, author={Kuo, Jhe-Jia and Lien, Chun-Hsien and Tsai, Zuo-Min and Lin, Kun-You and Schmalz, Klaus and Scheytt, Christoph and Wang, Huei}, year={2013}, pages={2473–2485} }","mla":"Kuo, Jhe-Jia, et al. “Design and Analysis of Down-Conversion Gate/Base-Pumped Harmonic Mixers Using Novel Reduced-Size 180 ^\\circ Hybrid With Different Input Frequencies .” <i>Microwave Theory and Techniques, IEEE Transactions On</i>, vol. 60, no. 8, 2013, pp. 2473–85, doi:<a href=\"https://doi.org/10.1109/TMTT.2012.2202039\">10.1109/TMTT.2012.2202039</a>.","short":"J.-J. Kuo, C.-H. Lien, Z.-M. Tsai, K.-Y. Lin, K. Schmalz, C. Scheytt, H. Wang, Microwave Theory and Techniques, IEEE Transactions On 60 (2013) 2473–2485.","apa":"Kuo, J.-J., Lien, C.-H., Tsai, Z.-M., Lin, K.-Y., Schmalz, K., Scheytt, C., &#38; Wang, H. (2013). Design and Analysis of Down-Conversion Gate/Base-Pumped Harmonic Mixers Using Novel Reduced-Size 180 ^\\circ Hybrid With Different Input Frequencies . <i>Microwave Theory and Techniques, IEEE Transactions On</i>, <i>60</i>(8), 2473–2485. <a href=\"https://doi.org/10.1109/TMTT.2012.2202039\">https://doi.org/10.1109/TMTT.2012.2202039</a>","ama":"Kuo J-J, Lien C-H, Tsai Z-M, et al. Design and Analysis of Down-Conversion Gate/Base-Pumped Harmonic Mixers Using Novel Reduced-Size 180 ^\\circ Hybrid With Different Input Frequencies . <i>Microwave Theory and Techniques, IEEE Transactions on</i>. 2013;60(8):2473-2485. doi:<a href=\"https://doi.org/10.1109/TMTT.2012.2202039\">10.1109/TMTT.2012.2202039</a>","ieee":"J.-J. Kuo <i>et al.</i>, “Design and Analysis of Down-Conversion Gate/Base-Pumped Harmonic Mixers Using Novel Reduced-Size 180 ^\\circ Hybrid With Different Input Frequencies ,” <i>Microwave Theory and Techniques, IEEE Transactions on</i>, vol. 60, no. 8, pp. 2473–2485, 2013, doi: <a href=\"https://doi.org/10.1109/TMTT.2012.2202039\">10.1109/TMTT.2012.2202039</a>.","chicago":"Kuo, Jhe-Jia, Chun-Hsien Lien, Zuo-Min Tsai, Kun-You Lin, Klaus Schmalz, Christoph Scheytt, and Huei Wang. “Design and Analysis of Down-Conversion Gate/Base-Pumped Harmonic Mixers Using Novel Reduced-Size 180 ^\\circ Hybrid With Different Input Frequencies .” <i>Microwave Theory and Techniques, IEEE Transactions On</i> 60, no. 8 (2013): 2473–85. <a href=\"https://doi.org/10.1109/TMTT.2012.2202039\">https://doi.org/10.1109/TMTT.2012.2202039</a>."},"user_id":"15931","department":[{"_id":"58"}],"publication":"Microwave Theory and Techniques, IEEE Transactions on","related_material":{"link":[{"url":"https://ieeexplore.ieee.org/document/6214582","relation":"confirmation"}]},"date_created":"2021-09-14T09:22:19Z","year":"2013","type":"journal_article","language":[{"iso":"eng"}],"status":"public","_id":"24344","page":"2473-2485","volume":60,"date_updated":"2022-01-11T10:44:00Z","issue":"8"}]