---
_id: '24306'
author:
- first_name: Mohamed
full_name: Elkhouly, Mohamed
last_name: Elkhouly
- first_name: Yanfei
full_name: Mao, Yanfei
last_name: Mao
- first_name: Chafik
full_name: Meliani, Chafik
last_name: Meliani
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
- first_name: Frank
full_name: Ellinger, Frank
last_name: Ellinger
citation:
ama: Elkhouly M, Mao Y, Meliani C, Scheytt C, Ellinger F. A -Band Four-Element Butler
Matrix in 0.13 µm SiGe BiCMOS Technology. IEEE JOURNAL OF SOLID-STATE CIRCUITS.
2014;49(9).
apa: Elkhouly, M., Mao, Y., Meliani, C., Scheytt, C., & Ellinger, F. (2014).
A -Band Four-Element Butler Matrix in 0.13 µm SiGe BiCMOS Technology. IEEE
JOURNAL OF SOLID-STATE CIRCUITS, 49(9).
bibtex: '@article{Elkhouly_Mao_Meliani_Scheytt_Ellinger_2014, title={A -Band Four-Element
Butler Matrix in 0.13 µm SiGe BiCMOS Technology}, volume={49}, number={9}, journal={IEEE
JOURNAL OF SOLID-STATE CIRCUITS}, author={Elkhouly, Mohamed and Mao, Yanfei and
Meliani, Chafik and Scheytt, Christoph and Ellinger, Frank}, year={2014} }'
chicago: Elkhouly, Mohamed, Yanfei Mao, Chafik Meliani, Christoph Scheytt, and Frank
Ellinger. “A -Band Four-Element Butler Matrix in 0.13 Μm SiGe BiCMOS Technology.”
IEEE JOURNAL OF SOLID-STATE CIRCUITS 49, no. 9 (2014).
ieee: M. Elkhouly, Y. Mao, C. Meliani, C. Scheytt, and F. Ellinger, “A -Band Four-Element
Butler Matrix in 0.13 µm SiGe BiCMOS Technology,” IEEE JOURNAL OF SOLID-STATE
CIRCUITS, vol. 49, no. 9, 2014.
mla: Elkhouly, Mohamed, et al. “A -Band Four-Element Butler Matrix in 0.13 Μm SiGe
BiCMOS Technology.” IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 49, no.
9, 2014.
short: M. Elkhouly, Y. Mao, C. Meliani, C. Scheytt, F. Ellinger, IEEE JOURNAL OF
SOLID-STATE CIRCUITS 49 (2014).
date_created: 2021-09-14T07:06:52Z
date_updated: 2022-02-17T12:48:32Z
department:
- _id: '58'
intvolume: ' 49'
issue: '9'
language:
- iso: eng
publication: IEEE JOURNAL OF SOLID-STATE CIRCUITS
status: public
title: A -Band Four-Element Butler Matrix in 0.13 µm SiGe BiCMOS Technology
type: journal_article
user_id: '15931'
volume: 49
year: '2014'
...
---
_id: '24311'
abstract:
- lang: eng
text: Intelligent automotive electronics significantly improved driving safety in
the last decades. With the increasing complexity of automotive systems, dependability
of the electronic components themselves and of their interaction must be assured
to avoid any risk to driving safety due to unexpected failures caused by internal
or external faults. Additionally, Virtual Prototypes (VPs) have been accepted
in many areas of system development processes in the automotive industry as platforms
for SW development, verification, and design space exploration. We believe that
VPs will significantly contribute to the analysis of safety conditions for automotive
electronics. This paper shows the advantages of such a methodology based on today's
industrial needs, presents the current state of the art in this field, and outlines
upcoming research challenges that need to be addressed to make this vision a reality.
author:
- first_name: Jan-Hendrik
full_name: Oetjens, Jan-Hendrik
last_name: Oetjens
- first_name: Markus
full_name: Becker, Markus
last_name: Becker
- first_name: Christoph
full_name: Kuznik, Christoph
last_name: Kuznik
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Nico
full_name: Bannow, Nico
last_name: Bannow
- first_name: Oliver
full_name: Brinkmann, Oliver
last_name: Brinkmann
- first_name: Andreas
full_name: Burger, Andreas
last_name: Burger
- first_name: Moomen
full_name: Chaari, Moomen
last_name: Chaari
- first_name: Samarjit
full_name: Chakraborty, Samarjit
last_name: Chakraborty
- first_name: R.
full_name: Drechsler, R.
last_name: Drechsler
- first_name: Wolfgang
full_name: Ecker, Wolfgang
last_name: Ecker
- first_name: Kim
full_name: Grüttner, Kim
last_name: Grüttner
- first_name: Thomas
full_name: Kruse, Thomas
last_name: Kruse
- first_name: Hoang M
full_name: Le, Hoang M
last_name: Le
- first_name: M.
full_name: Mauderer, M.
last_name: Mauderer
- first_name: Daniel
full_name: Mueller-Gritschneider, Daniel
last_name: Mueller-Gritschneider
- first_name: Frank
full_name: Poppen, Frank
last_name: Poppen
- first_name: Hendrik
full_name: Post, Hendrik
last_name: Post
- first_name: SEbastian
full_name: Reiter, SEbastian
last_name: Reiter
- first_name: Wolfgang
full_name: Rosenstiel, Wolfgang
last_name: Rosenstiel
- first_name: 'S. '
full_name: 'Roth, S. '
last_name: Roth
- first_name: Ulf
full_name: Schlichtmann, Ulf
last_name: Schlichtmann
- first_name: Andreas
full_name: Von Schwerin, Andreas
last_name: Von Schwerin
- first_name: Bogdan Andrei
full_name: Tabacaru, Bogdan Andrei
last_name: Tabacaru
- first_name: Alexander
full_name: Viehl, Alexander
last_name: Viehl
citation:
ama: 'Oetjens J-H, Becker M, Kuznik C, et al. Safety Evaluation of Automotive Electronics
Using Virtual Prototypes: State of the Art and Research Challenges. In: Design
Automation Conference (DAC). ; 2014. doi:10.1145/2593069.2602976'
apa: 'Oetjens, J.-H., Becker, M., Kuznik, C., Müller, W., Bannow, N., Brinkmann,
O., Burger, A., Chaari, M., Chakraborty, S., Drechsler, R., Ecker, W., Grüttner,
K., Kruse, T., Le, H. M., Mauderer, M., Mueller-Gritschneider, D., Poppen, F.,
Post, H., Reiter, Se., … Viehl, A. (2014). Safety Evaluation of Automotive Electronics
Using Virtual Prototypes: State of the Art and Research Challenges. Design
Automation Conference (DAC). https://doi.org/10.1145/2593069.2602976'
bibtex: '@inproceedings{Oetjens_Becker_Kuznik_Müller_Bannow_Brinkmann_Burger_Chaari_Chakraborty_Drechsler_et
al._2014, title={Safety Evaluation of Automotive Electronics Using Virtual Prototypes:
State of the Art and Research Challenges}, DOI={10.1145/2593069.2602976},
booktitle={Design Automation Conference (DAC)}, author={Oetjens, Jan-Hendrik and
Becker, Markus and Kuznik, Christoph and Müller, Wolfgang and Bannow, Nico and
Brinkmann, Oliver and Burger, Andreas and Chaari, Moomen and Chakraborty, Samarjit
and Drechsler, R. and et al.}, year={2014} }'
chicago: 'Oetjens, Jan-Hendrik, Markus Becker, Christoph Kuznik, Wolfgang Müller,
Nico Bannow, Oliver Brinkmann, Andreas Burger, et al. “Safety Evaluation of Automotive
Electronics Using Virtual Prototypes: State of the Art and Research Challenges.”
In Design Automation Conference (DAC), 2014. https://doi.org/10.1145/2593069.2602976.'
ieee: 'J.-H. Oetjens et al., “Safety Evaluation of Automotive Electronics
Using Virtual Prototypes: State of the Art and Research Challenges,” 2014, doi:
10.1145/2593069.2602976.'
mla: 'Oetjens, Jan-Hendrik, et al. “Safety Evaluation of Automotive Electronics
Using Virtual Prototypes: State of the Art and Research Challenges.” Design
Automation Conference (DAC), 2014, doi:10.1145/2593069.2602976.'
short: 'J.-H. Oetjens, M. Becker, C. Kuznik, W. Müller, N. Bannow, O. Brinkmann,
A. Burger, M. Chaari, S. Chakraborty, R. Drechsler, W. Ecker, K. Grüttner, T.
Kruse, H.M. Le, M. Mauderer, D. Mueller-Gritschneider, F. Poppen, H. Post, Se.
Reiter, W. Rosenstiel, S. Roth, U. Schlichtmann, A. Von Schwerin, B.A. Tabacaru,
A. Viehl, in: Design Automation Conference (DAC), 2014.'
date_created: 2021-09-14T07:06:59Z
date_updated: 2022-02-17T13:47:16Z
department:
- _id: '58'
doi: 10.1145/2593069.2602976
language:
- iso: eng
publication: Design Automation Conference (DAC)
related_material:
link:
- relation: confirmation
url: https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6881440
status: public
title: 'Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State
of the Art and Research Challenges'
type: conference
user_id: '15931'
year: '2014'
...
---
_id: '24301'
author:
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
orcid: https://orcid.org/0000-0002-5950-6618
citation:
ama: 'Scheytt C. mm-Wellen- und Electronic-Photonic System-on-Chip Design. In: Fakultätskolloquium
Der Fakultät Für Elektrotechnik Und Informationstechnik. ; 2014.'
apa: Scheytt, C. (2014). mm-Wellen- und Electronic-Photonic System-on-Chip Design.
Fakultätskolloquium Der Fakultät Für Elektrotechnik Und Informationstechnik.
bibtex: '@inproceedings{Scheytt_2014, place={Institut für Technologie, Karlsruhe},
title={mm-Wellen- und Electronic-Photonic System-on-Chip Design}, booktitle={Fakultätskolloquium
der Fakultät für Elektrotechnik und Informationstechnik}, author={Scheytt, Christoph},
year={2014} }'
chicago: Scheytt, Christoph. “Mm-Wellen- Und Electronic-Photonic System-on-Chip
Design.” In Fakultätskolloquium Der Fakultät Für Elektrotechnik Und Informationstechnik.
Institut für Technologie, Karlsruhe, 2014.
ieee: C. Scheytt, “mm-Wellen- und Electronic-Photonic System-on-Chip Design,” 2014.
mla: Scheytt, Christoph. “Mm-Wellen- Und Electronic-Photonic System-on-Chip Design.”
Fakultätskolloquium Der Fakultät Für Elektrotechnik Und Informationstechnik,
2014.
short: 'C. Scheytt, in: Fakultätskolloquium Der Fakultät Für Elektrotechnik Und
Informationstechnik, Institut für Technologie, Karlsruhe, 2014.'
date_created: 2021-09-14T07:06:46Z
date_updated: 2023-01-10T12:48:54Z
department:
- _id: '58'
- _id: '230'
language:
- iso: eng
place: Institut für Technologie, Karlsruhe
publication: Fakultätskolloquium der Fakultät für Elektrotechnik und Informationstechnik
status: public
title: mm-Wellen- und Electronic-Photonic System-on-Chip Design
type: conference
user_id: '15931'
year: '2014'
...
---
_id: '25120'
author:
- first_name: Fabian
full_name: Mischkalla, Fabian
last_name: Mischkalla
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Mischkalla F, Müller W. Architectural Low-Power Design Using Transaction-Based
System Simulation. In: Embedded Computer Systems: Architectures, Modeling,
and Simulation (SAMOS XIV). IEEE; 2014.'
apa: 'Mischkalla, F., & Müller, W. (2014). Architectural Low-Power Design Using
Transaction-Based System Simulation. Embedded Computer Systems: Architectures,
Modeling, and Simulation (SAMOS XIV).'
bibtex: '@inproceedings{Mischkalla_Müller_2014, title={Architectural Low-Power Design
Using Transaction-Based System Simulation}, booktitle={Embedded Computer Systems:
Architectures, Modeling, and Simulation (SAMOS XIV)}, publisher={IEEE}, author={Mischkalla,
Fabian and Müller, Wolfgang}, year={2014} }'
chicago: 'Mischkalla, Fabian, and Wolfgang Müller. “Architectural Low-Power Design
Using Transaction-Based System Simulation.” In Embedded Computer Systems: Architectures,
Modeling, and Simulation (SAMOS XIV). IEEE, 2014.'
ieee: F. Mischkalla and W. Müller, “Architectural Low-Power Design Using Transaction-Based
System Simulation,” Greece, Sep. 2014, IEEE, 2014.
mla: 'Mischkalla, Fabian, and Wolfgang Müller. “Architectural Low-Power Design Using
Transaction-Based System Simulation.” Embedded Computer Systems: Architectures,
Modeling, and Simulation (SAMOS XIV), IEEE, 2014.'
short: 'F. Mischkalla, W. Müller, in: Embedded Computer Systems: Architectures,
Modeling, and Simulation (SAMOS XIV), IEEE, 2014.'
conference:
location: Greece, Sep. 2014, IEEE
date_created: 2021-09-29T12:06:12Z
date_updated: 2023-01-16T11:29:24Z
department:
- _id: '58'
language:
- iso: eng
publication: 'Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS
XIV)'
publisher: IEEE
status: public
title: Architectural Low-Power Design Using Transaction-Based System Simulation
type: conference
user_id: '5786'
year: '2014'
...
---
_id: '25146'
author:
- first_name: M. tech. Mabel Mary
full_name: Joy, M. tech. Mabel Mary
last_name: Joy
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Franz-Josef
full_name: Rammig, Franz-Josef
last_name: Rammig
citation:
ama: 'Joy M tech. MM, Müller W, Rammig F-J. Source code annotated memory leak detection
for soft real time embedded systems with resource constraints. In: 12th IEEE
International Conference on Embedded Computing. ; 2014.'
apa: Joy, M. tech. M. M., Müller, W., & Rammig, F.-J. (2014). Source code annotated
memory leak detection for soft real time embedded systems with resource constraints.
12th IEEE International Conference on Embedded Computing.
bibtex: '@inproceedings{Joy_Müller_Rammig_2014, title={Source code annotated memory
leak detection for soft real time embedded systems with resource constraints},
booktitle={12th IEEE International conference on Embedded Computing}, author={Joy,
M. tech. Mabel Mary and Müller, Wolfgang and Rammig, Franz-Josef}, year={2014}
}'
chicago: Joy, M. tech. Mabel Mary, Wolfgang Müller, and Franz-Josef Rammig. “Source
Code Annotated Memory Leak Detection for Soft Real Time Embedded Systems with
Resource Constraints.” In 12th IEEE International Conference on Embedded Computing,
2014.
ieee: M. tech. M. M. Joy, W. Müller, and F.-J. Rammig, “Source code annotated memory
leak detection for soft real time embedded systems with resource constraints,”
2014.
mla: Joy, M. tech. Mabel Mary, et al. “Source Code Annotated Memory Leak Detection
for Soft Real Time Embedded Systems with Resource Constraints.” 12th IEEE International
Conference on Embedded Computing, 2014.
short: 'M. tech. M.M. Joy, W. Müller, F.-J. Rammig, in: 12th IEEE International
Conference on Embedded Computing, 2014.'
date_created: 2021-09-30T07:18:43Z
date_updated: 2023-01-16T11:36:02Z
department:
- _id: '58'
language:
- iso: eng
publication: 12th IEEE International conference on Embedded Computing
status: public
title: Source code annotated memory leak detection for soft real time embedded systems
with resource constraints
type: conference
user_id: '5786'
year: '2014'
...
---
_id: '25144'
author:
- first_name: Fabian
full_name: Mischkalla, Fabian
last_name: Mischkalla
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Mischkalla F, Müller W. Advanced SoC Virtual Prototyping for System-Level
Power Planning and Validation. In: PATMOS 2014. ; 2014.'
apa: Mischkalla, F., & Müller, W. (2014). Advanced SoC Virtual Prototyping for
System-Level Power Planning and Validation. PATMOS 2014.
bibtex: '@inproceedings{Mischkalla_Müller_2014, place={Palma de Mallorca, Spain},
title={Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation},
booktitle={PATMOS 2014}, author={Mischkalla, Fabian and Müller, Wolfgang}, year={2014}
}'
chicago: Mischkalla, Fabian, and Wolfgang Müller. “Advanced SoC Virtual Prototyping
for System-Level Power Planning and Validation.” In PATMOS 2014. Palma
de Mallorca, Spain, 2014.
ieee: F. Mischkalla and W. Müller, “Advanced SoC Virtual Prototyping for System-Level
Power Planning and Validation,” 2014.
mla: Mischkalla, Fabian, and Wolfgang Müller. “Advanced SoC Virtual Prototyping
for System-Level Power Planning and Validation.” PATMOS 2014, 2014.
short: 'F. Mischkalla, W. Müller, in: PATMOS 2014, Palma de Mallorca, Spain, 2014.'
date_created: 2021-09-30T07:13:17Z
date_updated: 2023-01-16T11:28:39Z
department:
- _id: '58'
language:
- iso: eng
place: Palma de Mallorca, Spain
publication: PATMOS 2014
status: public
title: Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation
type: conference
user_id: '5786'
year: '2014'
...
---
_id: '36918'
abstract:
- lang: eng
text: This paper presents an advanced eight levels spanning SystemC based virtual
platform methodology and framework - referred to as HeroeS 3 - providing smooth
application to platform mapping and continuous co-refinement of a virtual prototype
with its physical environment model. For heterogeneity support, various SystemC
extensions are combined covering continuous/discrete models of computation and
different communication abstractions, such as analog mixed-signal models, abstract
RTOS/HAL/middleware models, TLM bus models, and QEMU wrappers. We enable dependability
assessment by Fault Effect Modeling (FEM) at the virtual prototype in order to
avoid risking physical injury or damage. Also, simulation results are deterministic
and can be evaluated interactively or offline. We apply FEM to both the physical
environment model and the different abstractions of the virtual prototype. Currently,
we focus on sensor failures and application control flow errors.
author:
- first_name: Markus
full_name: Becker, Markus
last_name: Becker
- first_name: Christoph
full_name: Kuznik, Christoph
last_name: Kuznik
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Becker M, Kuznik C, Müller W. Fault Effect Modeling in a Heterogeneous SystemC
Based Virtual Platform Framework for Cyber Physical Systems. In: IEEE; 2014. doi:10.1109/ICCPS.2014.6843726'
apa: Becker, M., Kuznik, C., & Müller, W. (2014). Fault Effect Modeling in
a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems.
ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS), Berlin. https://doi.org/10.1109/ICCPS.2014.6843726
bibtex: '@inproceedings{Becker_Kuznik_Müller_2014, place={Berlin}, title={Fault
Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for
Cyber Physical Systems}, DOI={10.1109/ICCPS.2014.6843726},
publisher={IEEE}, author={Becker, Markus and Kuznik, Christoph and Müller, Wolfgang},
year={2014} }'
chicago: 'Becker, Markus, Christoph Kuznik, and Wolfgang Müller. “Fault Effect Modeling
in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical
Systems.” Berlin: IEEE, 2014. https://doi.org/10.1109/ICCPS.2014.6843726.'
ieee: 'M. Becker, C. Kuznik, and W. Müller, “Fault Effect Modeling in a Heterogeneous
SystemC Based Virtual Platform Framework for Cyber Physical Systems,” presented
at the ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS), Berlin,
2014, doi: 10.1109/ICCPS.2014.6843726.'
mla: Becker, Markus, et al. Fault Effect Modeling in a Heterogeneous SystemC
Based Virtual Platform Framework for Cyber Physical Systems. IEEE, 2014, doi:10.1109/ICCPS.2014.6843726.
short: 'M. Becker, C. Kuznik, W. Müller, in: IEEE, Berlin, 2014.'
conference:
location: Berlin
name: ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS)
date_created: 2023-01-16T11:57:08Z
date_updated: 2023-01-16T11:57:22Z
department:
- _id: '58'
doi: 10.1109/ICCPS.2014.6843726
keyword:
- Computational modeling
- Finite element analysis
- Prototypes
- Abstracts
- Software
- Fault tolerance
- Fault tolerant systems
language:
- iso: eng
place: Berlin
publisher: IEEE
status: public
title: Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework
for Cyber Physical Systems
type: conference
user_id: '5786'
year: '2014'
...
---
_id: '36917'
abstract:
- lang: eng
text: The ever-increasing complexity of heterogeneous electronic systems demand
for intensified abstraction and automation efforts to improve design, verification
and validation productivity, especially in earlier phases of system engineering.
Within the verification activity various metrics can be applied to determine functional
correctness or the overall progress. Here, a supporting verification methodology
defining high-level verification planning down to the actual metric code development
is essential. Moreover, an advanced assistance for the designer, such as a tooling
infrastructure to automatize and accelerate the metric code implementation, is
needed to minimize the influence of errorprone manual coding. In this article
we present a single-source verification metric code-generation methodology for
improved coverage automation. We determine (i) a suitable metric model for model-based
capture of verification metrics as well as (ii) an assisted model-based processing
and generation flow of the verification environment and metric skeletons. We apply
our method to a SystemC case-study, in doing so, targeting metric code implementation
productivity and consistency enhancement.
author:
- first_name: Christoph
full_name: Kuznik, Christoph
last_name: Kuznik
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Gilles Bertrand
full_name: Defo, Gilles Bertrand
last_name: Defo
citation:
ama: 'Kuznik C, Müller W, Defo GB. An Assisted Single Source Verification Metric
Model Code Generation Methodology. In: ; 2014.'
apa: Kuznik, C., Müller, W., & Defo, G. B. (2014). An Assisted Single Source
Verification Metric Model Code Generation Methodology. Proceedings of the
Electronic System Level Synthesis Conference (ESLSyn).
bibtex: '@inproceedings{Kuznik_Müller_Defo_2014, place={San Francisco, USA}, title={An
Assisted Single Source Verification Metric Model Code Generation Methodology},
author={Kuznik, Christoph and Müller, Wolfgang and Defo, Gilles Bertrand}, year={2014}
}'
chicago: Kuznik, Christoph, Wolfgang Müller, and Gilles Bertrand Defo. “An Assisted
Single Source Verification Metric Model Code Generation Methodology.” San Francisco,
USA, 2014.
ieee: C. Kuznik, W. Müller, and G. B. Defo, “An Assisted Single Source Verification
Metric Model Code Generation Methodology,” presented at the Proceedings of the
Electronic System Level Synthesis Conference (ESLSyn), 2014.
mla: Kuznik, Christoph, et al. An Assisted Single Source Verification Metric
Model Code Generation Methodology. 2014.
short: 'C. Kuznik, W. Müller, G.B. Defo, in: San Francisco, USA, 2014.'
conference:
name: Proceedings of the Electronic System Level Synthesis Conference (ESLSyn)
date_created: 2023-01-16T11:43:50Z
date_updated: 2023-01-16T11:44:06Z
department:
- _id: '58'
keyword:
- System Design
- Verification
language:
- iso: eng
place: San Francisco, USA
status: public
title: An Assisted Single Source Verification Metric Model Code Generation Methodology
type: conference
user_id: '5786'
year: '2014'
...
---
_id: '25166'
abstract:
- lang: eng
text: Zur Sicherstellung hoher Zuverlässigkeits- und Fehlertoleranzwerte von Schaltungen
und ganzen Systemen finden vermehrt Test- und Verifikationsmethoden Anwendung
die einen virtuellen Prototypen (VP) des Systems bereits frühzeitig im Entwurfsablauf
einem Stresstest unterziehen. Hierbei werden speziell für die Domäne relevante
Fehlerinjektoren verwendet (Digital, Mixed-Signal, Mechanik) die anhand von Fehlermodellen
geeignete Testfälle erzeugen und in das System über Stimuli bzw. direkt injizieren.
Jede effektive Anwendung einer Methode bedingt jedoch auch das Vorhandensein einer
zugrundeliegenden Methodik. In diesem Beitrag wird die System Verification Methodology
(SVM) vorgestellt werden, eine universell einsetzbare und erweiterbare Infrastruktur
zur Beschreibung von Testumgebungen auf Basis der SystemC Sprache und Simulationskernels.
author:
- first_name: Christoph
full_name: Kuznik, Christoph
last_name: Kuznik
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Kuznik C, Müller W. Modellierung effizienter Stresstest-Umgebungen für virtuelle
Prototypen mit SVM. In: 26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen. ; 2014.'
apa: Kuznik, C., & Müller, W. (2014). Modellierung effizienter Stresstest-Umgebungen
für virtuelle Prototypen mit SVM. 26. ITG / GI / GMM Workshop Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen.
bibtex: '@inproceedings{Kuznik_Müller_2014, title={Modellierung effizienter Stresstest-Umgebungen
für virtuelle Prototypen mit SVM}, booktitle={26. ITG / GI / GMM Workshop Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen}, author={Kuznik, Christoph and
Müller, Wolfgang}, year={2014} }'
chicago: Kuznik, Christoph, and Wolfgang Müller. “Modellierung effizienter Stresstest-Umgebungen
für virtuelle Prototypen mit SVM.” In 26. ITG / GI / GMM Workshop Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen, 2014.
ieee: C. Kuznik and W. Müller, “Modellierung effizienter Stresstest-Umgebungen für
virtuelle Prototypen mit SVM,” 2014.
mla: Kuznik, Christoph, and Wolfgang Müller. “Modellierung effizienter Stresstest-Umgebungen
für virtuelle Prototypen mit SVM.” 26. ITG / GI / GMM Workshop Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen, 2014.
short: 'C. Kuznik, W. Müller, in: 26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen, 2014.'
date_created: 2021-09-30T10:26:58Z
date_updated: 2023-01-16T11:46:54Z
department:
- _id: '58'
language:
- iso: ger
publication: 26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen
und Systemen
status: public
title: Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit
SVM
type: conference
user_id: '5786'
year: '2014'
...
---
_id: '25163'
author:
- first_name: Christoph
full_name: Kuznik, Christoph
last_name: Kuznik
- first_name: Bertrand Gilles
full_name: Defo, Bertrand Gilles
last_name: Defo
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Kuznik C, Defo BG, Müller W. Semi-automatische Generierung von Überdeckungsmetriken
mittels methodischer Verikationsplan Verarbeitung. In: 17. Workshop Methoden
und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und
Systemen (MBMV 2014) . ; 2014.'
apa: Kuznik, C., Defo, B. G., & Müller, W. (2014). Semi-automatische Generierung
von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung. 17.
Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV 2014) .
bibtex: '@inproceedings{Kuznik_Defo_Müller_2014, title={Semi-automatische Generierung
von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung}, booktitle={17.
Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV 2014) }, author={Kuznik, Christoph and Defo,
Bertrand Gilles and Müller, Wolfgang}, year={2014} }'
chicago: Kuznik, Christoph, Bertrand Gilles Defo, and Wolfgang Müller. “Semi-automatische
Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung.”
In 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV 2014) , 2014.
ieee: C. Kuznik, B. G. Defo, and W. Müller, “Semi-automatische Generierung von Überdeckungsmetriken
mittels methodischer Verikationsplan Verarbeitung,” 2014.
mla: Kuznik, Christoph, et al. “Semi-automatische Generierung von Überdeckungsmetriken
mittels methodischer Verikationsplan Verarbeitung.” 17. Workshop Methoden und
Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
(MBMV 2014) , 2014.
short: 'C. Kuznik, B.G. Defo, W. Müller, in: 17. Workshop Methoden und Beschreibungssprachen
zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) , 2014.'
date_created: 2021-09-30T10:11:13Z
date_updated: 2023-01-16T11:45:51Z
department:
- _id: '58'
language:
- iso: ger
publication: '17. Workshop Methoden und Beschreibungssprachen zur Modellierung und
Verifikation von Schaltungen und Systemen (MBMV 2014) '
status: public
title: Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer
Verikationsplan Verarbeitung
type: conference
user_id: '5786'
year: '2014'
...
---
_id: '25151'
author:
- first_name: Christoph
full_name: Kuznik, Christoph
last_name: Kuznik
- first_name: Bertrand Gilles
full_name: Defo, Bertrand Gilles
last_name: Defo
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: Kuznik C, Defo BG, Müller W. An Assisted Single Source Verification Metric
Model Code Generation Methodology. Electronic System Level Synthesis Conference
(ESLSyn). Published online 2014.
apa: Kuznik, C., Defo, B. G., & Müller, W. (2014). An Assisted Single Source
Verification Metric Model Code Generation Methodology. Electronic System Level
Synthesis Conference (ESLSyn).
bibtex: '@article{Kuznik_Defo_Müller_2014, title={An Assisted Single Source Verification
Metric Model Code Generation Methodology}, journal={Electronic System Level Synthesis
Conference (ESLSyn)}, author={Kuznik, Christoph and Defo, Bertrand Gilles and
Müller, Wolfgang}, year={2014} }'
chicago: Kuznik, Christoph, Bertrand Gilles Defo, and Wolfgang Müller. “An Assisted
Single Source Verification Metric Model Code Generation Methodology.” Electronic
System Level Synthesis Conference (ESLSyn), 2014.
ieee: C. Kuznik, B. G. Defo, and W. Müller, “An Assisted Single Source Verification
Metric Model Code Generation Methodology,” Electronic System Level Synthesis
Conference (ESLSyn), 2014.
mla: Kuznik, Christoph, et al. “An Assisted Single Source Verification Metric Model
Code Generation Methodology.” Electronic System Level Synthesis Conference
(ESLSyn), 2014.
short: C. Kuznik, B.G. Defo, W. Müller, Electronic System Level Synthesis Conference
(ESLSyn) (2014).
date_created: 2021-09-30T08:05:38Z
date_updated: 2023-01-16T11:44:46Z
department:
- _id: '58'
language:
- iso: eng
publication: Electronic System Level Synthesis Conference (ESLSyn)
status: public
title: An Assisted Single Source Verification Metric Model Code Generation Methodology
type: journal_article
user_id: '5786'
year: '2014'
...
---
_id: '24310'
abstract:
- lang: eng
text: A millimeter wave frequency mixed-signal design of a 1-tap half-rate look-ahead
decision feedback equalizer for 80 Gb/s short-reach optical communication systems
is presented. On-wafer tests are developed to determine the maximum operating
bit rate of the equalizer. Results are also presented for intersymbol interference
mitigation at 80 Gb/s for a 20 GHz bandwidth-limited channel. Further improvements
on the architecture of the 80 Gb/s equalizer are discussed and used in the design
and on-wafer measurement of a 110 Gb/s equalizer. The equalizers are designed
in a 0.13 μm SiGe:C BiCMOS technology. The 80 and 110 Gb/s versions dissipate
4 and 5.75 W, respectively and occupy 2 and 2.56 mm 2 , respectively.
author:
- first_name: Ahmed
full_name: Awny, Ahmed
last_name: Awny
- first_name: Lothar
full_name: Möller, Lothar
last_name: Möller
- first_name: Josef
full_name: Junio, Josef
last_name: Junio
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
orcid: https://orcid.org/0000-0002-5950-6618
- first_name: Andreas
full_name: Thiede, Andreas
id: '538'
last_name: Thiede
citation:
ama: Awny A, Möller L, Junio J, Scheytt C, Thiede A. Design and Measurement Techniques
for an 80 Gb/s 1-Tap Decision Feedback Equalizer. IEEE JOURNAL OF SOLID-STATE
CIRCUITS. 2014;Vol.49(No.2):452-470. doi:10.1109/JSSC.2013.2285385
apa: Awny, A., Möller, L., Junio, J., Scheytt, C., & Thiede, A. (2014). Design
and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer. IEEE
JOURNAL OF SOLID-STATE CIRCUITS, Vol.49(No.2), 452–470. https://doi.org/10.1109/JSSC.2013.2285385
bibtex: '@article{Awny_Möller_Junio_Scheytt_Thiede_2014, title={Design and Measurement
Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer}, volume={Vol.49},
DOI={10.1109/JSSC.2013.2285385},
number={No.2}, journal={IEEE JOURNAL OF SOLID-STATE CIRCUITS}, author={Awny, Ahmed
and Möller, Lothar and Junio, Josef and Scheytt, Christoph and Thiede, Andreas},
year={2014}, pages={452–470} }'
chicago: 'Awny, Ahmed, Lothar Möller, Josef Junio, Christoph Scheytt, and Andreas
Thiede. “Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback
Equalizer.” IEEE JOURNAL OF SOLID-STATE CIRCUITS Vol.49, no. No.2 (2014):
452–70. https://doi.org/10.1109/JSSC.2013.2285385.'
ieee: 'A. Awny, L. Möller, J. Junio, C. Scheytt, and A. Thiede, “Design and Measurement
Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer,” IEEE JOURNAL
OF SOLID-STATE CIRCUITS, vol. Vol.49, no. No.2, pp. 452–470, 2014, doi: 10.1109/JSSC.2013.2285385.'
mla: Awny, Ahmed, et al. “Design and Measurement Techniques for an 80 Gb/s 1-Tap
Decision Feedback Equalizer.” IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol.
Vol.49, no. No.2, 2014, pp. 452–70, doi:10.1109/JSSC.2013.2285385.
short: A. Awny, L. Möller, J. Junio, C. Scheytt, A. Thiede, IEEE JOURNAL OF SOLID-STATE
CIRCUITS Vol.49 (2014) 452–470.
date_created: 2021-09-14T07:06:58Z
date_updated: 2023-01-25T11:03:36Z
department:
- _id: '58'
- _id: '51'
doi: 10.1109/JSSC.2013.2285385
issue: No.2
language:
- iso: eng
page: 452-470
publication: IEEE JOURNAL OF SOLID-STATE CIRCUITS
publication_identifier:
eissn:
- 1558-173X
related_material:
link:
- relation: confirmation
url: https://ieeexplore.ieee.org/document/6648461
status: public
title: Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer
type: journal_article
user_id: '158'
volume: Vol.49
year: '2014'
...
---
_id: '34585'
abstract:
- lang: eng
text: In this paper, we present an efficient approach to virtual platform modeling
for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666
Standard SystemC simulation. For evaluation we consider Infineon's recently introduced
AURIX processor family as a target platform, which utilizes multiple CPU cores
operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals.
For SoC prototyping, we integrate the fast and open instruction accurate QEMU
software emulator with the TLMu library for SystemC co-verification. This article
reports our most recent efforts of the implementation of the TriCore instruction
set for QEMU. The experimental results demonstrate the functional correctness
and performance of our TriCore implementation.
author:
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Bernd
full_name: Messidat, Bernd
last_name: Messidat
- first_name: Markus
full_name: Becker, Markus
last_name: Becker
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: J. Christoph
full_name: Scheytt, J. Christoph
id: '37144'
last_name: Scheytt
orcid: https://orcid.org/0000-0002-5950-6618
citation:
ama: 'Koppelmann B, Messidat B, Becker M, Müller W, Scheytt JC. Fast and Open Virtual
Platforms for TriCore-based SoCs Using QEMU. In: Proceedings of the Design
and Verification Conference Europe (DVCON Europe). ; 2014.'
apa: Koppelmann, B., Messidat, B., Becker, M., Müller, W., & Scheytt, J. C.
(2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. Proceedings
of the Design and Verification Conference Europe (DVCON Europe).
bibtex: '@inproceedings{Koppelmann_Messidat_Becker_Müller_Scheytt_2014, place={München},
title={Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}, booktitle={Proceedings
of the Design and Verification Conference Europe (DVCON Europe)}, author={Koppelmann,
Bastian and Messidat, Bernd and Becker, Markus and Müller, Wolfgang and Scheytt,
J. Christoph}, year={2014} }'
chicago: Koppelmann, Bastian, Bernd Messidat, Markus Becker, Wolfgang Müller, and
J. Christoph Scheytt. “Fast and Open Virtual Platforms for TriCore-Based SoCs
Using QEMU.” In Proceedings of the Design and Verification Conference Europe
(DVCON Europe). München, 2014.
ieee: B. Koppelmann, B. Messidat, M. Becker, W. Müller, and J. C. Scheytt, “Fast
and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” 2014.
mla: Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based
SoCs Using QEMU.” Proceedings of the Design and Verification Conference Europe
(DVCON Europe), 2014.
short: 'B. Koppelmann, B. Messidat, M. Becker, W. Müller, J.C. Scheytt, in: Proceedings
of the Design and Verification Conference Europe (DVCON Europe), München, 2014.'
date_created: 2022-12-20T10:48:25Z
date_updated: 2023-02-01T08:12:02Z
department:
- _id: '58'
keyword:
- System Design
- Verification
language:
- iso: eng
place: München
publication: Proceedings of the Design and Verification Conference Europe (DVCON Europe)
status: public
title: Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU
type: conference
user_id: '15931'
year: '2014'
...
---
_id: '34583'
abstract:
- lang: eng
text: In this paper, we present an efficient approach to virtual platform modeling
for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666
Standard SystemC simulation. For evaluation we consider Infineon's recently introduced
AURIX processor family as a target platform, which utilizes multiple CPU cores
operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals.
For SoC prototyping, we integrate the fast and open instruction accurate QEMU
software emulator with the TLMu library for SystemC co-verification. This article
reports our most recent efforts of the implementation of the TriCore instruction
set for QEMU. The experimental results demonstrate the functional correctness
and performance of our TriCore implementation.
author:
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Bernd
full_name: Messidat, Bernd
last_name: Messidat
- first_name: Christoph
full_name: Kuznik, Christoph
last_name: Kuznik
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Markus
full_name: Becker, Markus
last_name: Becker
- first_name: J. Christoph
full_name: Scheytt, J. Christoph
id: '37144'
last_name: Scheytt
orcid: https://orcid.org/0000-0002-5950-6618
citation:
ama: 'Koppelmann B, Messidat B, Kuznik C, Müller W, Becker M, Scheytt JC. Fast and
Open Virtual Platforms for TriCore-based SoCs Using QEMU. In: Proceedings of
the Design and Verification Conference Europe (DVCON Europe). ; 2014.'
apa: Koppelmann, B., Messidat, B., Kuznik, C., Müller, W., Becker, M., & Scheytt,
J. C. (2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU.
Proceedings of the Design and Verification Conference Europe (DVCON Europe).
bibtex: '@inproceedings{Koppelmann_Messidat_Kuznik_Müller_Becker_Scheytt_2014, place={München},
title={Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}, booktitle={Proceedings
of the Design and Verification Conference Europe (DVCON Europe)}, author={Koppelmann,
Bastian and Messidat, Bernd and Kuznik, Christoph and Müller, Wolfgang and Becker,
Markus and Scheytt, J. Christoph}, year={2014} }'
chicago: Koppelmann, Bastian, Bernd Messidat, Christoph Kuznik, Wolfgang Müller,
Markus Becker, and J. Christoph Scheytt. “Fast and Open Virtual Platforms for
TriCore-Based SoCs Using QEMU.” In Proceedings of the Design and Verification
Conference Europe (DVCON Europe). München, 2014.
ieee: B. Koppelmann, B. Messidat, C. Kuznik, W. Müller, M. Becker, and J. C. Scheytt,
“Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” 2014.
mla: Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based
SoCs Using QEMU.” Proceedings of the Design and Verification Conference Europe
(DVCON Europe), 2014.
short: 'B. Koppelmann, B. Messidat, C. Kuznik, W. Müller, M. Becker, J.C. Scheytt,
in: Proceedings of the Design and Verification Conference Europe (DVCON Europe),
München, 2014.'
date_created: 2022-12-20T10:45:38Z
date_updated: 2025-02-26T14:42:18Z
department:
- _id: '58'
keyword:
- System Design
- Verification
language:
- iso: eng
place: München
publication: Proceedings of the Design and Verification Conference Europe (DVCON Europe)
status: public
title: Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU
type: conference
user_id: '16243'
year: '2014'
...
---
_id: '24356'
abstract:
- lang: eng
text: A fully integrated six-port receiver front-end at 120 GHz center frequency
including a low-noise-amplifier, a passive six-port network, a VCO, and four direct
converters is presented in this publication. The overall architecture of the designed
six-port receiver is analyzed and fundamental theory of the receiver given. The
design of the six-port building blocks is described and measurement results are
presented. All circuits have been fabricated in a 0.13μm 300-GHz f T SiGe BiCMOS
technology. The fully integrated receiver consumes 85.9 rnA from a 3.3-V supply
and occupies an area of 1.03mm 2 . The receiver includes a VCO with a center frequency
of 117.15 GHz, a tuning range of 2.7 GHz, and a phase noise of -86 dBc/Hz at 1
MHz offset. The LNA shows a gain of 12 dB, a 3-dB bandwidth of 30 GHz at a power
consumption of 9.2 rnA. The six-port core has a conversion gain of 3.6 dB, a P
1dB of -12 dBm, and a power consumption of 28 rnA. The overall receiver shows
a conversion gain of 2.4 dB at 120 GHz and P 1dB of -17 dBm.
author:
- first_name: Benjamin
full_name: Laemmle, Benjamin
last_name: Laemmle
- first_name: Klaus
full_name: Schmalz, Klaus
last_name: Schmalz
- first_name: Johannes
full_name: Borngräber, Johannes
last_name: Borngräber
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
- first_name: Robert
full_name: Weigel, Robert
last_name: Weigel
- first_name: Alexander
full_name: Koelpin, Alexander
last_name: Koelpin
- first_name: Dietmar
full_name: Kissinger, Dietmar
last_name: Kissinger
citation:
ama: 'Laemmle B, Schmalz K, Borngräber J, et al. A fully integrated 120-GHz six-port
receiver front-end in a 130-nm SiGe BiCMOS technology. In: Silicon Monolithic
Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On.
; 2013. doi:10.1109/SiRF.2013.6489455'
apa: Laemmle, B., Schmalz, K., Borngräber, J., Scheytt, C., Weigel, R., Koelpin,
A., & Kissinger, D. (2013). A fully integrated 120-GHz six-port receiver front-end
in a 130-nm SiGe BiCMOS technology. Silicon Monolithic Integrated Circuits
in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On. https://doi.org/10.1109/SiRF.2013.6489455
bibtex: '@inproceedings{Laemmle_Schmalz_Borngräber_Scheytt_Weigel_Koelpin_Kissinger_2013,
title={A fully integrated 120-GHz six-port receiver front-end in a 130-nm SiGe
BiCMOS technology}, DOI={10.1109/SiRF.2013.6489455},
booktitle={Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE
13th Topical Meeting on}, author={Laemmle, Benjamin and Schmalz, Klaus and Borngräber,
Johannes and Scheytt, Christoph and Weigel, Robert and Koelpin, Alexander and
Kissinger, Dietmar}, year={2013} }'
chicago: Laemmle, Benjamin, Klaus Schmalz, Johannes Borngräber, Christoph Scheytt,
Robert Weigel, Alexander Koelpin, and Dietmar Kissinger. “A Fully Integrated 120-GHz
Six-Port Receiver Front-End in a 130-Nm SiGe BiCMOS Technology.” In Silicon
Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting
On, 2013. https://doi.org/10.1109/SiRF.2013.6489455.
ieee: 'B. Laemmle et al., “A fully integrated 120-GHz six-port receiver front-end
in a 130-nm SiGe BiCMOS technology,” 2013, doi: 10.1109/SiRF.2013.6489455.'
mla: Laemmle, Benjamin, et al. “A Fully Integrated 120-GHz Six-Port Receiver Front-End
in a 130-Nm SiGe BiCMOS Technology.” Silicon Monolithic Integrated Circuits
in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On, 2013, doi:10.1109/SiRF.2013.6489455.
short: 'B. Laemmle, K. Schmalz, J. Borngräber, C. Scheytt, R. Weigel, A. Koelpin,
D. Kissinger, in: Silicon Monolithic Integrated Circuits in RF Systems (SiRF),
2013 IEEE 13th Topical Meeting On, 2013.'
conference:
end_date: 2013.01.23
start_date: 2013.01.21
date_created: 2021-09-14T09:22:35Z
date_updated: 2022-02-17T09:02:41Z
department:
- _id: '58'
doi: 10.1109/SiRF.2013.6489455
language:
- iso: eng
publication: Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE
13th Topical Meeting on
publication_identifier:
eisbn:
- 978-1-4673-1553-1
related_material:
link:
- relation: confirmation
url: https://ieeexplore.ieee.org/document/6489455
status: public
title: A fully integrated 120-GHz six-port receiver front-end in a 130-nm SiGe BiCMOS
technology
type: conference
user_id: '15931'
year: '2013'
...
---
_id: '24355'
abstract:
- lang: eng
text: Impulse-radio ultra-wideband systems (IR-UWB) provide short-range wireless
communication and precise localization simultaneously. Especially non-coherent
IR-UWB reduces the system complexity which enables the design of low-power receivers.
This paper presents an integrating digitizer which integrates rectified baseband
pulses of an IR-UWB signal and provides the digitized data to the digital baseband
of the receiver. The integrator is composed of two time-interleaved (TI) operational
amplifiers with capacitive feedback. With this structure, the integrator can be
periodically reset without introducing a dead time between two integration periods.
The analog-to-digital conversion is performed by a 6 bit 62.4 MS/s successive
approximation register analog-to-digital converter (SAR ADC). The integrating
digitizer chip is realized in a 250 nm SiGe:C BiCMOS technology from IHP.
author:
- first_name: Johannes
full_name: Digel, Johannes
last_name: Digel
- first_name: Michelangelo
full_name: Masini, Michelangelo
last_name: Masini
- first_name: Markus
full_name: Grözing, Markus
last_name: Grözing
- first_name: Manfred
full_name: Berroth, Manfred
last_name: Berroth
- first_name: Gunter
full_name: Fischer, Gunter
last_name: Fischer
- first_name: Sonom
full_name: Olonbayar, Sonom
last_name: Olonbayar
- first_name: Hans
full_name: Gustat, Hans
last_name: Gustat
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
citation:
ama: 'Digel J, Masini M, Grözing M, et al. Integrator and digitizer for a non-coherent
IR-UWB receiver. In: Silicon Monolithic Integrated Circuits in RF Systems (SiRF),
2013 IEEE 13th Topical Meeting On. ; 2013:93-95. doi:10.1109/SiRF.2013.6489443'
apa: Digel, J., Masini, M., Grözing, M., Berroth, M., Fischer, G., Olonbayar, S.,
Gustat, H., & Scheytt, C. (2013). Integrator and digitizer for a non-coherent
IR-UWB receiver. Silicon Monolithic Integrated Circuits in RF Systems (SiRF),
2013 IEEE 13th Topical Meeting On, 93–95. https://doi.org/10.1109/SiRF.2013.6489443
bibtex: '@inproceedings{Digel_Masini_Grözing_Berroth_Fischer_Olonbayar_Gustat_Scheytt_2013,
title={Integrator and digitizer for a non-coherent IR-UWB receiver}, DOI={10.1109/SiRF.2013.6489443},
booktitle={Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE
13th Topical Meeting on}, author={Digel, Johannes and Masini, Michelangelo and
Grözing, Markus and Berroth, Manfred and Fischer, Gunter and Olonbayar, Sonom
and Gustat, Hans and Scheytt, Christoph}, year={2013}, pages={93–95} }'
chicago: Digel, Johannes, Michelangelo Masini, Markus Grözing, Manfred Berroth,
Gunter Fischer, Sonom Olonbayar, Hans Gustat, and Christoph Scheytt. “Integrator
and Digitizer for a Non-Coherent IR-UWB Receiver.” In Silicon Monolithic Integrated
Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On, 93–95, 2013.
https://doi.org/10.1109/SiRF.2013.6489443.
ieee: 'J. Digel et al., “Integrator and digitizer for a non-coherent IR-UWB
receiver,” in Silicon Monolithic Integrated Circuits in RF Systems (SiRF),
2013 IEEE 13th Topical Meeting on, 2013, pp. 93–95, doi: 10.1109/SiRF.2013.6489443.'
mla: Digel, Johannes, et al. “Integrator and Digitizer for a Non-Coherent IR-UWB
Receiver.” Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013
IEEE 13th Topical Meeting On, 2013, pp. 93–95, doi:10.1109/SiRF.2013.6489443.
short: 'J. Digel, M. Masini, M. Grözing, M. Berroth, G. Fischer, S. Olonbayar, H.
Gustat, C. Scheytt, in: Silicon Monolithic Integrated Circuits in RF Systems (SiRF),
2013 IEEE 13th Topical Meeting On, 2013, pp. 93–95.'
conference:
end_date: 2013.01.23
start_date: 2013.01.21
date_created: 2021-09-14T09:22:33Z
date_updated: 2022-02-17T09:01:16Z
department:
- _id: '58'
doi: 10.1109/SiRF.2013.6489443
language:
- iso: eng
page: 93-95
publication: Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE
13th Topical Meeting on
publication_identifier:
eisbn:
- 978-1-4673-1553-1
related_material:
link:
- relation: confirmation
url: https://ieeexplore.ieee.org/document/6489443
status: public
title: Integrator and digitizer for a non-coherent IR-UWB receiver
type: conference
user_id: '15931'
year: '2013'
...
---
_id: '24353'
abstract:
- lang: eng
text: This paper presents an integrated mixed-signal 120GHz FMCW/CW radar chipset
in a 0.13μm SiGe BiCMOS technology. It features on-chip MMW built-in-self-test
(BIST) circuits, a harmonic transceiver, software linearization (SWL) circuits
and a digital interface. This chipset has been tested in a low-cost package, where
the antennas are integrated. Above 100GHz, our transceiver has achieved state-ofthe-art
integration level and receiver linearity, and DC power consumption.
author:
- first_name: Yaoming
full_name: Sun, Yaoming
last_name: Sun
- first_name: Miroslav
full_name: Marinkovic, Miroslav
last_name: Marinkovic
- first_name: Gunter
full_name: Fischer, Gunter
last_name: Fischer
- first_name: Wolfgang
full_name: Winkler, Wolfgang
last_name: Winkler
- first_name: Wojciech
full_name: Debski, Wojciech
last_name: Debski
- first_name: Stefan
full_name: Beer, Stefan
last_name: Beer
- first_name: Thomas
full_name: Zwick, Thomas
last_name: Zwick
- first_name: Mekdes Gebresilassie
full_name: Girma, Mekdes Gebresilassie
last_name: Girma
- first_name: Jürgen
full_name: Hasch, Jürgen
last_name: Hasch
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
citation:
ama: 'Sun Y, Marinkovic M, Fischer G, et al. A low-cost miniature 120GHz SiP FMCW/CW
radar sensor with software linearization. In: Solid-State Circuits Conference
Digest of Technical Papers (ISSCC), 2013 IEEE International. ; 2013:148-149.
doi:10.1109/ISSCC.2013.6487676'
apa: Sun, Y., Marinkovic, M., Fischer, G., Winkler, W., Debski, W., Beer, S., Zwick,
T., Girma, M. G., Hasch, J., & Scheytt, C. (2013). A low-cost miniature 120GHz
SiP FMCW/CW radar sensor with software linearization. Solid-State Circuits
Conference Digest of Technical Papers (ISSCC), 2013 IEEE International, 148–149.
https://doi.org/10.1109/ISSCC.2013.6487676
bibtex: '@inproceedings{Sun_Marinkovic_Fischer_Winkler_Debski_Beer_Zwick_Girma_Hasch_Scheytt_2013,
title={A low-cost miniature 120GHz SiP FMCW/CW radar sensor with software linearization},
DOI={10.1109/ISSCC.2013.6487676},
booktitle={Solid-State Circuits Conference Digest of Technical Papers (ISSCC),
2013 IEEE International}, author={Sun, Yaoming and Marinkovic, Miroslav and Fischer,
Gunter and Winkler, Wolfgang and Debski, Wojciech and Beer, Stefan and Zwick,
Thomas and Girma, Mekdes Gebresilassie and Hasch, Jürgen and Scheytt, Christoph},
year={2013}, pages={148–149} }'
chicago: Sun, Yaoming, Miroslav Marinkovic, Gunter Fischer, Wolfgang Winkler, Wojciech
Debski, Stefan Beer, Thomas Zwick, Mekdes Gebresilassie Girma, Jürgen Hasch, and
Christoph Scheytt. “A Low-Cost Miniature 120GHz SiP FMCW/CW Radar Sensor with
Software Linearization.” In Solid-State Circuits Conference Digest of Technical
Papers (ISSCC), 2013 IEEE International, 148–49, 2013. https://doi.org/10.1109/ISSCC.2013.6487676.
ieee: 'Y. Sun et al., “A low-cost miniature 120GHz SiP FMCW/CW radar sensor
with software linearization,” in Solid-State Circuits Conference Digest of
Technical Papers (ISSCC), 2013 IEEE International, 2013, pp. 148–149, doi:
10.1109/ISSCC.2013.6487676.'
mla: Sun, Yaoming, et al. “A Low-Cost Miniature 120GHz SiP FMCW/CW Radar Sensor
with Software Linearization.” Solid-State Circuits Conference Digest of Technical
Papers (ISSCC), 2013 IEEE International, 2013, pp. 148–49, doi:10.1109/ISSCC.2013.6487676.
short: 'Y. Sun, M. Marinkovic, G. Fischer, W. Winkler, W. Debski, S. Beer, T. Zwick,
M.G. Girma, J. Hasch, C. Scheytt, in: Solid-State Circuits Conference Digest of
Technical Papers (ISSCC), 2013 IEEE International, 2013, pp. 148–149.'
conference:
end_date: 2013.02.21
start_date: 2013.02.17
date_created: 2021-09-14T09:22:31Z
date_updated: 2022-02-17T08:57:43Z
department:
- _id: '58'
doi: 10.1109/ISSCC.2013.6487676
language:
- iso: eng
page: 148-149
publication: Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013
IEEE International
publication_identifier:
eisbn:
- 978-1-4673-4516-3
related_material:
link:
- relation: confirmation
url: https://ieeexplore.ieee.org/document/6487676
status: public
title: A low-cost miniature 120GHz SiP FMCW/CW radar sensor with software linearization
type: conference
user_id: '15931'
year: '2013'
...
---
_id: '24357'
abstract:
- lang: eng
text: Complex integrated 122 and 245 GHz SiGe BiCMOS transceiver ICs as well as
an efficient broadband on-chip antenna are presented. The ICs target radar and
sensing applications for the ISM bands at 122 and 245 GHz. Due to high level of
integration and basic mm-wave self-testing production as well as test cost are
dramatically reduced. Furthermore a compact and efficient on-chip antenna allows
for chip-on-board mounting without RF interfaces.
author:
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
- first_name: Yaoming
full_name: Sun, Yaoming
last_name: Sun
- first_name: Klaus
full_name: Schmalz, Klaus
last_name: Schmalz
- first_name: Yanfei
full_name: Mao, Yanfei
last_name: Mao
- first_name: Ruoyu
full_name: Wang, Ruoyu
last_name: Wang
- first_name: Wojciech
full_name: Debski, Wojciech
last_name: Debski
- first_name: Wolfgang
full_name: Winkler, Wolfgang
last_name: Winkler
citation:
ama: 'Scheytt C, Sun Y, Schmalz K, et al. Towards mm-wave System-On-Chip with integrated
antennas for low-cost 122 and 245 GHz radar sensors. In: Silicon Monolithic
Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On.
; 2013:246-248. doi:10.1109/SiRF.2013.6489494'
apa: Scheytt, C., Sun, Y., Schmalz, K., Mao, Y., Wang, R., Debski, W., & Winkler,
W. (2013). Towards mm-wave System-On-Chip with integrated antennas for low-cost
122 and 245 GHz radar sensors. Silicon Monolithic Integrated Circuits in RF
Systems (SiRF), 2013 IEEE 13th Topical Meeting On, 246–248. https://doi.org/10.1109/SiRF.2013.6489494
bibtex: '@inproceedings{Scheytt_Sun_Schmalz_Mao_Wang_Debski_Winkler_2013, place={Austin
TX}, title={Towards mm-wave System-On-Chip with integrated antennas for low-cost
122 and 245 GHz radar sensors}, DOI={10.1109/SiRF.2013.6489494},
booktitle={Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE
13th Topical Meeting on}, author={Scheytt, Christoph and Sun, Yaoming and Schmalz,
Klaus and Mao, Yanfei and Wang, Ruoyu and Debski, Wojciech and Winkler, Wolfgang},
year={2013}, pages={246–248} }'
chicago: Scheytt, Christoph, Yaoming Sun, Klaus Schmalz, Yanfei Mao, Ruoyu Wang,
Wojciech Debski, and Wolfgang Winkler. “Towards Mm-Wave System-On-Chip with Integrated
Antennas for Low-Cost 122 and 245 GHz Radar Sensors.” In Silicon Monolithic
Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On,
246–48. Austin TX, 2013. https://doi.org/10.1109/SiRF.2013.6489494.
ieee: 'C. Scheytt et al., “Towards mm-wave System-On-Chip with integrated
antennas for low-cost 122 and 245 GHz radar sensors,” in Silicon Monolithic
Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on,
2013, pp. 246–248, doi: 10.1109/SiRF.2013.6489494.'
mla: Scheytt, Christoph, et al. “Towards Mm-Wave System-On-Chip with Integrated
Antennas for Low-Cost 122 and 245 GHz Radar Sensors.” Silicon Monolithic Integrated
Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On, 2013, pp.
246–48, doi:10.1109/SiRF.2013.6489494.
short: 'C. Scheytt, Y. Sun, K. Schmalz, Y. Mao, R. Wang, W. Debski, W. Winkler,
in: Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th
Topical Meeting On, Austin TX, 2013, pp. 246–248.'
conference:
end_date: 2013.01.23
start_date: 2013.01.21
date_created: 2021-09-14T09:22:36Z
date_updated: 2022-02-17T09:03:54Z
department:
- _id: '58'
doi: 10.1109/SiRF.2013.6489494
language:
- iso: eng
page: 246-248
place: Austin TX
publication: Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE
13th Topical Meeting on
publication_identifier:
eisbn:
- 978-1-4673-1553-1
related_material:
link:
- relation: confirmation
url: https://ieeexplore.ieee.org/document/6489494
status: public
title: Towards mm-wave System-On-Chip with integrated antennas for low-cost 122 and
245 GHz radar sensors
type: conference
user_id: '15931'
year: '2013'
...
---
_id: '24354'
abstract:
- lang: eng
text: In this paper, a 6-bit true modular programmable frequency divider with division
ratios ranging from 64 to 127 is reported. It is composed of a divider chain of
6 divide-by-2/3 cells, and ECL stages that are introduced as synchronization circuits
for programming inputs. The synchronization circuits have CMOS input for compatibility
with programming circuits. The stand-alone divider chain is functional up to an
input clock frequency of 49 GHz. The combination of the divider chain with synchronization
circuits is functional up to 44 GHz. The 6 stage divider draws 34 mA current from
a 2.7 V supply. The synchronization circuits draw 30 mA from a 3 V supply. The
circuit is fabricated in a 0.13 μm SiGe BiCMOS technology, and is well suited
for millimeter-wave phase-locked loop (PLL) circuits which require fine frequency
resolution.
author:
- first_name: Arzu
full_name: Ergintav, Arzu
last_name: Ergintav
- first_name: Yaoming
full_name: Sun, Yaoming
last_name: Sun
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
- first_name: Yasar
full_name: Gürbüz, Yasar
last_name: Gürbüz
citation:
ama: 'Ergintav A, Sun Y, Scheytt C, Gürbüz Y. 49 GHz 6-bit programmable divider
in SiGe BiCMOS. In: Silicon Monolithic Integrated Circuits in RF Systems (SiRF),
2013 IEEE 13th Topical Meeting On. ; 2013. doi:10.1109/SiRF.2013.6489451'
apa: Ergintav, A., Sun, Y., Scheytt, C., & Gürbüz, Y. (2013). 49 GHz 6-bit programmable
divider in SiGe BiCMOS. Silicon Monolithic Integrated Circuits in RF Systems
(SiRF), 2013 IEEE 13th Topical Meeting On. https://doi.org/10.1109/SiRF.2013.6489451
bibtex: '@inproceedings{Ergintav_Sun_Scheytt_Gürbüz_2013, title={49 GHz 6-bit programmable
divider in SiGe BiCMOS}, DOI={10.1109/SiRF.2013.6489451},
booktitle={Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE
13th Topical Meeting on}, author={Ergintav, Arzu and Sun, Yaoming and Scheytt,
Christoph and Gürbüz, Yasar}, year={2013} }'
chicago: Ergintav, Arzu, Yaoming Sun, Christoph Scheytt, and Yasar Gürbüz. “49 GHz
6-Bit Programmable Divider in SiGe BiCMOS.” In Silicon Monolithic Integrated
Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On, 2013. https://doi.org/10.1109/SiRF.2013.6489451.
ieee: 'A. Ergintav, Y. Sun, C. Scheytt, and Y. Gürbüz, “49 GHz 6-bit programmable
divider in SiGe BiCMOS,” 2013, doi: 10.1109/SiRF.2013.6489451.'
mla: Ergintav, Arzu, et al. “49 GHz 6-Bit Programmable Divider in SiGe BiCMOS.”
Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th
Topical Meeting On, 2013, doi:10.1109/SiRF.2013.6489451.
short: 'A. Ergintav, Y. Sun, C. Scheytt, Y. Gürbüz, in: Silicon Monolithic Integrated
Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting On, 2013.'
conference:
end_date: 2013.01.23
start_date: 2013.01.21
date_created: 2021-09-14T09:22:32Z
date_updated: 2022-02-17T08:59:40Z
department:
- _id: '58'
doi: 10.1109/SiRF.2013.6489451
language:
- iso: eng
publication: Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE
13th Topical Meeting on
related_material:
link:
- relation: confirmation
url: https://ieeexplore.ieee.org/document/6489451
status: public
title: 49 GHz 6-bit programmable divider in SiGe BiCMOS
type: conference
user_id: '15931'
year: '2013'
...
---
_id: '24361'
abstract:
- lang: eng
text: Two subharmonic receivers for 245 GHz spectroscopy sensor applications in
the 245 GHz ISM band have been proposed. One receiver consists of an 2nd APDP
(antiparallel diode pair) passive SHM (subharmonic mixer), a 120 GHz push-push
VCO with 1/64 divider, and a 120 GHz PA (power amplifier). The other consists
of a single-ended four-stage CB (common base) LNA, an 2 nd APDP passive SHM, an
IF amplifier, a 120 GHz push-push VCO with 1/64 divider, and a 120 GHz PA. The
receivers are fabricated in a SiGe:C BiCMOS technology with f T /f max =300/500
GHz. The measured conversion gain are -17 dB rsp. 10.6 dB at 245 GHz with 3-dB
bandwidths of 13 GHz rsp. 14 GHz, and the single-side band noise figure are 17
dB rsp. 20 dB; the two receivers dissipates a power of 213 mW and 312 mW, respectively.
author:
- first_name: Yanfei
full_name: Mao, Yanfei
last_name: Mao
- first_name: Klaus
full_name: Schmalz, Klaus
last_name: Schmalz
- first_name: Johannes
full_name: Borngräber, Johannes
last_name: Borngräber
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
citation:
ama: 'Mao Y, Schmalz K, Borngräber J, Scheytt C. 245 GHz subharmonic receivers in
SiGe. In: 2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium.
; 2013. doi:10.1109/RFIC.2013.6569533'
apa: Mao, Y., Schmalz, K., Borngräber, J., & Scheytt, C. (2013). 245 GHz subharmonic
receivers in SiGe. 2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium.
https://doi.org/10.1109/RFIC.2013.6569533
bibtex: '@inproceedings{Mao_Schmalz_Borngräber_Scheytt_2013, place={Seattle, Washington},
title={245 GHz subharmonic receivers in SiGe}, DOI={10.1109/RFIC.2013.6569533},
booktitle={2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium}, author={Mao,
Yanfei and Schmalz, Klaus and Borngräber, Johannes and Scheytt, Christoph}, year={2013}
}'
chicago: Mao, Yanfei, Klaus Schmalz, Johannes Borngräber, and Christoph Scheytt.
“245 GHz Subharmonic Receivers in SiGe.” In 2013 IEEE Radio Frequency Integrated
Circuits (RFIC) Symposium. Seattle, Washington, 2013. https://doi.org/10.1109/RFIC.2013.6569533.
ieee: 'Y. Mao, K. Schmalz, J. Borngräber, and C. Scheytt, “245 GHz subharmonic receivers
in SiGe,” 2013, doi: 10.1109/RFIC.2013.6569533.'
mla: Mao, Yanfei, et al. “245 GHz Subharmonic Receivers in SiGe.” 2013 IEEE Radio
Frequency Integrated Circuits (RFIC) Symposium, 2013, doi:10.1109/RFIC.2013.6569533.
short: 'Y. Mao, K. Schmalz, J. Borngräber, C. Scheytt, in: 2013 IEEE Radio Frequency
Integrated Circuits (RFIC) Symposium, Seattle, Washington, 2013.'
conference:
end_date: 2013.06.04
start_date: 2013.06.02
date_created: 2021-09-14T09:22:41Z
date_updated: 2022-02-17T09:14:10Z
department:
- _id: '58'
doi: 10.1109/RFIC.2013.6569533
language:
- iso: eng
place: Seattle, Washington
publication: 2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium
publication_identifier:
eisbn:
- 978-1-4673-6062-3
related_material:
link:
- relation: confirmation
url: https://ieeexplore.ieee.org/document/6569533
status: public
title: 245 GHz subharmonic receivers in SiGe
type: conference
user_id: '15931'
year: '2013'
...