---
_id: '62981'
abstract:
- lang: eng
  text: "Otus is a high-performance computing cluster that was launched in 2025 and
    is operated by the Paderborn Center for Parallel Computing (PC2) at Paderborn
    University in Germany. The system is part of the National High Performance Computing
    (NHR) initiative. Otus complements the previous supercomputer Noctua 2, offering
    approximately twice the computing power while retaining the three node types that
    were characteristic of Noctua 2: 1) CPU compute nodes with different memory capacities,
    2) high-end GPU nodes, and 3) HPC-grade FPGA nodes. On the Top500 list, which
    ranks the 500 most powerful supercomputers in the world, Otus is in position 164
    with the CPU partition and in position 255 with the GPU partition (June 2025).
    On the Green500 list, ranking the 500 most energy-efficient supercomputers in
    the world, Otus is in position 5 with the GPU partition (June 2025).\r\n\r\n\r\nThis
    article provides a comprehensive overview of the system in terms of its hardware,
    software, system integration, and its overall integration into the data center
    building to ensure energy-efficient operation. The article aims to provide unique
    insights for scientists using the system and for other centers operating HPC clusters.
    The article will be continuously updated to reflect the latest system setup and
    measurements. "
author:
- first_name: Sadaf
  full_name: Ehtesabi, Sadaf
  id: '116116'
  last_name: Ehtesabi
- first_name: Manoar
  full_name: Hossain, Manoar
  id: '114619'
  last_name: Hossain
  orcid: https://orcid.org/0000-0002-0737-7981
- first_name: Tobias
  full_name: Kenter, Tobias
  id: '3145'
  last_name: Kenter
- first_name: Andreas
  full_name: Krawinkel, Andreas
  id: '15275'
  last_name: Krawinkel
- first_name: Lukas
  full_name: Ostermann, Lukas
  id: '69976'
  last_name: Ostermann
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Heinrich
  full_name: Riebler, Heinrich
  id: '8961'
  last_name: Riebler
- first_name: Stefan
  full_name: Rohde, Stefan
  id: '34009'
  last_name: Rohde
- first_name: Robert
  full_name: Schade, Robert
  id: '75963'
  last_name: Schade
  orcid: 0000-0002-6268-5397
- first_name: Michael
  full_name: Schwarz, Michael
  id: '5312'
  last_name: Schwarz
- first_name: Jens
  full_name: Simon, Jens
  id: '15273'
  last_name: Simon
- first_name: Nils
  full_name: Winnwa, Nils
  id: '61189'
  last_name: Winnwa
- first_name: Alex
  full_name: Wiens, Alex
  id: '23522'
  last_name: Wiens
  orcid: 0000-0003-1764-9773
- first_name: Xin
  full_name: Wu, Xin
  id: '77439'
  last_name: Wu
citation:
  ama: Ehtesabi S, Hossain M, Kenter T, et al. <i>Otus Supercomputer</i>. Vol 1. Paderborn
    Center for Parallel Computing (PC2); 2025. doi:<a href="https://doi.org/10.48550/ARXIV.2512.07401">10.48550/ARXIV.2512.07401</a>
  apa: Ehtesabi, S., Hossain, M., Kenter, T., Krawinkel, A., Ostermann, L., Plessl,
    C., Riebler, H., Rohde, S., Schade, R., Schwarz, M., Simon, J., Winnwa, N., Wiens,
    A., &#38; Wu, X. (2025). <i>Otus Supercomputer</i> (Vol. 1). Paderborn Center
    for Parallel Computing (PC2). <a href="https://doi.org/10.48550/ARXIV.2512.07401">https://doi.org/10.48550/ARXIV.2512.07401</a>
  bibtex: '@book{Ehtesabi_Hossain_Kenter_Krawinkel_Ostermann_Plessl_Riebler_Rohde_Schade_Schwarz_et
    al._2025, place={Paderborn}, series={PC2 Tech­nic­al Re­port Series}, title={Otus
    Supercomputer}, volume={1}, DOI={<a href="https://doi.org/10.48550/ARXIV.2512.07401">10.48550/ARXIV.2512.07401</a>},
    publisher={Paderborn Center for Parallel Computing (PC2)}, author={Ehtesabi, Sadaf
    and Hossain, Manoar and Kenter, Tobias and Krawinkel, Andreas and Ostermann, Lukas
    and Plessl, Christian and Riebler, Heinrich and Rohde, Stefan and Schade, Robert
    and Schwarz, Michael and et al.}, year={2025}, collection={PC2 Tech­nic­al Re­port
    Series} }'
  chicago: 'Ehtesabi, Sadaf, Manoar Hossain, Tobias Kenter, Andreas Krawinkel, Lukas
    Ostermann, Christian Plessl, Heinrich Riebler, et al. <i>Otus Supercomputer</i>.
    Vol. 1. PC2 Tech­nic­al Re­port Series. Paderborn: Paderborn Center for Parallel
    Computing (PC2), 2025. <a href="https://doi.org/10.48550/ARXIV.2512.07401">https://doi.org/10.48550/ARXIV.2512.07401</a>.'
  ieee: 'S. Ehtesabi <i>et al.</i>, <i>Otus Supercomputer</i>, vol. 1. Paderborn:
    Paderborn Center for Parallel Computing (PC2), 2025.'
  mla: Ehtesabi, Sadaf, et al. <i>Otus Supercomputer</i>. Paderborn Center for Parallel
    Computing (PC2), 2025, doi:<a href="https://doi.org/10.48550/ARXIV.2512.07401">10.48550/ARXIV.2512.07401</a>.
  short: S. Ehtesabi, M. Hossain, T. Kenter, A. Krawinkel, L. Ostermann, C. Plessl,
    H. Riebler, S. Rohde, R. Schade, M. Schwarz, J. Simon, N. Winnwa, A. Wiens, X.
    Wu, Otus Supercomputer, Paderborn Center for Parallel Computing (PC2), Paderborn,
    2025.
date_created: 2025-12-09T09:11:04Z
date_updated: 2026-03-25T11:50:31Z
ddc:
- '004'
department:
- _id: '27'
- _id: '518'
doi: 10.48550/ARXIV.2512.07401
file:
- access_level: open_access
  content_type: application/pdf
  creator: deffel
  date_created: 2025-12-09T09:19:12Z
  date_updated: 2026-03-25T11:50:30Z
  file_id: '62982'
  file_name: 2512.07401v1.pdf
  file_size: 4535595
  relation: main_file
file_date_updated: 2026-03-25T11:50:30Z
has_accepted_license: '1'
intvolume: '         1'
keyword:
- Otus
- Supercomputer
- FPGA
- PC2
- Paderborn Center for Parallel Computing
- Noctua 2
- HPC
language:
- iso: eng
oa: '1'
page: '33'
place: Paderborn
publication_status: published
publisher: Paderborn Center for Parallel Computing (PC2)
report_number: PC2TR-2025-1
series_title: PC2 Tech­nic­al Re­port Series
status: public
title: Otus Supercomputer
type: report
user_id: '23522'
volume: 1
year: '2025'
...
---
_id: '53663'
abstract:
- lang: eng
  text: 'Noctua 2 is a supercomputer operated at the Paderborn Center for Parallel
    Computing (PC2) at Paderborn University in Germany. Noctua 2 was inaugurated in
    2022 and is an Atos BullSequana XH2000 system. It consists mainly of three node
    types: 1) CPU Compute nodes with AMD EPYC processors in different main memory
    configurations, 2) GPU nodes with NVIDIA A100 GPUs, and 3) FPGA nodes with Xilinx
    Alveo U280 and Intel Stratix 10 FPGA cards. While CPUs and GPUs are known off-the-shelf
    components in HPC systems, the operation of a large number of FPGA cards from
    different vendors and a dedicated FPGA-to-FPGA network are unique characteristics
    of Noctua 2. This paper describes in detail the overall setup of Noctua 2 and
    gives insights into the operation of the cluster from a hardware, software and
    facility perspective.'
article_type: original
author:
- first_name: Carsten
  full_name: Bauer, Carsten
  id: '90082'
  last_name: Bauer
- first_name: Tobias
  full_name: Kenter, Tobias
  id: '3145'
  last_name: Kenter
- first_name: Michael
  full_name: Lass, Michael
  id: '24135'
  last_name: Lass
  orcid: 0000-0002-5708-7632
- first_name: Lukas
  full_name: Mazur, Lukas
  id: '90492'
  last_name: Mazur
  orcid: ' 0000-0001-6304-7082'
- first_name: Marius
  full_name: Meyer, Marius
  id: '40778'
  last_name: Meyer
- first_name: Holger
  full_name: Nitsche, Holger
  id: '15272'
  last_name: Nitsche
- first_name: Heinrich
  full_name: Riebler, Heinrich
  id: '8961'
  last_name: Riebler
- first_name: Robert
  full_name: Schade, Robert
  id: '75963'
  last_name: Schade
  orcid: 0000-0002-6268-5397
- first_name: Michael
  full_name: Schwarz, Michael
  id: '5312'
  last_name: Schwarz
- first_name: Nils
  full_name: Winnwa, Nils
  id: '61189'
  last_name: Winnwa
- first_name: Alex
  full_name: Wiens, Alex
  id: '23522'
  last_name: Wiens
  orcid: 0000-0003-1764-9773
- first_name: Xin
  full_name: Wu, Xin
  id: '77439'
  last_name: Wu
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Jens
  full_name: Simon, Jens
  id: '15273'
  last_name: Simon
citation:
  ama: Bauer C, Kenter T, Lass M, et al. Noctua 2 Supercomputer. <i>Journal of large-scale
    research facilities</i>. 2024;9. doi:<a href="https://doi.org/10.17815/jlsrf-8-187
    ">10.17815/jlsrf-8-187 </a>
  apa: Bauer, C., Kenter, T., Lass, M., Mazur, L., Meyer, M., Nitsche, H., Riebler,
    H., Schade, R., Schwarz, M., Winnwa, N., Wiens, A., Wu, X., Plessl, C., &#38;
    Simon, J. (2024). Noctua 2 Supercomputer. <i>Journal of Large-Scale Research Facilities</i>,
    <i>9</i>. <a href="https://doi.org/10.17815/jlsrf-8-187 ">https://doi.org/10.17815/jlsrf-8-187
    </a>
  bibtex: '@article{Bauer_Kenter_Lass_Mazur_Meyer_Nitsche_Riebler_Schade_Schwarz_Winnwa_et
    al._2024, title={Noctua 2 Supercomputer}, volume={9}, DOI={<a href="https://doi.org/10.17815/jlsrf-8-187
    ">10.17815/jlsrf-8-187 </a>}, journal={Journal of large-scale research facilities},
    author={Bauer, Carsten and Kenter, Tobias and Lass, Michael and Mazur, Lukas and
    Meyer, Marius and Nitsche, Holger and Riebler, Heinrich and Schade, Robert and
    Schwarz, Michael and Winnwa, Nils and et al.}, year={2024} }'
  chicago: Bauer, Carsten, Tobias Kenter, Michael Lass, Lukas Mazur, Marius Meyer,
    Holger Nitsche, Heinrich Riebler, et al. “Noctua 2 Supercomputer.” <i>Journal
    of Large-Scale Research Facilities</i> 9 (2024). <a href="https://doi.org/10.17815/jlsrf-8-187
    ">https://doi.org/10.17815/jlsrf-8-187 </a>.
  ieee: 'C. Bauer <i>et al.</i>, “Noctua 2 Supercomputer,” <i>Journal of large-scale
    research facilities</i>, vol. 9, 2024, doi: <a href="https://doi.org/10.17815/jlsrf-8-187
    ">10.17815/jlsrf-8-187 </a>.'
  mla: Bauer, Carsten, et al. “Noctua 2 Supercomputer.” <i>Journal of Large-Scale
    Research Facilities</i>, vol. 9, 2024, doi:<a href="https://doi.org/10.17815/jlsrf-8-187
    ">10.17815/jlsrf-8-187 </a>.
  short: C. Bauer, T. Kenter, M. Lass, L. Mazur, M. Meyer, H. Nitsche, H. Riebler,
    R. Schade, M. Schwarz, N. Winnwa, A. Wiens, X. Wu, C. Plessl, J. Simon, Journal
    of Large-Scale Research Facilities 9 (2024).
date_created: 2024-04-26T07:39:41Z
date_updated: 2024-04-26T08:44:30Z
ddc:
- '004'
department:
- _id: '27'
- _id: '518'
doi: '10.17815/jlsrf-8-187 '
file:
- access_level: open_access
  content_type: application/pdf
  creator: deffel
  date_created: 2024-04-26T07:30:20Z
  date_updated: 2024-04-26T08:35:17Z
  file_id: '53664'
  file_name: Noctua2_Supercomputer.pdf
  file_size: 3825480
  relation: main_file
file_date_updated: 2024-04-26T08:35:17Z
has_accepted_license: '1'
intvolume: '         9'
keyword:
- Noctua 2
- Supercomputer
- FPGA
- PC2
- Paderborn Center for Parallel Computing
language:
- iso: eng
oa: '1'
project:
- _id: '52'
  name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: Journal of large-scale research facilities
publication_status: published
status: public
title: Noctua 2 Supercomputer
type: journal_article
user_id: '8961'
volume: 9
year: '2024'
...
---
_id: '21208'
abstract:
- lang: eng
  text: <jats:p>Heterogeneous platforms with FPGAs have started to be employed in
    the High-Performance Computing (HPC) field to improve performance and overall
    efficiency. These platforms allow the use of specialized hardware to accelerate
    software applications, but require the software to be adapted in what can be a
    prolonged and complex process. The main goal of this work is to describe and evaluate
    mechanisms that can transparently transfer the control flow between CPU and FPGA
    within the scope of HPC. Combining such a mechanism with transparent software
    profiling and accelerator configuration could lead to an automatic way of accelerating
    regular applications. In this work, a mechanism based on the ptrace system call
    is proposed, and its performance on the Intel Xeon+FPGA platform is evaluated.
    The feasibility of the proposed approach is demonstrated by a working prototype
    that performs the transparent control flow transfer of any function call to a
    matching hardware accelerator. This approach is more general than shared library
    interposition at the cost of a small time overhead in each accelerator use (about
    1.3ms in the prototype implementation).</jats:p>
article_number: '406'
author:
- first_name: Daniel
  full_name: Granhão, Daniel
  last_name: Granhão
- first_name: João Canas
  full_name: Canas Ferreira, João Canas
  last_name: Canas Ferreira
citation:
  ama: Granhão D, Canas Ferreira JC. Transparent Control Flow Transfer between CPU
    and Accelerators for HPC. <i>Electronics</i>. 2021. doi:<a href="https://doi.org/10.3390/electronics10040406">10.3390/electronics10040406</a>
  apa: Granhão, D., &#38; Canas Ferreira, J. C. (2021). Transparent Control Flow Transfer
    between CPU and Accelerators for HPC. <i>Electronics</i>. <a href="https://doi.org/10.3390/electronics10040406">https://doi.org/10.3390/electronics10040406</a>
  bibtex: '@article{Granhão_Canas Ferreira_2021, title={Transparent Control Flow Transfer
    between CPU and Accelerators for HPC}, DOI={<a href="https://doi.org/10.3390/electronics10040406">10.3390/electronics10040406</a>},
    number={406}, journal={Electronics}, author={Granhão, Daniel and Canas Ferreira,
    João Canas}, year={2021} }'
  chicago: Granhão, Daniel, and João Canas Canas Ferreira. “Transparent Control Flow
    Transfer between CPU and Accelerators for HPC.” <i>Electronics</i>, 2021. <a href="https://doi.org/10.3390/electronics10040406">https://doi.org/10.3390/electronics10040406</a>.
  ieee: D. Granhão and J. C. Canas Ferreira, “Transparent Control Flow Transfer between
    CPU and Accelerators for HPC,” <i>Electronics</i>, 2021.
  mla: Granhão, Daniel, and João Canas Canas Ferreira. “Transparent Control Flow Transfer
    between CPU and Accelerators for HPC.” <i>Electronics</i>, 406, 2021, doi:<a href="https://doi.org/10.3390/electronics10040406">10.3390/electronics10040406</a>.
  short: D. Granhão, J.C. Canas Ferreira, Electronics (2021).
date_created: 2021-02-12T07:22:03Z
date_updated: 2022-01-06T06:54:49Z
doi: 10.3390/electronics10040406
keyword:
- pc2-harp-ressources
language:
- iso: eng
publication: Electronics
publication_identifier:
  issn:
  - 2079-9292
publication_status: published
status: public
title: Transparent Control Flow Transfer between CPU and Accelerators for HPC
type: journal_article
user_id: '61189'
year: '2021'
...
---
_id: '35131'
abstract:
- lang: eng
  text: An FPGA accelerator for the computation of the semi-global Levenshtein distance
    between a pattern and a reference text is presented. The accelerator provides
    an important benefit to reduce the execution time of read-mappers used in short-read
    genomic sequencing. Previous attempts to solve the same problem in FPGA use the
    Myers algorithm following a column approach to compute the dynamic programming
    table. We use an approach based on diagonals that allows for some resource savings
    while maintaining a very high throughput of 1 alignment per clock cycle. The design
    is implemented in OpenCL and tested on two FPGA accelerators. The maximum performance
    obtained is 91.5 MPairs/s for 100 × 120 sequences and 47 MPairs/s for 300 × 360
    sequences, the highest ever reported for this problem.
author:
- first_name: David
  full_name: Castells-Rufas, David
  last_name: Castells-Rufas
- first_name: Santiago
  full_name: Marco-Sola, Santiago
  last_name: Marco-Sola
- first_name: Quim
  full_name: Aguado-Puig, Quim
  last_name: Aguado-Puig
- first_name: Antonio
  full_name: Espinosa-Morales, Antonio
  last_name: Espinosa-Morales
- first_name: Juan Carlos
  full_name: Moure, Juan Carlos
  last_name: Moure
- first_name: Lluc
  full_name: Alvarez, Lluc
  last_name: Alvarez
- first_name: Miquel
  full_name: Moreto, Miquel
  last_name: Moreto
citation:
  ama: 'Castells-Rufas D, Marco-Sola S, Aguado-Puig Q, et al. OpenCL-based FPGA Accelerator
    for Semi-Global Approximate String Matching Using Diagonal Bit-Vectors. In: <i>2021
    31st International Conference on Field-Programmable Logic and Applications (FPL)</i>.
    IEEE; 2021. doi:<a href="https://doi.org/10.1109/fpl53798.2021.00036">10.1109/fpl53798.2021.00036</a>'
  apa: Castells-Rufas, D., Marco-Sola, S., Aguado-Puig, Q., Espinosa-Morales, A.,
    Moure, J. C., Alvarez, L., &#38; Moreto, M. (2021). OpenCL-based FPGA Accelerator
    for Semi-Global Approximate String Matching Using Diagonal Bit-Vectors. <i>2021
    31st International Conference on Field-Programmable Logic and Applications (FPL)</i>.
    <a href="https://doi.org/10.1109/fpl53798.2021.00036">https://doi.org/10.1109/fpl53798.2021.00036</a>
  bibtex: '@inproceedings{Castells-Rufas_Marco-Sola_Aguado-Puig_Espinosa-Morales_Moure_Alvarez_Moreto_2021,
    title={OpenCL-based FPGA Accelerator for Semi-Global Approximate String Matching
    Using Diagonal Bit-Vectors}, DOI={<a href="https://doi.org/10.1109/fpl53798.2021.00036">10.1109/fpl53798.2021.00036</a>},
    booktitle={2021 31st International Conference on Field-Programmable Logic and
    Applications (FPL)}, publisher={IEEE}, author={Castells-Rufas, David and Marco-Sola,
    Santiago and Aguado-Puig, Quim and Espinosa-Morales, Antonio and Moure, Juan Carlos
    and Alvarez, Lluc and Moreto, Miquel}, year={2021} }'
  chicago: Castells-Rufas, David, Santiago Marco-Sola, Quim Aguado-Puig, Antonio Espinosa-Morales,
    Juan Carlos Moure, Lluc Alvarez, and Miquel Moreto. “OpenCL-Based FPGA Accelerator
    for Semi-Global Approximate String Matching Using Diagonal Bit-Vectors.” In <i>2021
    31st International Conference on Field-Programmable Logic and Applications (FPL)</i>.
    IEEE, 2021. <a href="https://doi.org/10.1109/fpl53798.2021.00036">https://doi.org/10.1109/fpl53798.2021.00036</a>.
  ieee: 'D. Castells-Rufas <i>et al.</i>, “OpenCL-based FPGA Accelerator for Semi-Global
    Approximate String Matching Using Diagonal Bit-Vectors,” 2021, doi: <a href="https://doi.org/10.1109/fpl53798.2021.00036">10.1109/fpl53798.2021.00036</a>.'
  mla: Castells-Rufas, David, et al. “OpenCL-Based FPGA Accelerator for Semi-Global
    Approximate String Matching Using Diagonal Bit-Vectors.” <i>2021 31st International
    Conference on Field-Programmable Logic and Applications (FPL)</i>, IEEE, 2021,
    doi:<a href="https://doi.org/10.1109/fpl53798.2021.00036">10.1109/fpl53798.2021.00036</a>.
  short: 'D. Castells-Rufas, S. Marco-Sola, Q. Aguado-Puig, A. Espinosa-Morales, J.C.
    Moure, L. Alvarez, M. Moreto, in: 2021 31st International Conference on Field-Programmable
    Logic and Applications (FPL), IEEE, 2021.'
date_created: 2023-01-03T10:05:13Z
date_updated: 2024-01-22T09:56:25Z
doi: 10.1109/fpl53798.2021.00036
keyword:
- pc2-harp-ressources
language:
- iso: eng
project:
- _id: '52'
  name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: 2021 31st International Conference on Field-Programmable Logic and Applications
  (FPL)
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: OpenCL-based FPGA Accelerator for Semi-Global Approximate String Matching Using
  Diagonal Bit-Vectors
type: conference
user_id: '3145'
year: '2021'
...
---
_id: '17359'
abstract:
- lang: eng
  text: <jats:p>In this article, we focus on the acceleration of a chemical reaction
    simulation that relies on a system of stiff ordinary differential equation (ODEs)
    targeting heterogeneous computing systems with CPUs and field-programmable gate
    arrays (FPGAs). Specifically, we target an essential kernel of the coupled chemistry
    aerosol-tracer transport model to the Brazilian developments on the regional atmospheric
    modeling system (CCATT-BRAMS). We focus on a linear solve step using the QR factorization
    based on the modified Gram-Schmidt method as the basis of the ODE solver in this
    application. We target Intel hardware accelerator research program (HARP) architecture
    with the OpenCL programming environment for these early experiments. Our design
    exploration reveals a hardware design that is up to 4 times faster than the original
    iterative Jacobi method used in this solver. Still, even with hardware support,
    the overall performance of our QR-based hardware is lower than its original software
    version.</jats:p>
article_number: '843'
author:
- first_name: Carlos
  full_name: Alberto Oliveira de Souza Junior, Carlos
  last_name: Alberto Oliveira de Souza Junior
- first_name: João
  full_name: Bispo, João
  last_name: Bispo
- first_name: João M. P.
  full_name: Cardoso, João M. P.
  last_name: Cardoso
- first_name: Pedro C.
  full_name: Diniz, Pedro C.
  last_name: Diniz
- first_name: Eduardo
  full_name: Marques, Eduardo
  last_name: Marques
citation:
  ama: Alberto Oliveira de Souza Junior C, Bispo J, Cardoso JMP, Diniz PC, Marques
    E. Exploration of FPGA-Based Hardware Designs for QR Decomposition for Solving
    Stiff ODE Numerical Methods Using the HARP Hybrid Architecture. <i>Electronics</i>.
    2020. doi:<a href="https://doi.org/10.3390/electronics9050843">10.3390/electronics9050843</a>
  apa: Alberto Oliveira de Souza Junior, C., Bispo, J., Cardoso, J. M. P., Diniz,
    P. C., &#38; Marques, E. (2020). Exploration of FPGA-Based Hardware Designs for
    QR Decomposition for Solving Stiff ODE Numerical Methods Using the HARP Hybrid
    Architecture. <i>Electronics</i>. <a href="https://doi.org/10.3390/electronics9050843">https://doi.org/10.3390/electronics9050843</a>
  bibtex: '@article{Alberto Oliveira de Souza Junior_Bispo_Cardoso_Diniz_Marques_2020,
    title={Exploration of FPGA-Based Hardware Designs for QR Decomposition for Solving
    Stiff ODE Numerical Methods Using the HARP Hybrid Architecture}, DOI={<a href="https://doi.org/10.3390/electronics9050843">10.3390/electronics9050843</a>},
    number={843}, journal={Electronics}, author={Alberto Oliveira de Souza Junior,
    Carlos and Bispo, João and Cardoso, João M. P. and Diniz, Pedro C. and Marques,
    Eduardo}, year={2020} }'
  chicago: Alberto Oliveira de Souza Junior, Carlos, João Bispo, João M. P. Cardoso,
    Pedro C. Diniz, and Eduardo Marques. “Exploration of FPGA-Based Hardware Designs
    for QR Decomposition for Solving Stiff ODE Numerical Methods Using the HARP Hybrid
    Architecture.” <i>Electronics</i>, 2020. <a href="https://doi.org/10.3390/electronics9050843">https://doi.org/10.3390/electronics9050843</a>.
  ieee: C. Alberto Oliveira de Souza Junior, J. Bispo, J. M. P. Cardoso, P. C. Diniz,
    and E. Marques, “Exploration of FPGA-Based Hardware Designs for QR Decomposition
    for Solving Stiff ODE Numerical Methods Using the HARP Hybrid Architecture,” <i>Electronics</i>,
    2020.
  mla: Alberto Oliveira de Souza Junior, Carlos, et al. “Exploration of FPGA-Based
    Hardware Designs for QR Decomposition for Solving Stiff ODE Numerical Methods
    Using the HARP Hybrid Architecture.” <i>Electronics</i>, 843, 2020, doi:<a href="https://doi.org/10.3390/electronics9050843">10.3390/electronics9050843</a>.
  short: C. Alberto Oliveira de Souza Junior, J. Bispo, J.M.P. Cardoso, P.C. Diniz,
    E. Marques, Electronics (2020).
date_created: 2020-07-08T08:18:59Z
date_updated: 2022-01-06T06:53:09Z
doi: 10.3390/electronics9050843
keyword:
- pc2-harp-ressources
language:
- iso: eng
publication: Electronics
publication_identifier:
  issn:
  - 2079-9292
publication_status: published
status: public
title: Exploration of FPGA-Based Hardware Designs for QR Decomposition for Solving
  Stiff ODE Numerical Methods Using the HARP Hybrid Architecture
type: journal_article
user_id: '61189'
year: '2020'
...
---
_id: '16411'
abstract:
- lang: eng
  text: FPGA devices have been proving to be good candidates to accelerate applications
    from different research topics. For instance, machine learning applications such
    as K-Means clustering usually relies on large amount of data to be processed,
    and, despite the performance offered by other architectures, FPGAs can offer better
    energy efficiency. With that in mind, Intel has launched a platform that integrates
    a multicore and an FPGA in the same package, enabling low latency and coherent
    fine-grained data offload. In this paper, we present a parallel implementation
    of the K-Means clustering algorithm, for this novel platform, using OpenCL language,
    and compared it against other platforms. We found that the CPU+FPGA platform was
    more energy efficient than the CPU-only approach from 70.71% to 85.92%, with Standard
    and Tiny input sizes respectively, and up to 68.21% of performance improvement
    was obtained with Tiny input size. Furthermore, it was up to 7.2×more energy efficient
    than an Intel® Xeon Phi ™, 21.5×than a cluster of Raspberry Pi boards, and 3.8×than
    the low-power MPPA-256 architecture, when the Standard input size was used.
author:
- first_name: Matheus A.
  full_name: Souza, Matheus A.
  last_name: Souza
- first_name: Lucas A.
  full_name: Maciel, Lucas A.
  last_name: Maciel
- first_name: Pedro Henrique
  full_name: Penna, Pedro Henrique
  last_name: Penna
- first_name: Henrique C.
  full_name: Freitas, Henrique C.
  last_name: Freitas
citation:
  ama: 'Souza MA, Maciel LA, Penna PH, Freitas HC. Energy Efficient Parallel K-Means
    Clustering for an Intel® Hybrid Multi-Chip Package. In: <i>2018 30th International
    Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)</i>.
    ; 2019. doi:<a href="https://doi.org/10.1109/cahpc.2018.8645850">10.1109/cahpc.2018.8645850</a>'
  apa: Souza, M. A., Maciel, L. A., Penna, P. H., &#38; Freitas, H. C. (2019). Energy
    Efficient Parallel K-Means Clustering for an Intel® Hybrid Multi-Chip Package.
    In <i>2018 30th International Symposium on Computer Architecture and High Performance
    Computing (SBAC-PAD)</i>. <a href="https://doi.org/10.1109/cahpc.2018.8645850">https://doi.org/10.1109/cahpc.2018.8645850</a>
  bibtex: '@inproceedings{Souza_Maciel_Penna_Freitas_2019, title={Energy Efficient
    Parallel K-Means Clustering for an Intel® Hybrid Multi-Chip Package}, DOI={<a
    href="https://doi.org/10.1109/cahpc.2018.8645850">10.1109/cahpc.2018.8645850</a>},
    booktitle={2018 30th International Symposium on Computer Architecture and High
    Performance Computing (SBAC-PAD)}, author={Souza, Matheus A. and Maciel, Lucas
    A. and Penna, Pedro Henrique and Freitas, Henrique C.}, year={2019} }'
  chicago: Souza, Matheus A., Lucas A. Maciel, Pedro Henrique Penna, and Henrique
    C. Freitas. “Energy Efficient Parallel K-Means Clustering for an Intel® Hybrid
    Multi-Chip Package.” In <i>2018 30th International Symposium on Computer Architecture
    and High Performance Computing (SBAC-PAD)</i>, 2019. <a href="https://doi.org/10.1109/cahpc.2018.8645850">https://doi.org/10.1109/cahpc.2018.8645850</a>.
  ieee: M. A. Souza, L. A. Maciel, P. H. Penna, and H. C. Freitas, “Energy Efficient
    Parallel K-Means Clustering for an Intel® Hybrid Multi-Chip Package,” in <i>2018
    30th International Symposium on Computer Architecture and High Performance Computing
    (SBAC-PAD)</i>, 2019.
  mla: Souza, Matheus A., et al. “Energy Efficient Parallel K-Means Clustering for
    an Intel® Hybrid Multi-Chip Package.” <i>2018 30th International Symposium on
    Computer Architecture and High Performance Computing (SBAC-PAD)</i>, 2019, doi:<a
    href="https://doi.org/10.1109/cahpc.2018.8645850">10.1109/cahpc.2018.8645850</a>.
  short: 'M.A. Souza, L.A. Maciel, P.H. Penna, H.C. Freitas, in: 2018 30th International
    Symposium on Computer Architecture and High Performance Computing (SBAC-PAD),
    2019.'
date_created: 2020-04-06T09:41:41Z
date_updated: 2022-01-06T06:52:50Z
doi: 10.1109/cahpc.2018.8645850
keyword:
- pc2-harp-ressources
language:
- iso: eng
publication: 2018 30th International Symposium on Computer Architecture and High Performance
  Computing (SBAC-PAD)
publication_identifier:
  isbn:
  - '9781538677698'
publication_status: published
status: public
title: Energy Efficient Parallel K-Means Clustering for an Intel® Hybrid Multi-Chip
  Package
type: conference
user_id: '61189'
year: '2019'
...
---
_id: '16413'
abstract:
- lang: eng
  text: In recent years, FPGAs have been successfully employed for the implementation
    of efficient, application-specific accelerators for a wide range of machine learning
    tasks. In this work, we consider probabilistic models, namely, (Mixed) Sum-Product
    Networks (SPN), a deep architecture that can provide tractable inference for multivariate
    distributions over mixed data-sources. We develop a fully pipelined FPGA accelerator
    architecture, including a pipelined interface to external memory, for the inference
    in (mixed) SPNs. To meet the precision constraints of SPNs, all computations are
    conducted using double-precision floating point arithmetic. Starting from an input
    description, the custom FPGA-accelerator is synthesized fully automatically by
    our tool flow. To the best of our knowledge, this work is the first approach to
    offload the SPN inference problem to FPGA-based accelerators. Our evaluation shows
    that the SPN inference problem benefits from offloading to our pipelined FPGA
    accelerator architecture.
author:
- first_name: Lukas
  full_name: Sommer, Lukas
  last_name: Sommer
- first_name: Julian
  full_name: Oppermann, Julian
  last_name: Oppermann
- first_name: Alejandro
  full_name: Molina, Alejandro
  last_name: Molina
- first_name: Carsten
  full_name: Binnig, Carsten
  last_name: Binnig
- first_name: Kristian
  full_name: Kersting, Kristian
  last_name: Kersting
- first_name: Andreas
  full_name: Koch, Andreas
  last_name: Koch
citation:
  ama: 'Sommer L, Oppermann J, Molina A, Binnig C, Kersting K, Koch A. Automatic Mapping
    of the Sum-Product Network Inference Problem to FPGA-Based Accelerators. In: <i>2018
    IEEE 36th International Conference on Computer Design (ICCD)</i>. ; 2019. doi:<a
    href="https://doi.org/10.1109/iccd.2018.00060">10.1109/iccd.2018.00060</a>'
  apa: Sommer, L., Oppermann, J., Molina, A., Binnig, C., Kersting, K., &#38; Koch,
    A. (2019). Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based
    Accelerators. In <i>2018 IEEE 36th International Conference on Computer Design
    (ICCD)</i>. <a href="https://doi.org/10.1109/iccd.2018.00060">https://doi.org/10.1109/iccd.2018.00060</a>
  bibtex: '@inproceedings{Sommer_Oppermann_Molina_Binnig_Kersting_Koch_2019, title={Automatic
    Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators},
    DOI={<a href="https://doi.org/10.1109/iccd.2018.00060">10.1109/iccd.2018.00060</a>},
    booktitle={2018 IEEE 36th International Conference on Computer Design (ICCD)},
    author={Sommer, Lukas and Oppermann, Julian and Molina, Alejandro and Binnig,
    Carsten and Kersting, Kristian and Koch, Andreas}, year={2019} }'
  chicago: Sommer, Lukas, Julian Oppermann, Alejandro Molina, Carsten Binnig, Kristian
    Kersting, and Andreas Koch. “Automatic Mapping of the Sum-Product Network Inference
    Problem to FPGA-Based Accelerators.” In <i>2018 IEEE 36th International Conference
    on Computer Design (ICCD)</i>, 2019. <a href="https://doi.org/10.1109/iccd.2018.00060">https://doi.org/10.1109/iccd.2018.00060</a>.
  ieee: L. Sommer, J. Oppermann, A. Molina, C. Binnig, K. Kersting, and A. Koch, “Automatic
    Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators,”
    in <i>2018 IEEE 36th International Conference on Computer Design (ICCD)</i>, 2019.
  mla: Sommer, Lukas, et al. “Automatic Mapping of the Sum-Product Network Inference
    Problem to FPGA-Based Accelerators.” <i>2018 IEEE 36th International Conference
    on Computer Design (ICCD)</i>, 2019, doi:<a href="https://doi.org/10.1109/iccd.2018.00060">10.1109/iccd.2018.00060</a>.
  short: 'L. Sommer, J. Oppermann, A. Molina, C. Binnig, K. Kersting, A. Koch, in:
    2018 IEEE 36th International Conference on Computer Design (ICCD), 2019.'
date_created: 2020-04-06T10:33:58Z
date_updated: 2022-01-06T06:52:50Z
doi: 10.1109/iccd.2018.00060
keyword:
- pc2-harp-ressources
language:
- iso: eng
publication: 2018 IEEE 36th International Conference on Computer Design (ICCD)
publication_identifier:
  isbn:
  - '9781538684771'
publication_status: published
status: public
title: Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based
  Accelerators
type: conference
user_id: '61189'
year: '2019'
...
---
_id: '16417'
abstract:
- lang: eng
  text: The performance of High-Level Synthesis (HLS) applications with irregular
    data structures is limited by its imperative programming paradigm like C/C++.
    In this paper, we show that constructing concurrent data structures with channels,
    a programming construct derived from CSP (communicating sequential processes)
    paradigm, is an effective approach to improve the performance of these applications.
    We evaluate concurrent data structure for FPGA by synthesizing a K-means clustering
    algorithm on the Intel HARP2 platform. A fully pipelined KMC processing element
    can be synthesized from OpenCL with the help of a SPSC (single-producer-single-consumer)
    queue and stack built from channels, achieving 15.2x speedup over a sequential
    baseline. The number of processing element can be scaled up by leveraging a MPMC
    (multiple-producer-multiple-consumer) stack with work distribution for dynamic
    load balance. Evaluation shows that an additional 3.5x speedup can be achieved
    when 4 processing element is instantiated. These results show that the concurrent
    data structure built with channels has great potential for improving the parallelism
    of HLS applications. We hope that our study will stimulate further research into
    the potential of channel-based HLS.
author:
- first_name: Hui
  full_name: Yan, Hui
  last_name: Yan
- first_name: Zhaoshi
  full_name: Li, Zhaoshi
  last_name: Li
- first_name: Leibo
  full_name: Liu, Leibo
  last_name: Liu
- first_name: Shouyi
  full_name: Yin, Shouyi
  last_name: Yin
- first_name: Shaojun
  full_name: Wei, Shaojun
  last_name: Wei
citation:
  ama: 'Yan H, Li Z, Liu L, Yin S, Wei S. Constructing Concurrent Data Structures
    on FPGA with Channels. In: <i>Proceedings of the 2019 ACM/SIGDA International
    Symposium on Field-Programmable Gate Arrays</i>. ; 2019. doi:<a href="https://doi.org/10.1145/3289602.3293921">10.1145/3289602.3293921</a>'
  apa: Yan, H., Li, Z., Liu, L., Yin, S., &#38; Wei, S. (2019). Constructing Concurrent
    Data Structures on FPGA with Channels. In <i>Proceedings of the 2019 ACM/SIGDA
    International Symposium on Field-Programmable Gate Arrays</i>. <a href="https://doi.org/10.1145/3289602.3293921">https://doi.org/10.1145/3289602.3293921</a>
  bibtex: '@inproceedings{Yan_Li_Liu_Yin_Wei_2019, title={Constructing Concurrent
    Data Structures on FPGA with Channels}, DOI={<a href="https://doi.org/10.1145/3289602.3293921">10.1145/3289602.3293921</a>},
    booktitle={Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable
    Gate Arrays}, author={Yan, Hui and Li, Zhaoshi and Liu, Leibo and Yin, Shouyi
    and Wei, Shaojun}, year={2019} }'
  chicago: Yan, Hui, Zhaoshi Li, Leibo Liu, Shouyi Yin, and Shaojun Wei. “Constructing
    Concurrent Data Structures on FPGA with Channels.” In <i>Proceedings of the 2019
    ACM/SIGDA International Symposium on Field-Programmable Gate Arrays</i>, 2019.
    <a href="https://doi.org/10.1145/3289602.3293921">https://doi.org/10.1145/3289602.3293921</a>.
  ieee: H. Yan, Z. Li, L. Liu, S. Yin, and S. Wei, “Constructing Concurrent Data Structures
    on FPGA with Channels,” in <i>Proceedings of the 2019 ACM/SIGDA International
    Symposium on Field-Programmable Gate Arrays</i>, 2019.
  mla: Yan, Hui, et al. “Constructing Concurrent Data Structures on FPGA with Channels.”
    <i>Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable
    Gate Arrays</i>, 2019, doi:<a href="https://doi.org/10.1145/3289602.3293921">10.1145/3289602.3293921</a>.
  short: 'H. Yan, Z. Li, L. Liu, S. Yin, S. Wei, in: Proceedings of the 2019 ACM/SIGDA
    International Symposium on Field-Programmable Gate Arrays, 2019.'
date_created: 2020-04-06T11:53:34Z
date_updated: 2022-01-06T06:52:50Z
doi: 10.1145/3289602.3293921
keyword:
- pc2-harp-ressources
language:
- iso: eng
publication: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable
  Gate Arrays
publication_identifier:
  isbn:
  - '9781450361378'
publication_status: published
status: public
title: Constructing Concurrent Data Structures on FPGA with Channels
type: conference
user_id: '61189'
year: '2019'
...
---
_id: '16420'
abstract:
- lang: eng
  text: '<jats:p> Field-Programmable Gate Arrays (FPGAs) are widely used in the central
    signal processing design of the Square Kilometer Array (SKA) as hardware accelerators.
    The frequency domain acceleration search (FDAS) module is an important part of
    the SKA1-MID pulsar search engine. To develop for a yet to be finalized hardware,
    for cross-discipline interoperability and to achieve fast prototyping, OpenCL
    as a high-level FPGA synthesis approaches employed to create the sub-modules of
    FDAS. The FT convolution and the harmonic-summing plus some other minor sub-modules
    are elements in the FDAS module that have been well-optimized separately before.
    In this paper, we explore the design space of combining well-optimized designs,
    dealing with the ensuing need to trade-off and compromise. Pipeline computing
    is employed to handle multiple input arrays at high speed. The hardware target
    is to employ multiple high-end FPGAs to process the combined FDAS module. The
    results show interesting consequences, where the best individual solutions are
    not necessarily the best solutions for the speed of a pipeline where FPGA resources
    and memory bandwidth need to be shared. By proposing multiple buffering techniques
    to the pipeline, the combined FDAS module can achieve up to 2[Formula: see text]
    speedup over implementations without pipeline computing. We perform an extensive
    experimental evaluation on multiple high-end FPGA cards hosted in a workstation
    and compare to a technology comparable mid-range GPU. </jats:p>'
article_number: '1950008'
author:
- first_name: Haomiao
  full_name: Wang, Haomiao
  last_name: Wang
- first_name: Prabu
  full_name: Thiagaraj, Prabu
  last_name: Thiagaraj
- first_name: Oliver
  full_name: Sinnen, Oliver
  last_name: Sinnen
citation:
  ama: Wang H, Thiagaraj P, Sinnen O. Combining Multiple Optimized FPGA-based Pulsar
    Search Modules Using OpenCL. <i>Journal of Astronomical Instrumentation</i>. 2019.
    doi:<a href="https://doi.org/10.1142/s2251171719500089">10.1142/s2251171719500089</a>
  apa: Wang, H., Thiagaraj, P., &#38; Sinnen, O. (2019). Combining Multiple Optimized
    FPGA-based Pulsar Search Modules Using OpenCL. <i>Journal of Astronomical Instrumentation</i>.
    <a href="https://doi.org/10.1142/s2251171719500089">https://doi.org/10.1142/s2251171719500089</a>
  bibtex: '@article{Wang_Thiagaraj_Sinnen_2019, title={Combining Multiple Optimized
    FPGA-based Pulsar Search Modules Using OpenCL}, DOI={<a href="https://doi.org/10.1142/s2251171719500089">10.1142/s2251171719500089</a>},
    number={1950008}, journal={Journal of Astronomical Instrumentation}, author={Wang,
    Haomiao and Thiagaraj, Prabu and Sinnen, Oliver}, year={2019} }'
  chicago: Wang, Haomiao, Prabu Thiagaraj, and Oliver Sinnen. “Combining Multiple
    Optimized FPGA-Based Pulsar Search Modules Using OpenCL.” <i>Journal of Astronomical
    Instrumentation</i>, 2019. <a href="https://doi.org/10.1142/s2251171719500089">https://doi.org/10.1142/s2251171719500089</a>.
  ieee: H. Wang, P. Thiagaraj, and O. Sinnen, “Combining Multiple Optimized FPGA-based
    Pulsar Search Modules Using OpenCL,” <i>Journal of Astronomical Instrumentation</i>,
    2019.
  mla: Wang, Haomiao, et al. “Combining Multiple Optimized FPGA-Based Pulsar Search
    Modules Using OpenCL.” <i>Journal of Astronomical Instrumentation</i>, 1950008,
    2019, doi:<a href="https://doi.org/10.1142/s2251171719500089">10.1142/s2251171719500089</a>.
  short: H. Wang, P. Thiagaraj, O. Sinnen, Journal of Astronomical Instrumentation
    (2019).
date_created: 2020-04-06T12:00:06Z
date_updated: 2022-01-06T06:52:50Z
doi: 10.1142/s2251171719500089
keyword:
- pc2-harp-ressources
language:
- iso: eng
publication: Journal of Astronomical Instrumentation
publication_identifier:
  issn:
  - 2251-1717
  - 2251-1725
publication_status: published
status: public
title: Combining Multiple Optimized FPGA-based Pulsar Search Modules Using OpenCL
type: journal_article
user_id: '61189'
year: '2019'
...
---
_id: '16422'
abstract:
- lang: eng
  text: <jats:p>Intel recently introduced the Heterogeneous Architecture Research
    Platform, HARP. In this platform, the Central Processing Unit and a Field-Programmable
    Gate Array are connected through a high-bandwidth, low-latency interconnect and
    both share DRAM memory. For this platform, Open Computing Language (OpenCL), a
    High-Level Synthesis (HLS) language, is made available. By making use of HLS,
    a faster design cycle can be achieved compared to programming in a traditional
    hardware description language. This, however, comes at the cost of having less
    control over the hardware implementation. We will investigate how OpenCL can be
    applied to implement a real-time guided image filter on the HARP platform. In
    the first phase, the performance-critical parameters of the OpenCL programming
    model are defined using several specialized benchmarks. In a second phase, the
    guided image filter algorithm is implemented using the insights gained in the
    first phase. Both a floating-point and a fixed-point implementation were developed
    for this algorithm, based on a sliding window implementation. This resulted in
    a maximum floating-point performance of 135 GFLOPS, a maximum fixed-point performance
    of 430 GOPS and a throughput of HD color images at 74 frames per second.</jats:p>
article_number: '149'
author:
- first_name: Thomas
  full_name: Faict, Thomas
  last_name: Faict
- first_name: Erik H.
  full_name: D’Hollander, Erik H.
  last_name: D’Hollander
- first_name: Bart
  full_name: Goossens, Bart
  last_name: Goossens
citation:
  ama: Faict T, D’Hollander EH, Goossens B. Mapping a Guided Image Filter on the HARP
    Reconfigurable Architecture Using OpenCL. <i>Algorithms</i>. 2019. doi:<a href="https://doi.org/10.3390/a12080149">10.3390/a12080149</a>
  apa: Faict, T., D’Hollander, E. H., &#38; Goossens, B. (2019). Mapping a Guided
    Image Filter on the HARP Reconfigurable Architecture Using OpenCL. <i>Algorithms</i>.
    <a href="https://doi.org/10.3390/a12080149">https://doi.org/10.3390/a12080149</a>
  bibtex: '@article{Faict_D’Hollander_Goossens_2019, title={Mapping a Guided Image
    Filter on the HARP Reconfigurable Architecture Using OpenCL}, DOI={<a href="https://doi.org/10.3390/a12080149">10.3390/a12080149</a>},
    number={149}, journal={Algorithms}, author={Faict, Thomas and D’Hollander, Erik
    H. and Goossens, Bart}, year={2019} }'
  chicago: Faict, Thomas, Erik H. D’Hollander, and Bart Goossens. “Mapping a Guided
    Image Filter on the HARP Reconfigurable Architecture Using OpenCL.” <i>Algorithms</i>,
    2019. <a href="https://doi.org/10.3390/a12080149">https://doi.org/10.3390/a12080149</a>.
  ieee: T. Faict, E. H. D’Hollander, and B. Goossens, “Mapping a Guided Image Filter
    on the HARP Reconfigurable Architecture Using OpenCL,” <i>Algorithms</i>, 2019.
  mla: Faict, Thomas, et al. “Mapping a Guided Image Filter on the HARP Reconfigurable
    Architecture Using OpenCL.” <i>Algorithms</i>, 149, 2019, doi:<a href="https://doi.org/10.3390/a12080149">10.3390/a12080149</a>.
  short: T. Faict, E.H. D’Hollander, B. Goossens, Algorithms (2019).
date_created: 2020-04-06T12:08:24Z
date_updated: 2022-01-06T06:52:50Z
doi: 10.3390/a12080149
keyword:
- pc2-harp-ressources
language:
- iso: eng
publication: Algorithms
publication_identifier:
  issn:
  - 1999-4893
publication_status: published
status: public
title: Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using
  OpenCL
type: journal_article
user_id: '61189'
year: '2019'
...
---
_id: '16423'
abstract:
- lang: eng
  text: Heterogeneous computing that exploits simultaneous co-processing with different
    device types has been shown to be effective at both increasing performance and
    reducing energy consumption. In this paper, we extend a scheduling framework encapsulated
    in a high-level C++ template and previously developed for heterogeneous chips
    comprising CPU and GPU cores, to new high-performance platforms for the data center,
    which include a cache coherent FPGA fabric and many-core CPU resources. Our goal
    is to evaluate the suitability of our framework with these new FPGA-based platforms,
    identifying performance benefits and limitations.We target the state-of-the-art
    HARP processor that includes 14 high-end Xeon classes tightly coupled to a FPGA
    device located in the same package. We select eight benchmarks from the high-performance
    computing domain that have been ported and optimized for this heterogeneous platform.
    The results show that a dynamic and adaptive scheduler that exploits simultaneous
    processing among the devices can improve performance up to a factor of 8 × compared
    to the best alternative solutions that only use the CPU cores or the FPGA fabric.
    Moreover, our proposal achieves up to 15% and 37% of improvement compared to the
    best heterogeneous solutions found with a dynamic and static schedulers, respectively.
author:
- first_name: Andrés
  full_name: Rodríguez, Andrés
  last_name: Rodríguez
- first_name: Angeles
  full_name: Navarro, Angeles
  last_name: Navarro
- first_name: Rafael
  full_name: Asenjo, Rafael
  last_name: Asenjo
- first_name: Francisco
  full_name: Corbera, Francisco
  last_name: Corbera
- first_name: Rubén
  full_name: Gran, Rubén
  last_name: Gran
- first_name: Darío
  full_name: Suárez, Darío
  last_name: Suárez
- first_name: Jose
  full_name: Nunez-Yanez, Jose
  last_name: Nunez-Yanez
citation:
  ama: Rodríguez A, Navarro A, Asenjo R, et al. Parallel multiprocessing and scheduling
    on the heterogeneous Xeon+FPGA platform. <i>The Journal of Supercomputing</i>.
    2019. doi:<a href="https://doi.org/10.1007/s11227-019-02935-1">10.1007/s11227-019-02935-1</a>
  apa: Rodríguez, A., Navarro, A., Asenjo, R., Corbera, F., Gran, R., Suárez, D.,
    &#38; Nunez-Yanez, J. (2019). Parallel multiprocessing and scheduling on the heterogeneous
    Xeon+FPGA platform. <i>The Journal of Supercomputing</i>. <a href="https://doi.org/10.1007/s11227-019-02935-1">https://doi.org/10.1007/s11227-019-02935-1</a>
  bibtex: '@article{Rodríguez_Navarro_Asenjo_Corbera_Gran_Suárez_Nunez-Yanez_2019,
    title={Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA
    platform}, DOI={<a href="https://doi.org/10.1007/s11227-019-02935-1">10.1007/s11227-019-02935-1</a>},
    journal={The Journal of Supercomputing}, author={Rodríguez, Andrés and Navarro,
    Angeles and Asenjo, Rafael and Corbera, Francisco and Gran, Rubén and Suárez,
    Darío and Nunez-Yanez, Jose}, year={2019} }'
  chicago: Rodríguez, Andrés, Angeles Navarro, Rafael Asenjo, Francisco Corbera, Rubén
    Gran, Darío Suárez, and Jose Nunez-Yanez. “Parallel Multiprocessing and Scheduling
    on the Heterogeneous Xeon+FPGA Platform.” <i>The Journal of Supercomputing</i>,
    2019. <a href="https://doi.org/10.1007/s11227-019-02935-1">https://doi.org/10.1007/s11227-019-02935-1</a>.
  ieee: A. Rodríguez <i>et al.</i>, “Parallel multiprocessing and scheduling on the
    heterogeneous Xeon+FPGA platform,” <i>The Journal of Supercomputing</i>, 2019.
  mla: Rodríguez, Andrés, et al. “Parallel Multiprocessing and Scheduling on the Heterogeneous
    Xeon+FPGA Platform.” <i>The Journal of Supercomputing</i>, 2019, doi:<a href="https://doi.org/10.1007/s11227-019-02935-1">10.1007/s11227-019-02935-1</a>.
  short: A. Rodríguez, A. Navarro, R. Asenjo, F. Corbera, R. Gran, D. Suárez, J. Nunez-Yanez,
    The Journal of Supercomputing (2019).
date_created: 2020-04-06T12:09:25Z
date_updated: 2022-01-06T06:52:50Z
doi: 10.1007/s11227-019-02935-1
keyword:
- pc2-harp-ressources
language:
- iso: eng
publication: The Journal of Supercomputing
publication_identifier:
  issn:
  - 0920-8542
  - 1573-0484
publication_status: published
status: public
title: Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform
type: journal_article
user_id: '61189'
year: '2019'
...
---
_id: '16427'
abstract:
- lang: eng
  text: "Transactional Memory (TM) has been considered as a promising alternative
    to existing synchronization operations, which are often the largest stumbling
    block to unleashing parallelism of applications. Efficient implementations of
    TM, however, are challenging due to the tension between lowering performance overhead
    and avoiding unnecessary aborts.\r\n\r\nIn this paper, we present Reachability-based
    Optimistic Concurrency Control for Transactional Memory (ROCoCoTM), a novel scheme
    which offloads concurrency control (CC) algorithms, the central building blocks
    of TM systems, to reconfigurable hardware. To reduce the abort rate, an innovative
    formalization of mainstream CC algorithms is developed to reveal a common restriction
    that leads to unnecessary aborts. This restriction is resolved by the ROCoCo algorithm
    with a centralized validation phase, which can be efficiently pipelined in hardware.
    Thanks to a high-performance offloading engine implemented in reconfigurable hardware,
    ROCoCo algorithm results in decreased abort rates and reduced performance overhead.
    The whole system is implemented on Intel's HARP2 platform and evaluated with the
    STAMP benchmark suite. Experiments show 1.55x and 8.05x geomean speedup over TinySTM
    and an HTM based on Intel TSX, respectively. Given the fast-growing deployment
    of commodity CPU-FPGA platforms, ROCoCoTM paves the way for software programmers
    to exploit heterogeneous computing resources with a high-level transactional abstraction
    to effectively extract the parallelism in modern applications."
author:
- first_name: Zhaoshi
  full_name: Li, Zhaoshi
  last_name: Li
- first_name: Leibo
  full_name: Liu, Leibo
  last_name: Liu
- first_name: Yangdong
  full_name: Deng, Yangdong
  last_name: Deng
- first_name: Jiawei
  full_name: Wang, Jiawei
  last_name: Wang
- first_name: Zhiwei
  full_name: Liu, Zhiwei
  last_name: Liu
- first_name: Shouyi
  full_name: Yin, Shouyi
  last_name: Yin
- first_name: Shaojun
  full_name: Wei, Shaojun
  last_name: Wei
citation:
  ama: 'Li Z, Liu L, Deng Y, et al. FPGA-Accelerated Optimistic Concurrency Control
    for Transactional Memory. In: <i>Proceedings of the 52nd Annual IEEE/ACM International
    Symposium on Microarchitecture</i>. ; 2019. doi:<a href="https://doi.org/10.1145/3352460.3358270">10.1145/3352460.3358270</a>'
  apa: Li, Z., Liu, L., Deng, Y., Wang, J., Liu, Z., Yin, S., &#38; Wei, S. (2019).
    FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory. In <i>Proceedings
    of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture</i>.
    <a href="https://doi.org/10.1145/3352460.3358270">https://doi.org/10.1145/3352460.3358270</a>
  bibtex: '@inproceedings{Li_Liu_Deng_Wang_Liu_Yin_Wei_2019, title={FPGA-Accelerated
    Optimistic Concurrency Control for Transactional Memory}, DOI={<a href="https://doi.org/10.1145/3352460.3358270">10.1145/3352460.3358270</a>},
    booktitle={Proceedings of the 52nd Annual IEEE/ACM International Symposium on
    Microarchitecture}, author={Li, Zhaoshi and Liu, Leibo and Deng, Yangdong and
    Wang, Jiawei and Liu, Zhiwei and Yin, Shouyi and Wei, Shaojun}, year={2019} }'
  chicago: Li, Zhaoshi, Leibo Liu, Yangdong Deng, Jiawei Wang, Zhiwei Liu, Shouyi
    Yin, and Shaojun Wei. “FPGA-Accelerated Optimistic Concurrency Control for Transactional
    Memory.” In <i>Proceedings of the 52nd Annual IEEE/ACM International Symposium
    on Microarchitecture</i>, 2019. <a href="https://doi.org/10.1145/3352460.3358270">https://doi.org/10.1145/3352460.3358270</a>.
  ieee: Z. Li <i>et al.</i>, “FPGA-Accelerated Optimistic Concurrency Control for
    Transactional Memory,” in <i>Proceedings of the 52nd Annual IEEE/ACM International
    Symposium on Microarchitecture</i>, 2019.
  mla: Li, Zhaoshi, et al. “FPGA-Accelerated Optimistic Concurrency Control for Transactional
    Memory.” <i>Proceedings of the 52nd Annual IEEE/ACM International Symposium on
    Microarchitecture</i>, 2019, doi:<a href="https://doi.org/10.1145/3352460.3358270">10.1145/3352460.3358270</a>.
  short: 'Z. Li, L. Liu, Y. Deng, J. Wang, Z. Liu, S. Yin, S. Wei, in: Proceedings
    of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019.'
date_created: 2020-04-06T12:49:40Z
date_updated: 2022-01-06T06:52:50Z
doi: 10.1145/3352460.3358270
keyword:
- pc2-harp-ressources
language:
- iso: eng
publication: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture
publication_identifier:
  isbn:
  - '9781450369381'
publication_status: published
status: public
title: FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory
type: conference
user_id: '61189'
year: '2019'
...
---
_id: '16416'
abstract:
- lang: eng
  text: The advent of FPGA-based hybrid architecture offers the opportunity of customizing
    memory subsystems to enhance the overall system performance. However, it is not
    straightforward to design efficient FPGA circuits for emerging FPGAs applications
    such as in-memory database and graph analytics, which heavily depend on concurrent
    data structures (CDS'). Highly dynamic behaviors of CDS' have to be orchestrated
    by synchronization primitives for correct execution. These primitives induce overwhelming
    memory traffic for synchronizations on FPGAs. This paper proposes a novel method
    for systematically exploring and exploiting memory-level parallelism (MLP) of
    CDS by transactional execution on FPGAs. Inspired by the idea that semantics of
    transactions can be implemented in a more efficient and scalable manner on FPGAs
    than on CPUs, we propose a transaction-based reconfigurable runtime system for
    capturing MLP of CDS'. Experiments on linked-list and skip-list show our approach
    achieves 5.18x and 1.55x throughput improvement on average than lock-based FPGA
    implementations and optimized CDS algorithms on a state-of-the-art multi-core
    CPU respectively.
author:
- first_name: Zhaoshi
  full_name: Li, Zhaoshi
  last_name: Li
- first_name: Leibo
  full_name: Liu, Leibo
  last_name: Liu
- first_name: Yangdong
  full_name: Deng, Yangdong
  last_name: Deng
- first_name: Shouyi
  full_name: Yin, Shouyi
  last_name: Yin
- first_name: Shaojun
  full_name: Wei, Shaojun
  last_name: Wei
citation:
  ama: Li Z, Liu L, Deng Y, Yin S, Wei S. Breaking the Synchronization Bottleneck
    with Reconfigurable Transactional Execution. <i>IEEE Computer Architecture Letters</i>.
    2018:147-150. doi:<a href="https://doi.org/10.1109/lca.2018.2828402">10.1109/lca.2018.2828402</a>
  apa: Li, Z., Liu, L., Deng, Y., Yin, S., &#38; Wei, S. (2018). Breaking the Synchronization
    Bottleneck with Reconfigurable Transactional Execution. <i>IEEE Computer Architecture
    Letters</i>, 147–150. <a href="https://doi.org/10.1109/lca.2018.2828402">https://doi.org/10.1109/lca.2018.2828402</a>
  bibtex: '@article{Li_Liu_Deng_Yin_Wei_2018, title={Breaking the Synchronization
    Bottleneck with Reconfigurable Transactional Execution}, DOI={<a href="https://doi.org/10.1109/lca.2018.2828402">10.1109/lca.2018.2828402</a>},
    journal={IEEE Computer Architecture Letters}, author={Li, Zhaoshi and Liu, Leibo
    and Deng, Yangdong and Yin, Shouyi and Wei, Shaojun}, year={2018}, pages={147–150}
    }'
  chicago: Li, Zhaoshi, Leibo Liu, Yangdong Deng, Shouyi Yin, and Shaojun Wei. “Breaking
    the Synchronization Bottleneck with Reconfigurable Transactional Execution.” <i>IEEE
    Computer Architecture Letters</i>, 2018, 147–50. <a href="https://doi.org/10.1109/lca.2018.2828402">https://doi.org/10.1109/lca.2018.2828402</a>.
  ieee: Z. Li, L. Liu, Y. Deng, S. Yin, and S. Wei, “Breaking the Synchronization
    Bottleneck with Reconfigurable Transactional Execution,” <i>IEEE Computer Architecture
    Letters</i>, pp. 147–150, 2018.
  mla: Li, Zhaoshi, et al. “Breaking the Synchronization Bottleneck with Reconfigurable
    Transactional Execution.” <i>IEEE Computer Architecture Letters</i>, 2018, pp.
    147–50, doi:<a href="https://doi.org/10.1109/lca.2018.2828402">10.1109/lca.2018.2828402</a>.
  short: Z. Li, L. Liu, Y. Deng, S. Yin, S. Wei, IEEE Computer Architecture Letters
    (2018) 147–150.
date_created: 2020-04-06T11:49:12Z
date_updated: 2022-01-06T06:52:50Z
doi: 10.1109/lca.2018.2828402
keyword:
- pc2-harp-ressources
language:
- iso: eng
page: 147-150
publication: IEEE Computer Architecture Letters
publication_identifier:
  issn:
  - 1556-6056
  - 1556-6064
  - 2473-2575
publication_status: published
status: public
title: Breaking the Synchronization Bottleneck with Reconfigurable Transactional Execution
type: journal_article
user_id: '61189'
year: '2018'
...
---
_id: '16421'
abstract:
- lang: eng
  text: The sheer amount of computing resources required to run modern cloud workloads
    has put a lot of pressure on the design of power efficient cluster nodes. To address
    this problem, Intel (HARP) and Microsoft (Catapult) have proposed CPU-FPGA integrated
    architectures that can deliver efficient power-performance executions. Unfortunately,
    the integration of FPGA acceleration modules to software is a challenging endeavor
    that does not have a seamless programming model. This paper proposes HardCloud
    (www.hardcloud.org), an extension of the OpenMP 4.X standard that eases the task
    of offloading FPGA modules to cluster accelerators.
author:
- first_name: Ciro
  full_name: Ceissler, Ciro
  last_name: Ceissler
- first_name: Ramon
  full_name: Nepomuceno, Ramon
  last_name: Nepomuceno
- first_name: Marcio
  full_name: Pereira, Marcio
  last_name: Pereira
- first_name: Guido
  full_name: Araujo, Guido
  last_name: Araujo
citation:
  ama: 'Ceissler C, Nepomuceno R, Pereira M, Araujo G. Automatic Offloading of Cluster
    Accelerators. In: <i>2018 IEEE 26th Annual International Symposium on Field-Programmable
    Custom Computing Machines (FCCM)</i>. ; 2018. doi:<a href="https://doi.org/10.1109/fccm.2018.00058">10.1109/fccm.2018.00058</a>'
  apa: Ceissler, C., Nepomuceno, R., Pereira, M., &#38; Araujo, G. (2018). Automatic
    Offloading of Cluster Accelerators. In <i>2018 IEEE 26th Annual International
    Symposium on Field-Programmable Custom Computing Machines (FCCM)</i>. <a href="https://doi.org/10.1109/fccm.2018.00058">https://doi.org/10.1109/fccm.2018.00058</a>
  bibtex: '@inproceedings{Ceissler_Nepomuceno_Pereira_Araujo_2018, title={Automatic
    Offloading of Cluster Accelerators}, DOI={<a href="https://doi.org/10.1109/fccm.2018.00058">10.1109/fccm.2018.00058</a>},
    booktitle={2018 IEEE 26th Annual International Symposium on Field-Programmable
    Custom Computing Machines (FCCM)}, author={Ceissler, Ciro and Nepomuceno, Ramon
    and Pereira, Marcio and Araujo, Guido}, year={2018} }'
  chicago: Ceissler, Ciro, Ramon Nepomuceno, Marcio Pereira, and Guido Araujo. “Automatic
    Offloading of Cluster Accelerators.” In <i>2018 IEEE 26th Annual International
    Symposium on Field-Programmable Custom Computing Machines (FCCM)</i>, 2018. <a
    href="https://doi.org/10.1109/fccm.2018.00058">https://doi.org/10.1109/fccm.2018.00058</a>.
  ieee: C. Ceissler, R. Nepomuceno, M. Pereira, and G. Araujo, “Automatic Offloading
    of Cluster Accelerators,” in <i>2018 IEEE 26th Annual International Symposium
    on Field-Programmable Custom Computing Machines (FCCM)</i>, 2018.
  mla: Ceissler, Ciro, et al. “Automatic Offloading of Cluster Accelerators.” <i>2018
    IEEE 26th Annual International Symposium on Field-Programmable Custom Computing
    Machines (FCCM)</i>, 2018, doi:<a href="https://doi.org/10.1109/fccm.2018.00058">10.1109/fccm.2018.00058</a>.
  short: 'C. Ceissler, R. Nepomuceno, M. Pereira, G. Araujo, in: 2018 IEEE 26th Annual
    International Symposium on Field-Programmable Custom Computing Machines (FCCM),
    2018.'
date_created: 2020-04-06T12:02:37Z
date_updated: 2022-01-06T06:52:50Z
doi: 10.1109/fccm.2018.00058
keyword:
- pc2-harp-ressources
language:
- iso: eng
publication: 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom
  Computing Machines (FCCM)
publication_identifier:
  isbn:
  - '9781538655221'
publication_status: published
status: public
title: Automatic Offloading of Cluster Accelerators
type: conference
user_id: '61189'
year: '2018'
...
---
_id: '16425'
abstract:
- lang: eng
  text: 'In recent years, OpenCL has been increasingly adopted as it enables software
    programmers to harness the performance and power efficiency of FPGAs. Despite
    simplifying the FPGA programming challenge, achieving high performance and energy
    efficiency with OpenCL is still a difficult task. In order to further contribute
    to the advance of the OpenCL usage for FPGAs, we utilize a realistic application
    scenario as our case study: the AutoDock molecular docking software. While OpenCL
    has proven its effectiveness in accelerating molecular docking on GPUs, for FPGA-based
    AutoDock accelerators it struggles with difficult design patterns. Besides complex
    multiple-producers to single-consumer datapaths, these include time-intensive
    loops with variable runtimes. Therefore, this work presents the design and optimization
    steps for implementing AutoDock in OpenCL targeting an Arria-10 FPGA, as well
    as a corresponding execution runtime and energy-efficiency evaluation. Applying
    these techniques improved the performance of the initial OpenCL implementation
    for FPGAs by three orders of magnitude, with the final version of the code now
    yielding speed-ups of up to ~2.7x, and energy-efficiency gains of up to ~1.8x
    over the original serial AutoDock version executing on a current-generation CPU.'
author:
- first_name: Leonardo
  full_name: Solis-Vasquez, Leonardo
  last_name: Solis-Vasquez
- first_name: Andreas
  full_name: Koch, Andreas
  last_name: Koch
citation:
  ama: 'Solis-Vasquez L, Koch A. A Case Study in Using OpenCL on FPGAs: Creating an
    Open-Source Accelerator of the AutoDock Molecular Docking Software. In: <i>FSP
    Workshop 2018; Fifth International Workshop on FPGAs for Software Programmers</i>.
    ; 2018:1-10.'
  apa: 'Solis-Vasquez, L., &#38; Koch, A. (2018). A Case Study in Using OpenCL on
    FPGAs: Creating an Open-Source Accelerator of the AutoDock Molecular Docking Software.
    In <i>FSP Workshop 2018; Fifth International Workshop on FPGAs for Software Programmers</i>
    (pp. 1–10).'
  bibtex: '@inproceedings{Solis-Vasquez_Koch_2018, title={A Case Study in Using OpenCL
    on FPGAs: Creating an Open-Source Accelerator of the AutoDock Molecular Docking
    Software}, booktitle={FSP Workshop 2018; Fifth International Workshop on FPGAs
    for Software Programmers}, author={Solis-Vasquez, Leonardo and Koch, Andreas},
    year={2018}, pages={1–10} }'
  chicago: 'Solis-Vasquez, Leonardo, and Andreas Koch. “A Case Study in Using OpenCL
    on FPGAs: Creating an Open-Source Accelerator of the AutoDock Molecular Docking
    Software.” In <i>FSP Workshop 2018; Fifth International Workshop on FPGAs for
    Software Programmers</i>, 1–10, 2018.'
  ieee: 'L. Solis-Vasquez and A. Koch, “A Case Study in Using OpenCL on FPGAs: Creating
    an Open-Source Accelerator of the AutoDock Molecular Docking Software,” in <i>FSP
    Workshop 2018; Fifth International Workshop on FPGAs for Software Programmers</i>,
    2018, pp. 1–10.'
  mla: 'Solis-Vasquez, Leonardo, and Andreas Koch. “A Case Study in Using OpenCL on
    FPGAs: Creating an Open-Source Accelerator of the AutoDock Molecular Docking Software.”
    <i>FSP Workshop 2018; Fifth International Workshop on FPGAs for Software Programmers</i>,
    2018, pp. 1–10.'
  short: 'L. Solis-Vasquez, A. Koch, in: FSP Workshop 2018; Fifth International Workshop
    on FPGAs for Software Programmers, 2018, pp. 1–10.'
date_created: 2020-04-06T12:23:38Z
date_updated: 2022-01-06T06:52:50Z
keyword:
- pc2-harp-ressources
language:
- iso: eng
page: 1-10
publication: FSP Workshop 2018; Fifth International Workshop on FPGAs for Software
  Programmers
status: public
title: 'A Case Study in Using OpenCL on FPGAs: Creating an Open-Source Accelerator
  of the AutoDock Molecular Docking Software'
type: conference
user_id: '61189'
year: '2018'
...