Analyzing performance portability for a SYCL implementation of the 2D shallow water equations - Büttner, Markus; Alt, Christoph; Kenter, Tobias; Köstler, Harald; Plessl, Christian; Aizinger, Vadym (The Journal of Supercomputing)
SYCL is an open standard for targeting heterogeneous hardware from C++. In this work, we evaluate a SYCL implementation for a discontinuous Galerkin discretization of the 2D shallow water equations targeting CPUs, GPUs, and also FPGAs. The discretization uses polynomial orders zero to two on unstructured triangular meshes. Separating memory accesses from the numerical code allow us to optimize data accesses for the target architecture. A performance analysis shows good portability across x86 and ARM CPUs, GPUs from different vendors, and even two variants of Intel Stratix 10 FPGAs. Measuring the energy to solution shows that GPUs yield an up to 10x higher energy efficiency in terms of degrees of freedom per joule compared to CPUs. With custom designed caches, FPGAs offer a meaningful complement to the other architectures with particularly good computational performance on smaller meshes. FPGAs with High Bandwidth Memory are less affected by bandwidth issues and have similar energy efficiency as latest generation CPUs.

Evaluating oneAPI I/O Pipes in a Case Study of Scaling a SYCL Jacobi Solver to multiple FPGAs - Alt, Christoph; Plessl, Christian; Kenter, Tobias (Proceedings of the 13th International Workshop on OpenCL and SYCL)
In the context of high-performance computing (HPC) for distributed workloads, individual field-programmable gate arrays (FPGAs) need efficient ways to exchange data, which requires network infrastructure and software abstractions. Dedicated multi-FPGA clusters provide inter-FPGA networks for direct device to device communication. The oneAPI high-level synthesis toolchain offers I/O pipes to allow user kernels to interact with the networking ports of the FPGA board. In this work, we evaluate using oneAPI I/O pipes for direct FPGA-to-FPGA communication by scaling a SYCL implementation of a Jacobi solver on up to 25 FPGAs in the Noctua 2 cluster. We see good results in weak and strong scaling experiments.
Keywords: Multi-FPGA; High-level Synthesis; oneAPI; FPGA

Adaptive Spectral Block Floating Point for Discontinuous Galerkin Methods - Sundriyal, Shivam; Büttner, Markus; Alt, Christoph; Kenter, Tobias; Aizinger, Vadym (2025 IEEE High Performance Extreme Computing Conference (HPEC))

StencilStream: A SYCL-based Stencil Simulation Framework Targeting FPGAs - Opdenhövel, Jan-Oliver; Alt, Christoph; Plessl, Christian; Kenter, Tobias (2024 34th International Conference on Field-Programmable Logic and Applications (FPL))

Enabling Performance Portability for Shallow Water Equations on CPUs, GPUs, and FPGAs with SYCL - Büttner, Markus; Alt, Christoph; Kenter, Tobias; Köstler, Harald; Plessl, Christian; Aizinger, Vadym (Proceedings of the Platform for Advanced Scientific Computing Conference (PASC))

Performance analysis of the free surface lattice Boltzmann implementation in waLBerla - Plewinski, Jonas; Alt, Christoph; Köstler, Harald; Rüde, Ulrich (PAMM)
Abstract The free‐surface lattice Boltzmann method uses a volume of fluid approach to simulate immiscible two‐fluid flow problems. It divides the simulation domain into three distinct phases—gas, fluid, and interface—where computation within the gas phase is disregarded. The interface delineates a one‐cell‐thick layer between the first two phases, validated physically for implementation in the HPC C++ multiphysics framework waLBerla but lacking an exhaustive performance analysis. This paper aims to shed light on node‐level performance on different architectures, employing continuous benchmarking, showing and analyzing weak scaling results on a modern HPC cluster, the Fritz supercomputer, and reporting energy consumption for the current implementation.

A continuous benchmarking infrastructure for high-performance computing applications - Alt, Christoph; Lanser, Martin; Plewinski, Jonas; Janki, Atin; Klawonn, Axel; Köstler, Harald; Selzer, Michael; Rüde, Ulrich (International Journal of Parallel, Emergent and Distributed Systems)

Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation Pipeline - Alt, Christoph; Kenter, Tobias; Faghih-Naini, Sara; Faj, Jennifer; Opdenhövel, Jan-Oliver; Plessl, Christian; Aizinger, Vadym; Hönig, Jan; Köstler, Harald (Lecture Notes in Computer Science)