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Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)</i>, edited by Omar Hammami and Sandra Larrabee, 2010."},"quality_controlled":"1","language":[{"iso":"eng"}],"_id":"2228","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"editor":[{"first_name":"Omar","full_name":"Hammami, Omar","last_name":"Hammami"},{"last_name":"Larrabee","full_name":"Larrabee, Sandra","first_name":"Sandra"}],"status":"public","type":"conference","publication":"Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)"},{"keyword":["Rupeas","DSL","WSN","testing"],"extern":"1","language":[{"iso":"eng"}],"_id":"2353","user_id":"16153","department":[{"_id":"27"},{"_id":"518"}],"abstract":[{"text":"Wireless Sensor Networks (WSNs) are unique embedded computation systems for distributed sensing of a dispersed phenomenon. While being a strongly concurrent distributed system, its embedded aspects with severe resource limitations and the wireless communication requires a fusion of technologies and methodologies from very different fields. As WSNs are deployed in remote locations for long-term unattended operation, assurance of correct functioning of the system is of prime concern. Thus, the design and development of WSNs requires specialized tools to allow for testing and debugging the system. To this end, we present a framework for analyzing and checking WSNs based on collected events during system operation. It allows for abstracting from the event trace by means of behavioral queries and uses assertions for checking the accordance of an execution to its specification. The framework is independent from WSN test platforms, applications and logging semantics and thus generally applicable for analyzing event logs of WSN test executions. ","lang":"eng"}],"status":"public","report_number":"TIK-Report 290","type":"report","title":"Rupeas: Ruby Powered Event Analysis DSL","date_updated":"2022-01-06T06:55:56Z","author":[{"first_name":"Matthias","full_name":"Woehrle, Matthias","last_name":"Woehrle"},{"full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"},{"last_name":"Thiele","full_name":"Thiele, Lothar","first_name":"Lothar"}],"date_created":"2018-04-16T15:09:19Z","place":"Computer Engineering and Networks Lab, ETH Zurich","year":"2009","citation":{"chicago":"Woehrle, Matthias, Christian Plessl, and Lothar Thiele. <i>Rupeas: Ruby Powered Event Analysis DSL</i>. Computer Engineering and Networks Lab, ETH Zurich, 2009.","ieee":"M. Woehrle, C. Plessl, and L. Thiele, <i>Rupeas: Ruby Powered Event Analysis DSL</i>. Computer Engineering and Networks Lab, ETH Zurich, 2009.","ama":"Woehrle M, Plessl C, Thiele L. <i>Rupeas: Ruby Powered Event Analysis DSL</i>. Computer Engineering and Networks Lab, ETH Zurich; 2009.","apa":"Woehrle, M., Plessl, C., &#38; Thiele, L. (2009). <i>Rupeas: Ruby Powered Event Analysis DSL</i>. Computer Engineering and Networks Lab, ETH Zurich.","mla":"Woehrle, Matthias, et al. <i>Rupeas: Ruby Powered Event Analysis DSL</i>. 2009.","short":"M. Woehrle, C. Plessl, L. Thiele, Rupeas: Ruby Powered Event Analysis DSL, Computer Engineering and Networks Lab, ETH Zurich, 2009.","bibtex":"@book{Woehrle_Plessl_Thiele_2009, place={Computer Engineering and Networks Lab, ETH Zurich}, title={Rupeas: Ruby Powered Event Analysis DSL}, author={Woehrle, Matthias and Plessl, Christian and Thiele, Lothar}, year={2009} }"}},{"date_updated":"2023-09-26T13:51:44Z","publisher":"IEEE Computer Society","date_created":"2018-04-16T15:05:52Z","author":[{"first_name":"Tobias","full_name":"Schumacher, Tobias","last_name":"Schumacher"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"}],"title":"IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing","doi":"10.1109/FCCM.2009.25","publication_identifier":{"isbn":["978-1-4244-4450-2"]},"quality_controlled":"1","year":"2009","page":"275-278","citation":{"ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing,” in <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 2009, pp. 275–278, doi: <a href=\"https://doi.org/10.1109/FCCM.2009.25\">10.1109/FCCM.2009.25</a>.","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” In <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 275–78. IEEE Computer Society, 2009. <a href=\"https://doi.org/10.1109/FCCM.2009.25\">https://doi.org/10.1109/FCCM.2009.25</a>.","ama":"Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. In: <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>. IEEE Computer Society; 2009:275-278. doi:<a href=\"https://doi.org/10.1109/FCCM.2009.25\">10.1109/FCCM.2009.25</a>","apa":"Schumacher, T., Plessl, C., &#38; Platzner, M. (2009). IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 275–278. <a href=\"https://doi.org/10.1109/FCCM.2009.25\">https://doi.org/10.1109/FCCM.2009.25</a>","short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing}, DOI={<a href=\"https://doi.org/10.1109/FCCM.2009.25\">10.1109/FCCM.2009.25</a>}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={275–278} }","mla":"Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, IEEE Computer Society, 2009, pp. 275–78, doi:<a href=\"https://doi.org/10.1109/FCCM.2009.25\">10.1109/FCCM.2009.25</a>."},"_id":"2350","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","keyword":["IMORC","interconnect","performance"],"language":[{"iso":"eng"}],"publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","type":"conference","abstract":[{"text":"Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. ","lang":"eng"}],"status":"public"},{"title":"EvoCaches: Application-specific Adaptation of Cache Mapping","date_created":"2018-04-06T15:18:24Z","author":[{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"}],"publisher":"IEEE Computer Society","date_updated":"2023-09-26T13:53:11Z","citation":{"mla":"Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, IEEE Computer Society, 2009, pp. 11–18.","short":"P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 11–18.","bibtex":"@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009}, pages={11–18} }","apa":"Kaufmann, P., Plessl, C., &#38; Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, 11–18.","ama":"Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation of Cache Mapping. In: <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>. IEEE Computer Society; 2009:11-18.","chicago":"Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” In <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009.","ieee":"P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific Adaptation of Cache Mapping,” in <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, 2009, pp. 11–18."},"page":"11-18","place":"Los Alamitos, CA, USA","year":"2009","quality_controlled":"1","language":[{"iso":"eng"}],"keyword":["EvoCache","evolvable hardware","computer architecture"],"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"_id":"2262","status":"public","abstract":[{"text":"In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. ","lang":"eng"}],"type":"conference","publication":"Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)"},{"quality_controlled":"1","publication_identifier":{"isbn":["978-1-4244-5108-1"]},"page":"265-276","citation":{"ama":"Beutel J, Gruber S, Hasler A, et al. PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes. In: <i>Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)</i>. IEEE Computer Society; 2009:265-276.","chicago":"Beutel, Jan, Stephan Gruber, Andi Hasler, Roman Lim, Andreas Meier, Christian Plessl, Igor Talzi, et al. “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes.” In <i>Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)</i>, 265–76. Washington, DC, USA: IEEE Computer Society, 2009.","ieee":"J. Beutel <i>et al.</i>, “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes,” in <i>Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)</i>, 2009, pp. 265–276.","apa":"Beutel, J., Gruber, S., Hasler, A., Lim, R., Meier, A., Plessl, C., Talzi, I., Thiele, L., Tschudin, C., Woehrle, M., &#38; Yuecel, M. (2009). PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes. <i>Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)</i>, 265–276.","short":"J. Beutel, S. Gruber, A. Hasler, R. Lim, A. Meier, C. Plessl, I. Talzi, L. Thiele, C. Tschudin, M. Woehrle, M. Yuecel, in: Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), IEEE Computer Society, Washington, DC, USA, 2009, pp. 265–276.","mla":"Beutel, Jan, et al. “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes.” <i>Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)</i>, IEEE Computer Society, 2009, pp. 265–76.","bibtex":"@inproceedings{Beutel_Gruber_Hasler_Lim_Meier_Plessl_Talzi_Thiele_Tschudin_Woehrle_et al._2009, place={Washington, DC, USA}, title={PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes}, booktitle={Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)}, publisher={IEEE Computer Society}, author={Beutel, Jan and Gruber, Stephan and Hasler, Andi and Lim, Roman and Meier, Andreas and Plessl, Christian and Talzi, Igor and Thiele, Lothar and Tschudin, Christian and Woehrle, Matthias and et al.}, year={2009}, pages={265–276} }"},"year":"2009","place":"Washington, DC, USA","date_created":"2018-04-16T15:08:07Z","author":[{"first_name":"Jan","last_name":"Beutel","full_name":"Beutel, Jan"},{"last_name":"Gruber","full_name":"Gruber, Stephan","first_name":"Stephan"},{"last_name":"Hasler","full_name":"Hasler, Andi","first_name":"Andi"},{"first_name":"Roman","full_name":"Lim, Roman","last_name":"Lim"},{"first_name":"Andreas","full_name":"Meier, Andreas","last_name":"Meier"},{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"},{"first_name":"Igor","last_name":"Talzi","full_name":"Talzi, Igor"},{"first_name":"Lothar","full_name":"Thiele, Lothar","last_name":"Thiele"},{"first_name":"Christian","last_name":"Tschudin","full_name":"Tschudin, Christian"},{"full_name":"Woehrle, Matthias","last_name":"Woehrle","first_name":"Matthias"},{"full_name":"Yuecel, Mustafa","last_name":"Yuecel","first_name":"Mustafa"}],"date_updated":"2023-09-26T13:52:01Z","publisher":"IEEE Computer Society","title":"PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes","publication":"Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)","type":"conference","status":"public","department":[{"_id":"27"},{"_id":"518"}],"user_id":"15278","_id":"2352","extern":"1","language":[{"iso":"eng"}],"keyword":["WSN","PermaSense"]},{"citation":{"chicago":"Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” In <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 119–24. Los Alamitos, CA, USA: IEEE Computer Society, 2009. <a href=\"https://doi.org/10.1109/ReConFig.2009.32\">https://doi.org/10.1109/ReConFig.2009.32</a>.","ieee":"T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000,” in <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2009, pp. 119–124, doi: <a href=\"https://doi.org/10.1109/ReConFig.2009.32\">10.1109/ReConFig.2009.32</a>.","ama":"Schumacher T, Süß T, Plessl C, Platzner M. Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. In: <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE Computer Society; 2009:119-124. doi:<a href=\"https://doi.org/10.1109/ReConFig.2009.32\">10.1109/ReConFig.2009.32</a>","apa":"Schumacher, T., Süß, T., Plessl, C., &#38; Platzner, M. (2009). Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 119–124. <a href=\"https://doi.org/10.1109/ReConFig.2009.32\">https://doi.org/10.1109/ReConFig.2009.32</a>","mla":"Schumacher, Tobias, et al. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE Computer Society, 2009, pp. 119–24, doi:<a href=\"https://doi.org/10.1109/ReConFig.2009.32\">10.1109/ReConFig.2009.32</a>.","short":"T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 119–124.","bibtex":"@inproceedings{Schumacher_Süß_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2009.32\">10.1109/ReConFig.2009.32</a>}, booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2009}, pages={119–124} }"},"page":"119-124","place":"Los Alamitos, CA, USA","year":"2009","publication_identifier":{"isbn":["978-0-7695-3917-1"]},"quality_controlled":"1","doi":"10.1109/ReConFig.2009.32","title":"Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000","author":[{"first_name":"Tobias","last_name":"Schumacher","full_name":"Schumacher, Tobias"},{"last_name":"Süß","full_name":"Süß, Tim","first_name":"Tim"},{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"}],"date_created":"2018-04-05T17:11:28Z","publisher":"IEEE Computer Society","date_updated":"2023-09-26T13:52:32Z","status":"public","type":"conference","publication":"Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)","language":[{"iso":"eng"}],"keyword":["IMORC","graphics"],"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"_id":"2238"},{"publication_identifier":{"isbn":["978-1-4244-3892-1"],"issn":["1946-1488"]},"quality_controlled":"1","year":"2009","page":"338-344","citation":{"bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={338–344} }","short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–344.","mla":"Schumacher, Tobias, et al. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2009, pp. 338–44.","apa":"Schumacher, T., Plessl, C., &#38; Platzner, M. (2009). An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 338–344.","ama":"Schumacher T, Plessl C, Platzner M. An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. In: <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2009:338-344.","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 338–44. IEEE, 2009.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure,” in <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2009, pp. 338–344."},"date_updated":"2023-09-26T13:52:52Z","publisher":"IEEE","author":[{"first_name":"Tobias","last_name":"Schumacher","full_name":"Schumacher, Tobias"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"date_created":"2018-04-06T15:15:47Z","title":"An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","type":"conference","status":"public","_id":"2261","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","keyword":["IMORC","NOC","KNN","accelerator"],"language":[{"iso":"eng"}]},{"year":"2009","place":"USA","page":"319-322","citation":{"short":"M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, USA, 2009, pp. 319–322.","mla":"Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2009, pp. 319–22.","bibtex":"@inproceedings{Grad_Plessl_2009, place={USA}, title={Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz and Plessl, Christian}, year={2009}, pages={319–322} }","apa":"Grad, M., &#38; Plessl, C. (2009). Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 319–322.","ama":"Grad M, Plessl C. Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2009:319-322.","ieee":"M. Grad and C. Plessl, “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2009, pp. 319–322.","chicago":"Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 319–22. USA: CSREA Press, 2009."},"quality_controlled":"1","publication_identifier":{"isbn":["1-60132-101-5"]},"title":"Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX","publisher":"CSREA Press","date_updated":"2023-09-26T13:53:30Z","author":[{"first_name":"Mariusz","full_name":"Grad, Mariusz","last_name":"Grad"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"}],"date_created":"2018-04-06T15:19:51Z","abstract":[{"text":"In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. ","lang":"eng"}],"status":"public","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","type":"conference","language":[{"iso":"eng"}],"_id":"2263","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278"},{"keyword":["WSN","testing","verification"],"language":[{"iso":"eng"}],"_id":"2370","department":[{"_id":"27"},{"_id":"518"}],"user_id":"15278","status":"public","publication":"IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC)","type":"conference","title":"EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks","doi":"10.1109/SUTC.2008.24","publisher":"IEEE Computer Society","date_updated":"2023-09-26T13:55:02Z","author":[{"first_name":"Matthias","full_name":"Woehrle, Matthias","last_name":"Woehrle"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982"},{"last_name":"Lim","full_name":"Lim, Roman","first_name":"Roman"},{"first_name":"Jan","full_name":"Beutel, Jan","last_name":"Beutel"},{"first_name":"Lothar","full_name":"Thiele, Lothar","last_name":"Thiele"}],"date_created":"2018-04-17T12:03:20Z","place":"Los Alamitos, CA, USA","year":"2008","page":"201-208","citation":{"bibtex":"@inproceedings{Woehrle_Plessl_Lim_Beutel_Thiele_2008, place={Los Alamitos, CA, USA}, title={EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks}, DOI={<a href=\"https://doi.org/10.1109/SUTC.2008.24\">10.1109/SUTC.2008.24</a>}, booktitle={IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC)}, publisher={IEEE Computer Society}, author={Woehrle, Matthias and Plessl, Christian and Lim, Roman and Beutel, Jan and Thiele, Lothar}, year={2008}, pages={201–208} }","short":"M. Woehrle, C. Plessl, R. Lim, J. Beutel, L. Thiele, in: IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC), IEEE Computer Society, Los Alamitos, CA, USA, 2008, pp. 201–208.","mla":"Woehrle, Matthias, et al. “EvAnT: Analysis and Checking of Event Traces for Wireless Sensor Networks.” <i>IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC)</i>, IEEE Computer Society, 2008, pp. 201–08, doi:<a href=\"https://doi.org/10.1109/SUTC.2008.24\">10.1109/SUTC.2008.24</a>.","apa":"Woehrle, M., Plessl, C., Lim, R., Beutel, J., &#38; Thiele, L. (2008). EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks. <i>IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC)</i>, 201–208. <a href=\"https://doi.org/10.1109/SUTC.2008.24\">https://doi.org/10.1109/SUTC.2008.24</a>","ama":"Woehrle M, Plessl C, Lim R, Beutel J, Thiele L. EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks. In: <i>IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC)</i>. IEEE Computer Society; 2008:201-208. doi:<a href=\"https://doi.org/10.1109/SUTC.2008.24\">10.1109/SUTC.2008.24</a>","ieee":"M. Woehrle, C. Plessl, R. Lim, J. Beutel, and L. Thiele, “EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks,” in <i>IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC)</i>, 2008, pp. 201–208, doi: <a href=\"https://doi.org/10.1109/SUTC.2008.24\">10.1109/SUTC.2008.24</a>.","chicago":"Woehrle, Matthias, Christian Plessl, Roman Lim, Jan Beutel, and Lothar Thiele. “EvAnT: Analysis and Checking of Event Traces for Wireless Sensor Networks.” In <i>IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC)</i>, 201–8. Los Alamitos, CA, USA: IEEE Computer Society, 2008. <a href=\"https://doi.org/10.1109/SUTC.2008.24\">https://doi.org/10.1109/SUTC.2008.24</a>."},"publication_identifier":{"isbn":["978-0-7695-3158-8"]},"quality_controlled":"1"},{"type":"conference","publication":"Proc. Int. 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Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 245–51. CSREA Press, 2008.","apa":"Schumacher, T., Meiche, R., Kaufmann, P., Lübbers, E., Plessl, C., &#38; Platzner, M. (2008). A Hardware Accelerator for k-th Nearest Neighbor Thinning. <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 245–251.","short":"T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251.","mla":"Schumacher, Tobias, et al. “A Hardware Accelerator for K-Th Nearest Neighbor Thinning.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2008, pp. 245–51.","bibtex":"@inproceedings{Schumacher_Meiche_Kaufmann_Lübbers_Plessl_Platzner_2008, title={A Hardware Accelerator for k-th Nearest Neighbor Thinning}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Schumacher, Tobias and Meiche, Robert and Kaufmann, Paul and Lübbers, Enno and Plessl, Christian and Platzner, Marco}, year={2008}, pages={245–251} }"},"page":"245-251","year":"2008","date_created":"2018-04-17T11:33:32Z","author":[{"first_name":"Tobias","full_name":"Schumacher, Tobias","last_name":"Schumacher"},{"full_name":"Meiche, Robert","last_name":"Meiche","first_name":"Robert"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"full_name":"Lübbers, Enno","last_name":"Lübbers","first_name":"Enno"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"date_updated":"2023-09-26T13:54:24Z","publisher":"CSREA Press","title":"A Hardware Accelerator for k-th Nearest Neighbor Thinning"},{"title":"IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers","date_updated":"2023-09-26T13:55:51Z","author":[{"last_name":"Schumacher","full_name":"Schumacher, Tobias","first_name":"Tobias"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"date_created":"2018-04-17T12:05:28Z","year":"2008","citation":{"ama":"Schumacher T, Plessl C, Platzner M. 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Platzner, in: Many-Core and Reconfigurable Supercomputing Conference (MRSC), 2008.","mla":"Schumacher, Tobias, et al. “IMORC: An Infrastructure for Performance Monitoring and Optimization of Reconfigurable Computers.” <i>Many-Core and Reconfigurable Supercomputing Conference (MRSC)</i>, 2008."},"quality_controlled":"1","keyword":["IMORC","IP core","interconnect"],"language":[{"iso":"eng"}],"_id":"2372","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"status":"public","type":"conference","publication":"Many-core and Reconfigurable Supercomputing Conference (MRSC)"},{"department":[{"_id":"27"},{"_id":"518"}],"user_id":"24135","_id":"2394","status":"public","type":"report","report_number":"TIK-Report 272","title":"Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework","date_created":"2018-04-17T13:36:38Z","author":[{"first_name":"Jan","last_name":"Beutel","full_name":"Beutel, Jan"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"},{"first_name":"Matthias","full_name":"Woehrle, Matthias","last_name":"Woehrle"}],"date_updated":"2022-01-06T06:56:04Z","citation":{"apa":"Beutel, J., Plessl, C., &#38; Woehrle, M. (2007). <i>Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework</i>. Computer Engineering and Networks Laboratory, ETH Zurich.","mla":"Beutel, Jan, et al. <i>Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework</i>. 2007.","bibtex":"@book{Beutel_Plessl_Woehrle_2007, place={Computer Engineering and Networks Laboratory, ETH Zurich}, title={Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework}, author={Beutel, Jan and Plessl, Christian and Woehrle, Matthias}, year={2007} }","short":"J. Beutel, C. Plessl, M. Woehrle, Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework, Computer Engineering and Networks Laboratory, ETH Zurich, 2007.","ieee":"J. Beutel, C. Plessl, and M. Woehrle, <i>Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework</i>. Computer Engineering and Networks Laboratory, ETH Zurich, 2007.","chicago":"Beutel, Jan, Christian Plessl, and Matthias Woehrle. <i>Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework</i>. Computer Engineering and Networks Laboratory, ETH Zurich, 2007.","ama":"Beutel J, Plessl C, Woehrle M. <i>Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework</i>. Computer Engineering and Networks Laboratory, ETH Zurich; 2007."},"year":"2007","place":"Computer Engineering and Networks Laboratory, ETH Zurich"}]