[{"user_id":"15278","keyword":["IMORC","interconnect","performance"],"doi":"10.1109/FCCM.2009.25","abstract":[{"text":"Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. ","lang":"eng"}],"title":"IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing","page":"275-278","type":"conference","publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","quality_controlled":"1","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"citation":{"apa":"Schumacher, T., Plessl, C., &#38; Platzner, M. (2009). IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 275–278. <a href=\"https://doi.org/10.1109/FCCM.2009.25\">https://doi.org/10.1109/FCCM.2009.25</a>","ama":"Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. In: <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>. IEEE Computer Society; 2009:275-278. doi:<a href=\"https://doi.org/10.1109/FCCM.2009.25\">10.1109/FCCM.2009.25</a>","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” In <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 275–78. IEEE Computer Society, 2009. <a href=\"https://doi.org/10.1109/FCCM.2009.25\">https://doi.org/10.1109/FCCM.2009.25</a>.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing,” in <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 2009, pp. 275–278, doi: <a href=\"https://doi.org/10.1109/FCCM.2009.25\">10.1109/FCCM.2009.25</a>.","mla":"Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, IEEE Computer Society, 2009, pp. 275–78, doi:<a href=\"https://doi.org/10.1109/FCCM.2009.25\">10.1109/FCCM.2009.25</a>.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing}, DOI={<a href=\"https://doi.org/10.1109/FCCM.2009.25\">10.1109/FCCM.2009.25</a>}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={275–278} }","short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278."},"author":[{"last_name":"Schumacher","full_name":"Schumacher, Tobias","first_name":"Tobias"},{"orcid":"0000-0001-5728-9982","id":"16153","last_name":"Plessl","first_name":"Christian","full_name":"Plessl, Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"date_updated":"2023-09-26T13:51:44Z","_id":"2350","year":"2009","publication_identifier":{"isbn":["978-1-4244-4450-2"]},"language":[{"iso":"eng"}],"status":"public","date_created":"2018-04-16T15:05:52Z","publisher":"IEEE Computer Society"},{"citation":{"chicago":"Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” In <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009.","ieee":"P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific Adaptation of Cache Mapping,” in <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, 2009, pp. 11–18.","ama":"Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation of Cache Mapping. In: <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>. IEEE Computer Society; 2009:11-18.","apa":"Kaufmann, P., Plessl, C., &#38; Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, 11–18.","short":"P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 11–18.","mla":"Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, IEEE Computer Society, 2009, pp. 11–18.","bibtex":"@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009}, pages={11–18} }"},"user_id":"15278","keyword":["EvoCache","evolvable hardware","computer architecture"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"EvoCaches: Application-specific Adaptation of Cache Mapping","author":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"orcid":"0000-0001-5728-9982","id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","first_name":"Christian"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"place":"Los Alamitos, CA, USA","abstract":[{"text":"In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. ","lang":"eng"}],"_id":"2262","page":"11-18","date_updated":"2023-09-26T13:53:11Z","publication":"Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","quality_controlled":"1","date_created":"2018-04-06T15:18:24Z","publisher":"IEEE Computer Society","type":"conference","year":"2009","language":[{"iso":"eng"}],"status":"public"},{"citation":{"apa":"Beutel, J., Gruber, S., Hasler, A., Lim, R., Meier, A., Plessl, C., Talzi, I., Thiele, L., Tschudin, C., Woehrle, M., &#38; Yuecel, M. (2009). PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes. <i>Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)</i>, 265–276.","ama":"Beutel J, Gruber S, Hasler A, et al. PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes. In: <i>Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)</i>. IEEE Computer Society; 2009:265-276.","ieee":"J. Beutel <i>et al.</i>, “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes,” in <i>Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)</i>, 2009, pp. 265–276.","chicago":"Beutel, Jan, Stephan Gruber, Andi Hasler, Roman Lim, Andreas Meier, Christian Plessl, Igor Talzi, et al. “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes.” In <i>Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)</i>, 265–76. Washington, DC, USA: IEEE Computer Society, 2009.","bibtex":"@inproceedings{Beutel_Gruber_Hasler_Lim_Meier_Plessl_Talzi_Thiele_Tschudin_Woehrle_et al._2009, place={Washington, DC, USA}, title={PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes}, booktitle={Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)}, publisher={IEEE Computer Society}, author={Beutel, Jan and Gruber, Stephan and Hasler, Andi and Lim, Roman and Meier, Andreas and Plessl, Christian and Talzi, Igor and Thiele, Lothar and Tschudin, Christian and Woehrle, Matthias and et al.}, year={2009}, pages={265–276} }","mla":"Beutel, Jan, et al. “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes.” <i>Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)</i>, IEEE Computer Society, 2009, pp. 265–76.","short":"J. Beutel, S. Gruber, A. Hasler, R. Lim, A. Meier, C. Plessl, I. Talzi, L. Thiele, C. Tschudin, M. Woehrle, M. Yuecel, in: Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), IEEE Computer Society, Washington, DC, USA, 2009, pp. 265–276."},"user_id":"15278","keyword":["WSN","PermaSense"],"department":[{"_id":"27"},{"_id":"518"}],"title":"PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes","author":[{"full_name":"Beutel, Jan","first_name":"Jan","last_name":"Beutel"},{"first_name":"Stephan","full_name":"Gruber, Stephan","last_name":"Gruber"},{"last_name":"Hasler","full_name":"Hasler, Andi","first_name":"Andi"},{"first_name":"Roman","full_name":"Lim, Roman","last_name":"Lim"},{"first_name":"Andreas","full_name":"Meier, Andreas","last_name":"Meier"},{"full_name":"Plessl, Christian","first_name":"Christian","last_name":"Plessl","id":"16153","orcid":"0000-0001-5728-9982"},{"first_name":"Igor","full_name":"Talzi, Igor","last_name":"Talzi"},{"last_name":"Thiele","first_name":"Lothar","full_name":"Thiele, Lothar"},{"last_name":"Tschudin","full_name":"Tschudin, Christian","first_name":"Christian"},{"full_name":"Woehrle, Matthias","first_name":"Matthias","last_name":"Woehrle"},{"last_name":"Yuecel","full_name":"Yuecel, Mustafa","first_name":"Mustafa"}],"extern":"1","place":"Washington, DC, USA","_id":"2352","page":"265-276","date_updated":"2023-09-26T13:52:01Z","publication":"Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)","quality_controlled":"1","date_created":"2018-04-16T15:08:07Z","publisher":"IEEE Computer Society","type":"conference","publication_identifier":{"isbn":["978-1-4244-5108-1"]},"year":"2009","language":[{"iso":"eng"}],"status":"public"},{"year":"2009","type":"conference","publication_identifier":{"isbn":["978-0-7695-3917-1"]},"language":[{"iso":"eng"}],"status":"public","publication":"Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)","quality_controlled":"1","date_created":"2018-04-05T17:11:28Z","publisher":"IEEE Computer Society","date_updated":"2023-09-26T13:52:32Z","_id":"2238","page":"119-124","place":"Los Alamitos, CA, USA","doi":"10.1109/ReConFig.2009.32","title":"Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000","author":[{"last_name":"Schumacher","first_name":"Tobias","full_name":"Schumacher, Tobias"},{"last_name":"Süß","full_name":"Süß, Tim","first_name":"Tim"},{"full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"citation":{"chicago":"Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” In <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 119–24. Los Alamitos, CA, USA: IEEE Computer Society, 2009. <a href=\"https://doi.org/10.1109/ReConFig.2009.32\">https://doi.org/10.1109/ReConFig.2009.32</a>.","ieee":"T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000,” in <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2009, pp. 119–124, doi: <a href=\"https://doi.org/10.1109/ReConFig.2009.32\">10.1109/ReConFig.2009.32</a>.","apa":"Schumacher, T., Süß, T., Plessl, C., &#38; Platzner, M. (2009). Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 119–124. <a href=\"https://doi.org/10.1109/ReConFig.2009.32\">https://doi.org/10.1109/ReConFig.2009.32</a>","ama":"Schumacher T, Süß T, Plessl C, Platzner M. Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. In: <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE Computer Society; 2009:119-124. doi:<a href=\"https://doi.org/10.1109/ReConFig.2009.32\">10.1109/ReConFig.2009.32</a>","short":"T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 119–124.","mla":"Schumacher, Tobias, et al. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE Computer Society, 2009, pp. 119–24, doi:<a href=\"https://doi.org/10.1109/ReConFig.2009.32\">10.1109/ReConFig.2009.32</a>.","bibtex":"@inproceedings{Schumacher_Süß_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2009.32\">10.1109/ReConFig.2009.32</a>}, booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2009}, pages={119–124} }"},"user_id":"15278","keyword":["IMORC","graphics"]},{"title":"An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure","author":[{"last_name":"Schumacher","first_name":"Tobias","full_name":"Schumacher, Tobias"},{"orcid":"0000-0001-5728-9982","id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","first_name":"Christian"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"citation":{"mla":"Schumacher, Tobias, et al. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2009, pp. 338–44.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={338–344} }","short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–344.","apa":"Schumacher, T., Plessl, C., &#38; Platzner, M. (2009). An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 338–344.","ama":"Schumacher T, Plessl C, Platzner M. An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. In: <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2009:338-344.","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 338–44. IEEE, 2009.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure,” in <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2009, pp. 338–344."},"keyword":["IMORC","NOC","KNN","accelerator"],"user_id":"15278","language":[{"iso":"eng"}],"year":"2009","publication_identifier":{"isbn":["978-1-4244-3892-1"],"issn":["1946-1488"]},"type":"conference","status":"public","date_created":"2018-04-06T15:15:47Z","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","quality_controlled":"1","publisher":"IEEE","date_updated":"2023-09-26T13:52:52Z","page":"338-344","_id":"2261"},{"year":"2009","type":"conference","publication_identifier":{"isbn":["1-60132-101-5"]},"language":[{"iso":"eng"}],"status":"public","quality_controlled":"1","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","date_created":"2018-04-06T15:19:51Z","publisher":"CSREA Press","date_updated":"2023-09-26T13:53:30Z","page":"319-322","_id":"2263","place":"USA","abstract":[{"lang":"eng","text":"In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. "}],"title":"Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX","author":[{"last_name":"Grad","first_name":"Mariusz","full_name":"Grad, Mariusz"},{"orcid":"0000-0001-5728-9982","id":"16153","last_name":"Plessl","first_name":"Christian","full_name":"Plessl, Christian"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"citation":{"ama":"Grad M, Plessl C. Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2009:319-322.","apa":"Grad, M., &#38; Plessl, C. (2009). Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 319–322.","ieee":"M. Grad and C. Plessl, “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2009, pp. 319–322.","chicago":"Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 319–22. USA: CSREA Press, 2009.","bibtex":"@inproceedings{Grad_Plessl_2009, place={USA}, title={Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz and Plessl, Christian}, year={2009}, pages={319–322} }","mla":"Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2009, pp. 319–22.","short":"M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, USA, 2009, pp. 319–322."},"user_id":"15278"},{"place":"Los Alamitos, CA, USA","doi":"10.1109/SUTC.2008.24","title":"EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks","author":[{"last_name":"Woehrle","first_name":"Matthias","full_name":"Woehrle, Matthias"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Lim","full_name":"Lim, Roman","first_name":"Roman"},{"last_name":"Beutel","first_name":"Jan","full_name":"Beutel, Jan"},{"last_name":"Thiele","full_name":"Thiele, Lothar","first_name":"Lothar"}],"department":[{"_id":"27"},{"_id":"518"}],"citation":{"apa":"Woehrle, M., Plessl, C., Lim, R., Beutel, J., &#38; Thiele, L. (2008). EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks. <i>IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC)</i>, 201–208. <a href=\"https://doi.org/10.1109/SUTC.2008.24\">https://doi.org/10.1109/SUTC.2008.24</a>","ama":"Woehrle M, Plessl C, Lim R, Beutel J, Thiele L. EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks. In: <i>IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC)</i>. IEEE Computer Society; 2008:201-208. doi:<a href=\"https://doi.org/10.1109/SUTC.2008.24\">10.1109/SUTC.2008.24</a>","ieee":"M. Woehrle, C. Plessl, R. Lim, J. Beutel, and L. Thiele, “EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks,” in <i>IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC)</i>, 2008, pp. 201–208, doi: <a href=\"https://doi.org/10.1109/SUTC.2008.24\">10.1109/SUTC.2008.24</a>.","chicago":"Woehrle, Matthias, Christian Plessl, Roman Lim, Jan Beutel, and Lothar Thiele. “EvAnT: Analysis and Checking of Event Traces for Wireless Sensor Networks.” In <i>IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC)</i>, 201–8. Los Alamitos, CA, USA: IEEE Computer Society, 2008. <a href=\"https://doi.org/10.1109/SUTC.2008.24\">https://doi.org/10.1109/SUTC.2008.24</a>.","bibtex":"@inproceedings{Woehrle_Plessl_Lim_Beutel_Thiele_2008, place={Los Alamitos, CA, USA}, title={EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks}, DOI={<a href=\"https://doi.org/10.1109/SUTC.2008.24\">10.1109/SUTC.2008.24</a>}, booktitle={IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC)}, publisher={IEEE Computer Society}, author={Woehrle, Matthias and Plessl, Christian and Lim, Roman and Beutel, Jan and Thiele, Lothar}, year={2008}, pages={201–208} }","mla":"Woehrle, Matthias, et al. “EvAnT: Analysis and Checking of Event Traces for Wireless Sensor Networks.” <i>IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC)</i>, IEEE Computer Society, 2008, pp. 201–08, doi:<a href=\"https://doi.org/10.1109/SUTC.2008.24\">10.1109/SUTC.2008.24</a>.","short":"M. Woehrle, C. Plessl, R. Lim, J. Beutel, L. Thiele, in: IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC), IEEE Computer Society, Los Alamitos, CA, USA, 2008, pp. 201–208."},"user_id":"15278","keyword":["WSN","testing","verification"],"year":"2008","publication_identifier":{"isbn":["978-0-7695-3158-8"]},"type":"conference","language":[{"iso":"eng"}],"status":"public","quality_controlled":"1","publication":"IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC)","date_created":"2018-04-17T12:03:20Z","publisher":"IEEE Computer Society","date_updated":"2023-09-26T13:55:02Z","page":"201-208","_id":"2370"},{"date_created":"2018-04-17T11:33:32Z","publication":"Proc. Int. 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CSREA Press, 2008.","bibtex":"@inproceedings{Schumacher_Meiche_Kaufmann_Lübbers_Plessl_Platzner_2008, title={A Hardware Accelerator for k-th Nearest Neighbor Thinning}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Schumacher, Tobias and Meiche, Robert and Kaufmann, Paul and Lübbers, Enno and Plessl, Christian and Platzner, Marco}, year={2008}, pages={245–251} }","mla":"Schumacher, Tobias, et al. “A Hardware Accelerator for K-Th Nearest Neighbor Thinning.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2008, pp. 245–51.","short":"T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, M. Platzner, in: Proc. Int. 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Computer Engineering and Networks Laboratory, ETH Zurich, 2007.","ieee":"J. Beutel, C. Plessl, and M. Woehrle, <i>Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework</i>. Computer Engineering and Networks Laboratory, ETH Zurich, 2007.","apa":"Beutel, J., Plessl, C., &#38; Woehrle, M. (2007). <i>Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework</i>. Computer Engineering and Networks Laboratory, ETH Zurich.","ama":"Beutel J, Plessl C, Woehrle M. <i>Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework</i>. Computer Engineering and Networks Laboratory, ETH Zurich; 2007.","short":"J. Beutel, C. Plessl, M. Woehrle, Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework, Computer Engineering and Networks Laboratory, ETH Zurich, 2007.","mla":"Beutel, Jan, et al. <i>Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework</i>. 2007.","bibtex":"@book{Beutel_Plessl_Woehrle_2007, place={Computer Engineering and Networks Laboratory, ETH Zurich}, title={Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework}, author={Beutel, Jan and Plessl, Christian and Woehrle, Matthias}, year={2007} }"},"user_id":"24135"},{"author":[{"last_name":"Woehrle","full_name":"Woehrle, Matthias","first_name":"Matthias"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Beutel","first_name":"Jan","full_name":"Beutel, Jan"},{"full_name":"Thiele, Lothar","first_name":"Lothar","last_name":"Thiele"}],"title":"Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework","doi":"10.1145/1278972.1278996","place":"New York, NY, USA","user_id":"15278","keyword":["WSN","testing","distributed","embedded"],"citation":{"chicago":"Woehrle, Matthias, Christian Plessl, Jan Beutel, and Lothar Thiele. “Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework.” In <i>Proc. Workshop on Embedded Networked Sensors (EmNets)</i>, 93–97. New York, NY, USA: ACM, 2007. <a href=\"https://doi.org/10.1145/1278972.1278996\">https://doi.org/10.1145/1278972.1278996</a>.","ieee":"M. Woehrle, C. Plessl, J. Beutel, and L. Thiele, “Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework,” in <i>Proc. Workshop on Embedded Networked Sensors (EmNets)</i>, 2007, pp. 93–97, doi: <a href=\"https://doi.org/10.1145/1278972.1278996\">10.1145/1278972.1278996</a>.","ama":"Woehrle M, Plessl C, Beutel J, Thiele L. Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework. In: <i>Proc. Workshop on Embedded Networked Sensors (EmNets)</i>. ACM; 2007:93-97. doi:<a href=\"https://doi.org/10.1145/1278972.1278996\">10.1145/1278972.1278996</a>","apa":"Woehrle, M., Plessl, C., Beutel, J., &#38; Thiele, L. (2007). Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework. <i>Proc. Workshop on Embedded Networked Sensors (EmNets)</i>, 93–97. <a href=\"https://doi.org/10.1145/1278972.1278996\">https://doi.org/10.1145/1278972.1278996</a>","short":"M. Woehrle, C. Plessl, J. Beutel, L. Thiele, in: Proc. Workshop on Embedded Networked Sensors (EmNets), ACM, New York, NY, USA, 2007, pp. 93–97.","mla":"Woehrle, Matthias, et al. “Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework.” <i>Proc. Workshop on Embedded Networked Sensors (EmNets)</i>, ACM, 2007, pp. 93–97, doi:<a href=\"https://doi.org/10.1145/1278972.1278996\">10.1145/1278972.1278996</a>.","bibtex":"@inproceedings{Woehrle_Plessl_Beutel_Thiele_2007, place={New York, NY, USA}, title={Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework}, DOI={<a href=\"https://doi.org/10.1145/1278972.1278996\">10.1145/1278972.1278996</a>}, booktitle={Proc. Workshop on Embedded Networked Sensors (EmNets)}, publisher={ACM}, author={Woehrle, Matthias and Plessl, Christian and Beutel, Jan and Thiele, Lothar}, year={2007}, pages={93–97} }"},"department":[{"_id":"27"},{"_id":"518"}],"publisher":"ACM","publication":"Proc. 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Int. Conf. Networked Sensing Systems (INSS)</i>, IEEE, 2007, pp. 303–303, doi:<a href=\"https://doi.org/10.1109/INSS.2007.4297445\">10.1109/INSS.2007.4297445</a>.","bibtex":"@inproceedings{Beutel_Dyer_Lim_Plessl_Woehrle_Yuecel_Thiele_2007, place={Piscataway, NJ, USA}, title={Automated Wireless Sensor Network Testing}, DOI={<a href=\"https://doi.org/10.1109/INSS.2007.4297445\">10.1109/INSS.2007.4297445</a>}, booktitle={Proc. Int. Conf. Networked Sensing Systems (INSS)}, publisher={IEEE}, author={Beutel, Jan and Dyer, Matthias and Lim, Roman and Plessl, Christian and Woehrle, Matthias and Yuecel, Mustafa and Thiele, Lothar}, year={2007}, pages={303–303} }","short":"J. Beutel, M. Dyer, R. Lim, C. Plessl, M. Woehrle, M. Yuecel, L. Thiele, in: Proc. Int. Conf. Networked Sensing Systems (INSS), IEEE, Piscataway, NJ, USA, 2007, pp. 303–303.","apa":"Beutel, J., Dyer, M., Lim, R., Plessl, C., Woehrle, M., Yuecel, M., &#38; Thiele, L. (2007). Automated Wireless Sensor Network Testing. <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>, 303–303. <a href=\"https://doi.org/10.1109/INSS.2007.4297445\">https://doi.org/10.1109/INSS.2007.4297445</a>","ama":"Beutel J, Dyer M, Lim R, et al. Automated Wireless Sensor Network Testing. In: <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>. IEEE; 2007:303-303. doi:<a href=\"https://doi.org/10.1109/INSS.2007.4297445\">10.1109/INSS.2007.4297445</a>","chicago":"Beutel, Jan, Matthias Dyer, Roman Lim, Christian Plessl, Matthias Woehrle, Mustafa Yuecel, and Lothar Thiele. “Automated Wireless Sensor Network Testing.” In <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>, 303–303. Piscataway, NJ, USA: IEEE, 2007. <a href=\"https://doi.org/10.1109/INSS.2007.4297445\">https://doi.org/10.1109/INSS.2007.4297445</a>.","ieee":"J. Beutel <i>et al.</i>, “Automated Wireless Sensor Network Testing,” in <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>, 2007, pp. 303–303, doi: <a href=\"https://doi.org/10.1109/INSS.2007.4297445\">10.1109/INSS.2007.4297445</a>."},"status":"public","language":[{"iso":"eng"}],"year":"2007","publication_identifier":{"isbn":["1-4244-1231-5"]},"type":"conference","publisher":"IEEE","date_created":"2018-04-17T13:35:55Z","publication":"Proc. Int. Conf. Networked Sensing Systems (INSS)","quality_controlled":"1","date_updated":"2023-09-26T14:00:58Z","page":"303-303","_id":"2393"},{"_id":"2404","date_updated":"2022-01-06T06:56:06Z","date_created":"2018-04-17T13:46:27Z","publisher":"Shaker Verlag","year":"2006","type":"dissertation","publication_identifier":{"isbn":["978-3-8322-5561-3"]},"status":"public","citation":{"short":"C. Plessl, Hardware Virtualization on a Coarse-Grained Reconfigurable Processor, Shaker Verlag, Aachen, Germany, 2006.","mla":"Plessl, Christian. <i>Hardware Virtualization on a Coarse-Grained Reconfigurable Processor</i>. Shaker Verlag, 2006, doi:<a href=\"https://doi.org/10.2370/9783832255619\">10.2370/9783832255619</a>.","bibtex":"@book{Plessl_2006, place={Aachen, Germany}, series={Technische Informatik}, title={Hardware virtualization on a coarse-grained reconfigurable processor}, DOI={<a href=\"https://doi.org/10.2370/9783832255619\">10.2370/9783832255619</a>}, publisher={Shaker Verlag}, author={Plessl, Christian}, year={2006}, collection={Technische Informatik} }","chicago":"Plessl, Christian. <i>Hardware Virtualization on a Coarse-Grained Reconfigurable Processor</i>. Technische Informatik. Aachen, Germany: Shaker Verlag, 2006. <a href=\"https://doi.org/10.2370/9783832255619\">https://doi.org/10.2370/9783832255619</a>.","ieee":"C. Plessl, <i>Hardware virtualization on a coarse-grained reconfigurable processor</i>. Aachen, Germany: Shaker Verlag, 2006.","apa":"Plessl, C. (2006). <i>Hardware virtualization on a coarse-grained reconfigurable processor</i>. Aachen, Germany: Shaker Verlag. <a href=\"https://doi.org/10.2370/9783832255619\">https://doi.org/10.2370/9783832255619</a>","ama":"Plessl C. <i>Hardware Virtualization on a Coarse-Grained Reconfigurable Processor</i>. Aachen, Germany: Shaker Verlag; 2006. doi:<a href=\"https://doi.org/10.2370/9783832255619\">10.2370/9783832255619</a>"},"series_title":"Technische Informatik","keyword":["Zippy"],"user_id":"24135","department":[{"_id":"518"}],"title":"Hardware virtualization on a coarse-grained reconfigurable processor","author":[{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","last_name":"Plessl","id":"16153"}],"place":"Aachen, Germany","abstract":[{"text":" In this thesis, we propose to use a reconfigurable processor as main computation element in embedded systems for applications from the multi-media and communications domain. A reconfigurable processor integrates an embedded CPU core with a Reconfigurable Processing Unit (RPU). Many of our target applications require real-time signal-processing of data streams and expose a high computational demand. The key challenge in designing embedded systems for these applications is to find an implementation that satisfies the performance goals and is adaptable to new applications, while the system cost is minimized. Implementations that solely use an embedded CPU are likely to miss the performance goals. Application-Specific Integrated Circuit (ASIC)-based coprocessors can be used for some high-volume products with fixed functions, but fall short for systems with varying applications. We argue that a reconfigurable processor with a coarse-grained, dynamically reconfigurable array of modest size provides an attractive implementation platform for our application domain. The computational intensive application kernels are executed on the RPU, while the remaining parts of the application are executed on the CPU. Reconfigurable hardware allows for implementing application specific coprocessors with a high performance, while the function of the coprocessor can still be adapted due to the programmability. So far, reconfigurable technology is used in embedded systems primarily with static configurations, e.g., for implementing glue-logic, replacing ASICs, and for implementing fixed-function coprocessors. Changing the configuration at runtime enables a number of interesting application modes, e.g., on-demand loading of coprocessors and time-multiplexed execution of coprocessors, which is commonly denoted as hardware virtualization. While the use of static configurations is well understood and supported by design-tools, the role of dynamic reconfiguration is not well investigated yet. Current application specification methods and design-tools do not provide an end-to-end tool-flow that considers dynamic reconfiguration. A key idea of our approach is to reduce system cost by keeping the size of the reconfigurable array small and to use hardware virtualization techniques to compensate for the limited hardware resources. The main contribution of this thesis is the codesign of a reconfigurable processor architecture named ZIPPY, the corresponding hardware and software implementation tools, and an application specification model which explicitly considers hardware virtualization. The ZIPPY architecture is widely parametrized and allows for specifying a whole family of processor architectures. The implementation tools are also parametrized and can target any architectural variant. We evaluate the performance of the architecture with a system-level, cycle-accurate cosimulation framework. This framework enables us to perform design-space exploration for a variety of reconfigurable processor architectures. With two case studies, we demonstrate, that hardware virtualization on the Zippy architecture is feasible and enables us to trade-off performance for area in embedded systems. Finally, we present a novel method for optimal temporal partitioning of sequential circuits, which is an important form of hardware virtualization. The method based on Slowdown and Retiming allows us to decompose any sequential circuit into a number of smaller, communicating subcircuits that can be executed on a dynamically reconfigurable architecture. ","lang":"eng"}],"doi":"10.2370/9783832255619"},{"department":[{"_id":"518"},{"_id":"78"}],"citation":{"bibtex":"@inproceedings{Plessl_Platzner_Thiele_2006, title={Optimal Temporal Partitioning based on Slowdown and Retiming}, DOI={<a href=\"https://doi.org/10.1109/FPT.2006.270344\">10.1109/FPT.2006.270344</a>}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco and Thiele, Lothar}, year={2006}, pages={345–348} }","mla":"Plessl, Christian, et al. “Optimal Temporal Partitioning Based on Slowdown and Retiming.” <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>, IEEE Computer Society, 2006, pp. 345–48, doi:<a href=\"https://doi.org/10.1109/FPT.2006.270344\">10.1109/FPT.2006.270344</a>.","short":"C. Plessl, M. Platzner, L. Thiele, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–348.","ama":"Plessl C, Platzner M, Thiele L. Optimal Temporal Partitioning based on Slowdown and Retiming. In: <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>. IEEE Computer Society; 2006:345-348. doi:<a href=\"https://doi.org/10.1109/FPT.2006.270344\">10.1109/FPT.2006.270344</a>","apa":"Plessl, C., Platzner, M., &#38; Thiele, L. (2006). Optimal Temporal Partitioning based on Slowdown and Retiming. In <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i> (pp. 345–348). IEEE Computer Society. <a href=\"https://doi.org/10.1109/FPT.2006.270344\">https://doi.org/10.1109/FPT.2006.270344</a>","ieee":"C. Plessl, M. Platzner, and L. Thiele, “Optimal Temporal Partitioning based on Slowdown and Retiming,” in <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>, 2006, pp. 345–348.","chicago":"Plessl, Christian, Marco Platzner, and Lothar Thiele. “Optimal Temporal Partitioning Based on Slowdown and Retiming.” In <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>, 345–48. IEEE Computer Society, 2006. <a href=\"https://doi.org/10.1109/FPT.2006.270344\">https://doi.org/10.1109/FPT.2006.270344</a>."},"keyword":["temporal partitioning","retiming","ILP"],"user_id":"24135","abstract":[{"lang":"eng","text":" This paper presents a novel method for optimal temporal partitioning of sequential circuits for time-multiplexed reconfigurable architectures. The method bases on slowdown and retiming and maximizes the circuit's performance during execution while restricting the size of the partitions to respect the resource constraints of the reconfigurable architecture. We provide a mixed integer linear program (MILP) formulation of the problem, which can be solved exactly. In contrast to related work, our approach optimizes performance directly, takes structural modifications of the circuit into account, and is extensible. We present the application of the new method to temporal partitioning for a coarse-grained reconfigurable architecture. "}],"doi":"10.1109/FPT.2006.270344","title":"Optimal Temporal Partitioning based on Slowdown and Retiming","author":[{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"},{"last_name":"Thiele","first_name":"Lothar","full_name":"Thiele, Lothar"}],"date_updated":"2022-01-06T06:56:05Z","_id":"2401","page":"345-348","type":"conference","year":"2006","status":"public","date_created":"2018-04-17T13:43:21Z","publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)","publisher":"IEEE Computer Society"},{"publisher":"IEEE Computer Society","publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","date_created":"2018-04-17T14:34:03Z","status":"public","year":"2005","type":"conference","page":"213-218","_id":"2411","date_updated":"2022-01-06T06:56:07Z","author":[{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","last_name":"Plessl","id":"16153"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"}],"title":"Zippy – A coarse-grained reconfigurable array with support for hardware virtualization","abstract":[{"lang":"eng","text":" This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder. "}],"doi":"10.1109/ASAP.2005.69","user_id":"24135","keyword":["Zippy"],"citation":{"chicago":"Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” In <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 213–18. IEEE Computer Society, 2005. <a href=\"https://doi.org/10.1109/ASAP.2005.69\">https://doi.org/10.1109/ASAP.2005.69</a>.","ieee":"C. Plessl and M. Platzner, “Zippy – A coarse-grained reconfigurable array with support for hardware virtualization,” in <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 2005, pp. 213–218.","ama":"Plessl C, Platzner M. Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In: <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>. IEEE Computer Society; 2005:213-218. doi:<a href=\"https://doi.org/10.1109/ASAP.2005.69\">10.1109/ASAP.2005.69</a>","apa":"Plessl, C., &#38; Platzner, M. (2005). Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i> (pp. 213–218). IEEE Computer Society. <a href=\"https://doi.org/10.1109/ASAP.2005.69\">https://doi.org/10.1109/ASAP.2005.69</a>","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–218.","mla":"Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, IEEE Computer Society, 2005, pp. 213–18, doi:<a href=\"https://doi.org/10.1109/ASAP.2005.69\">10.1109/ASAP.2005.69</a>.","bibtex":"@inproceedings{Plessl_Platzner_2005, title={Zippy – A coarse-grained reconfigurable array with support for hardware virtualization}, DOI={<a href=\"https://doi.org/10.1109/ASAP.2005.69\">10.1109/ASAP.2005.69</a>}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2005}, pages={213–218} }"},"department":[{"_id":"518"},{"_id":"78"}]},{"volume":29,"_id":"2412","page":"63-73","issue":"2-3","date_updated":"2022-01-06T06:56:07Z","publisher":"Elsevier","date_created":"2018-04-17T14:36:10Z","publication":"Microprocessors and Microsystems","status":"public","year":"2005","type":"journal_article","keyword":["FPGA","reconfigurable computing","co-simulation","Zippy"],"user_id":"24135","citation":{"ieee":"R. Enzler, C. Plessl, and M. Platzner, “System-level performance evaluation of reconfigurable processors,” <i>Microprocessors and Microsystems</i>, vol. 29, no. 2–3, pp. 63–73, 2005.","chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “System-Level Performance Evaluation of Reconfigurable Processors.” <i>Microprocessors and Microsystems</i> 29, no. 2–3 (2005): 63–73. <a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">https://doi.org/10.1016/j.micpro.2004.06.004</a>.","ama":"Enzler R, Plessl C, Platzner M. System-level performance evaluation of reconfigurable processors. <i>Microprocessors and Microsystems</i>. 2005;29(2-3):63-73. doi:<a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">10.1016/j.micpro.2004.06.004</a>","apa":"Enzler, R., Plessl, C., &#38; Platzner, M. (2005). System-level performance evaluation of reconfigurable processors. <i>Microprocessors and Microsystems</i>, <i>29</i>(2–3), 63–73. <a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">https://doi.org/10.1016/j.micpro.2004.06.004</a>","short":"R. Enzler, C. Plessl, M. Platzner, Microprocessors and Microsystems 29 (2005) 63–73.","bibtex":"@article{Enzler_Plessl_Platzner_2005, title={System-level performance evaluation of reconfigurable processors}, volume={29}, DOI={<a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">10.1016/j.micpro.2004.06.004</a>}, number={2–3}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2005}, pages={63–73} }","mla":"Enzler, Rolf, et al. “System-Level Performance Evaluation of Reconfigurable Processors.” <i>Microprocessors and Microsystems</i>, vol. 29, no. 2–3, Elsevier, 2005, pp. 63–73, doi:<a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">10.1016/j.micpro.2004.06.004</a>."},"department":[{"_id":"518"},{"_id":"78"}],"author":[{"first_name":"Rolf","full_name":"Enzler, Rolf","last_name":"Enzler"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","first_name":"Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"title":"System-level performance evaluation of reconfigurable processors","intvolume":"        29","abstract":[{"lang":"eng","text":" Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors."}],"doi":"10.1016/j.micpro.2004.06.004"},{"abstract":[{"text":"In this paper we introduce to virtualization of hardware on reconfigurable devices. We identify three main approaches denoted with temporal partitioning, virtualized execution, and virtual machine. For each virtualization approach, we discuss the application models, the required execution architectures, the design tools and the run-time systems. Then, we survey a selection of important projects in the field. ","lang":"eng"}],"title":"Virtualization of Hardware – Introduction and Survey","author":[{"full_name":"Plessl, Christian","first_name":"Christian","last_name":"Plessl","id":"16153","orcid":"0000-0001-5728-9982"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"}],"department":[{"_id":"518"},{"_id":"78"}],"citation":{"chicago":"Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 63–69. CSREA Press, 2004.","ieee":"C. Plessl and M. Platzner, “Virtualization of Hardware – Introduction and Survey,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2004, pp. 63–69.","apa":"Plessl, C., &#38; Platzner, M. (2004). Virtualization of Hardware – Introduction and Survey. In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i> (pp. 63–69). CSREA Press.","ama":"Plessl C, Platzner M. Virtualization of Hardware – Introduction and Survey. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2004:63-69.","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004, pp. 63–69.","mla":"Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2004, pp. 63–69.","bibtex":"@inproceedings{Plessl_Platzner_2004, title={Virtualization of Hardware – Introduction and Survey}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian and Platzner, Marco}, year={2004}, pages={63–69} }"},"keyword":["hardware virtualization"],"user_id":"24135","type":"conference","year":"2004","status":"public","date_created":"2018-04-17T14:45:57Z","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","publisher":"CSREA Press","date_updated":"2022-01-06T06:56:08Z","_id":"2415","page":"63-69"},{"abstract":[{"text":" This paper presents TKDM, a PC-based high-performance reconfigurable computing environment. The TKDM hardware consists of an FPGA module that uses the DIMM (dual inline memory module) bus for high-bandwidth and low-latency communication with the host CPU. The system's firmware is integrated with the Linux host operating system and offers functions for data communication and FPGA reconfiguration. The intended use of TKDM is that of a dynamically reconfigurable co-processor for data streaming applications. The system's firmware can be customized for specific application domains to facilitate simple and easy-to-use programming interfaces. ","lang":"eng"}],"doi":"10.1109/FPT.2003.1275755","title":"TKDM – A Reconfigurable Co-processor in a PC's Memory Slot","author":[{"id":"16153","last_name":"Plessl","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"department":[{"_id":"518"},{"_id":"78"}],"citation":{"apa":"Plessl, C., &#38; Platzner, M. (2003). TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i> (pp. 252–259). IEEE Computer Society. <a href=\"https://doi.org/10.1109/FPT.2003.1275755\">https://doi.org/10.1109/FPT.2003.1275755</a>","ama":"Plessl C, Platzner M. TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In: <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>. IEEE Computer Society; 2003:252-259. doi:<a href=\"https://doi.org/10.1109/FPT.2003.1275755\">10.1109/FPT.2003.1275755</a>","chicago":"Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor in a PC’s Memory Slot.” In <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>, 252–59. IEEE Computer Society, 2003. <a href=\"https://doi.org/10.1109/FPT.2003.1275755\">https://doi.org/10.1109/FPT.2003.1275755</a>.","ieee":"C. Plessl and M. Platzner, “TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot,” in <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>, 2003, pp. 252–259.","mla":"Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor in a PC’s Memory Slot.” <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>, IEEE Computer Society, 2003, pp. 252–59, doi:<a href=\"https://doi.org/10.1109/FPT.2003.1275755\">10.1109/FPT.2003.1275755</a>.","bibtex":"@inproceedings{Plessl_Platzner_2003, title={TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot}, DOI={<a href=\"https://doi.org/10.1109/FPT.2003.1275755\">10.1109/FPT.2003.1275755</a>}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={252–259} }","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2003, pp. 252–259."},"keyword":["coprocessor","DIMM","memory bus","FPGA","high performance computing"],"user_id":"24135","year":"2003","type":"conference","status":"public","date_created":"2018-04-17T15:03:34Z","publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)","publisher":"IEEE Computer Society","date_updated":"2022-01-06T06:56:09Z","page":"252-259","_id":"2418"},{"extern":"1","title":"The Case for Reconfigurable Hardware in Wearable Computing","doi":"10.1007/s00779-003-0243-x","abstract":[{"lang":"eng","text":"Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM."}],"user_id":"398","publication":"Personal and Ubiquitous Computing","type":"journal_article","volume":7,"page":"299-308","issue":"5","author":[{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Enzler","first_name":"Rolf","full_name":"Enzler, Rolf"},{"last_name":"Walder","first_name":"Herbert","full_name":"Walder, Herbert"},{"full_name":"Beutel, Jan","first_name":"Jan","last_name":"Beutel"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"},{"full_name":"Thiele, Lothar","first_name":"Lothar","last_name":"Thiele"},{"last_name":"Tröster","full_name":"Tröster, Gerhard","first_name":"Gerhard"}],"intvolume":"         7","citation":{"short":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, G. Tröster, Personal and Ubiquitous Computing 7 (2003) 299–308.","mla":"Plessl, Christian, et al. “The Case for Reconfigurable Hardware in Wearable Computing.” <i>Personal and Ubiquitous Computing</i>, vol. 7, no. 5, Springer, 2003, pp. 299–308, doi:<a href=\"https://doi.org/10.1007/s00779-003-0243-x\">10.1007/s00779-003-0243-x</a>.","bibtex":"@article{Plessl_Enzler_Walder_Beutel_Platzner_Thiele_Tröster_2003, title={The Case for Reconfigurable Hardware in Wearable Computing}, volume={7}, DOI={<a href=\"https://doi.org/10.1007/s00779-003-0243-x\">10.1007/s00779-003-0243-x</a>}, number={5}, journal={Personal and Ubiquitous Computing}, publisher={Springer}, author={Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar and Tröster, Gerhard}, year={2003}, pages={299–308} }","chicago":"Plessl, Christian, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, Lothar Thiele, and Gerhard Tröster. “The Case for Reconfigurable Hardware in Wearable Computing.” <i>Personal and Ubiquitous Computing</i> 7, no. 5 (2003): 299–308. <a href=\"https://doi.org/10.1007/s00779-003-0243-x\">https://doi.org/10.1007/s00779-003-0243-x</a>.","ieee":"C. Plessl <i>et al.</i>, “The Case for Reconfigurable Hardware in Wearable Computing,” <i>Personal and Ubiquitous Computing</i>, vol. 7, no. 5, pp. 299–308, 2003.","apa":"Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., Thiele, L., &#38; Tröster, G. (2003). The Case for Reconfigurable Hardware in Wearable Computing. <i>Personal and Ubiquitous Computing</i>, <i>7</i>(5), 299–308. <a href=\"https://doi.org/10.1007/s00779-003-0243-x\">https://doi.org/10.1007/s00779-003-0243-x</a>","ama":"Plessl C, Enzler R, Walder H, et al. The Case for Reconfigurable Hardware in Wearable Computing. <i>Personal and Ubiquitous Computing</i>. 2003;7(5):299-308. doi:<a href=\"https://doi.org/10.1007/s00779-003-0243-x\">10.1007/s00779-003-0243-x</a>"},"department":[{"_id":"518"},{"_id":"78"}],"publisher":"Springer","date_created":"2018-04-17T15:04:47Z","status":"public","language":[{"iso":"eng"}],"year":"2003","_id":"2419","date_updated":"2022-01-06T06:56:09Z"},{"author":[{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"intvolume":"        26","citation":{"ama":"Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. <i>Journal of Supercomputing</i>. 2003;26(2):109-129. doi:<a href=\"https://doi.org/10.1023/a:1024443416592\">10.1023/a:1024443416592</a>","apa":"Plessl, C., &#38; Platzner, M. (2003). Instance-Specific Accelerators for Minimum Covering. <i>Journal of Supercomputing</i>, <i>26</i>(2), 109–129. <a href=\"https://doi.org/10.1023/a:1024443416592\">https://doi.org/10.1023/a:1024443416592</a>","chicago":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” <i>Journal of Supercomputing</i> 26, no. 2 (2003): 109–29. <a href=\"https://doi.org/10.1023/a:1024443416592\">https://doi.org/10.1023/a:1024443416592</a>.","ieee":"C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” <i>Journal of Supercomputing</i>, vol. 26, no. 2, pp. 109–129, 2003.","mla":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” <i>Journal of Supercomputing</i>, vol. 26, no. 2, Kluwer Academic Publishers, 2003, pp. 109–29, doi:<a href=\"https://doi.org/10.1023/a:1024443416592\">10.1023/a:1024443416592</a>.","bibtex":"@article{Plessl_Platzner_2003, title={Instance-Specific Accelerators for Minimum Covering}, volume={26}, DOI={<a href=\"https://doi.org/10.1023/a:1024443416592\">10.1023/a:1024443416592</a>}, number={2}, journal={Journal of Supercomputing}, publisher={Kluwer Academic Publishers}, author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={109–129} }","short":"C. Plessl, M. Platzner, Journal of Supercomputing 26 (2003) 109–129."},"department":[{"_id":"518"},{"_id":"78"}],"date_created":"2018-04-17T15:10:00Z","publisher":"Kluwer Academic Publishers","year":"2003","publication_identifier":{"issn":["0920-8542"]},"language":[{"iso":"eng"}],"status":"public","_id":"2420","date_updated":"2022-01-06T06:56:10Z","title":"Instance-Specific Accelerators for Minimum Covering","extern":"1","doi":"10.1023/a:1024443416592","abstract":[{"lang":"eng","text":" This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch \\& bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch \\& bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups. "}],"user_id":"398","keyword":["reconfigurable computing","instance-specific acceleration","minimum covering"],"publication":"Journal of Supercomputing","type":"journal_article","page":"109-129","volume":26,"issue":"2"}]