[{"citation":{"short":"R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2003, pp. 151–160.","mla":"Enzler, Rolf, et al. “Virtualizing Hardware with Multi-Context Reconfigurable Arrays.” <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, vol. 2778, Springer, 2003, pp. 151–60, doi:<a href=\"https://doi.org/10.1007/b12007\">10.1007/b12007</a>.","bibtex":"@inproceedings{Enzler_Plessl_Platzner_2003, series={Lecture Notes in Computer Science (LNCS)}, title={Virtualizing Hardware with Multi-Context Reconfigurable Arrays}, volume={2778}, DOI={<a href=\"https://doi.org/10.1007/b12007\">10.1007/b12007</a>}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2003}, pages={151–160}, collection={Lecture Notes in Computer Science (LNCS)} }","chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “Virtualizing Hardware with Multi-Context Reconfigurable Arrays.” In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2778:151–60. Lecture Notes in Computer Science (LNCS). Springer, 2003. <a href=\"https://doi.org/10.1007/b12007\">https://doi.org/10.1007/b12007</a>.","ieee":"R. Enzler, C. Plessl, and M. Platzner, “Virtualizing Hardware with Multi-Context Reconfigurable Arrays,” in <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2003, vol. 2778, pp. 151–160.","apa":"Enzler, R., Plessl, C., &#38; Platzner, M. (2003). Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i> (Vol. 2778, pp. 151–160). Springer. <a href=\"https://doi.org/10.1007/b12007\">https://doi.org/10.1007/b12007</a>","ama":"Enzler R, Plessl C, Platzner M. Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In: <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>. Vol 2778. Lecture Notes in Computer Science (LNCS). Springer; 2003:151-160. doi:<a href=\"https://doi.org/10.1007/b12007\">10.1007/b12007</a>"},"series_title":"Lecture Notes in Computer Science (LNCS)","keyword":["Zippy","multi-context","FPGA"],"user_id":"24135","department":[{"_id":"518"},{"_id":"78"}],"title":"Virtualizing Hardware with Multi-Context Reconfigurable Arrays","author":[{"full_name":"Enzler, Rolf","first_name":"Rolf","last_name":"Enzler"},{"id":"16153","last_name":"Plessl","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"abstract":[{"lang":"eng","text":"In contrast to processors, current reconfigurable devices totally lack programming models that would allow for device independent compilation and forward compatibility. The key to overcome this limitation is hardware virtualization. In this paper, we resort to a macro-pipelined execution model to achieve hardware virtualization for data streaming applications. As a hardware implementation we present a hybrid multi-context architecture that attaches a coarse-grained reconfigurable array to a host CPU. A co-simulation framework enables cycle-accurate simulation of the complete architecture. As a case study we map an FIR filter to our virtualized hardware model and evaluate different designs. We discuss the impact of the number of contexts and the feature of context state on the speedup and the CPU load."}],"doi":"10.1007/b12007","intvolume":"      2778","_id":"2421","page":"151-160","volume":2778,"date_updated":"2022-01-06T06:56:13Z","date_created":"2018-04-17T15:11:25Z","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","publisher":"Springer","type":"conference","year":"2003","status":"public"},{"department":[{"_id":"518"},{"_id":"78"}],"keyword":["Zippy","co-simulation"],"user_id":"24135","citation":{"short":"R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 174–180.","mla":"Enzler, Rolf, et al. “Co-Simulation of a Hybrid Multi-Context Architecture.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2003, pp. 174–80.","bibtex":"@inproceedings{Enzler_Plessl_Platzner_2003, title={Co-simulation of a Hybrid Multi-Context Architecture}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2003}, pages={174–180} }","chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “Co-Simulation of a Hybrid Multi-Context Architecture.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 174–80. CSREA Press, 2003.","ieee":"R. Enzler, C. Plessl, and M. Platzner, “Co-simulation of a Hybrid Multi-Context Architecture,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2003, pp. 174–180.","apa":"Enzler, R., Plessl, C., &#38; Platzner, M. (2003). Co-simulation of a Hybrid Multi-Context Architecture. In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i> (pp. 174–180). CSREA Press.","ama":"Enzler R, Plessl C, Platzner M. Co-simulation of a Hybrid Multi-Context Architecture. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2003:174-180."},"abstract":[{"text":"Reconfigurable computing architectures aim to dynamically adapt their hardware to the application at hand. As research shows, the time it takes to reconfigure the hardware forms an overhead that can significantly impair the benefits of hardware customization. Multi-context devices are one promising approach to overcome the limitations posed by long reconfiguration times. In contrast to more traditional reconfigurable architectures, multi-context devices hold several configurations on-chip. On demand, the device can quickly switch to another context. In this paper we present a co-simulation environment to investigate design trade-offs for hybrid multi-context architectures. Our architectural model comprises a reconfigurable unit closely coupled to a CPU core. As a case study, we discuss the implementation of a FIR filter partitioned into several contexts. We outline the mapping process and present simulation results for single- and multi-context reconfigurable units coupled with both embedded and high-end CPUs.","lang":"eng"}],"author":[{"last_name":"Enzler","first_name":"Rolf","full_name":"Enzler, Rolf"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"}],"title":"Co-simulation of a Hybrid Multi-Context Architecture","date_updated":"2022-01-06T06:56:13Z","page":"174-180","_id":"2422","status":"public","year":"2003","publication_identifier":{"isbn":["1-932415-05-X"]},"type":"conference","publisher":"CSREA Press","date_created":"2018-04-17T15:12:56Z","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)"},{"department":[{"_id":"518"},{"_id":"78"}],"keyword":["wearable computing"],"user_id":"24135","citation":{"ama":"Plessl C, Enzler R, Walder H, Beutel J, Platzner M, Thiele L. Reconfigurable Hardware in Wearable Computing Nodes. In: <i>Proc. Int. Symp. on Wearable Computers (ISWC)</i>. IEEE Computer Society; 2002:215-222. doi:<a href=\"https://doi.org/10.1109/ISWC.2002.1167250\">10.1109/ISWC.2002.1167250</a>","apa":"Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., &#38; Thiele, L. (2002). Reconfigurable Hardware in Wearable Computing Nodes. In <i>Proc. Int. Symp. on Wearable Computers (ISWC)</i> (pp. 215–222). IEEE Computer Society. <a href=\"https://doi.org/10.1109/ISWC.2002.1167250\">https://doi.org/10.1109/ISWC.2002.1167250</a>","chicago":"Plessl, Christian, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, and Lothar Thiele. “Reconfigurable Hardware in Wearable Computing Nodes.” In <i>Proc. Int. Symp. on Wearable Computers (ISWC)</i>, 215–22. IEEE Computer Society, 2002. <a href=\"https://doi.org/10.1109/ISWC.2002.1167250\">https://doi.org/10.1109/ISWC.2002.1167250</a>.","ieee":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, and L. Thiele, “Reconfigurable Hardware in Wearable Computing Nodes,” in <i>Proc. Int. Symp. on Wearable Computers (ISWC)</i>, 2002, pp. 215–222.","mla":"Plessl, Christian, et al. “Reconfigurable Hardware in Wearable Computing Nodes.” <i>Proc. Int. Symp. on Wearable Computers (ISWC)</i>, IEEE Computer Society, 2002, pp. 215–22, doi:<a href=\"https://doi.org/10.1109/ISWC.2002.1167250\">10.1109/ISWC.2002.1167250</a>.","bibtex":"@inproceedings{Plessl_Enzler_Walder_Beutel_Platzner_Thiele_2002, title={Reconfigurable Hardware in Wearable Computing Nodes}, DOI={<a href=\"https://doi.org/10.1109/ISWC.2002.1167250\">10.1109/ISWC.2002.1167250</a>}, booktitle={Proc. Int. Symp. on Wearable Computers (ISWC)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar}, year={2002}, pages={215–222} }","short":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, in: Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp. 215–222."},"doi":"10.1109/ISWC.2002.1167250","abstract":[{"text":"Wearable computers are embedded into the mobile environment of the human body. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with low energy consumption required to maximize battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss two experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we develop and evaluate task placement techniques used in the operating system layer of WURM.","lang":"eng"}],"author":[{"full_name":"Plessl, Christian","first_name":"Christian","last_name":"Plessl","id":"16153","orcid":"0000-0001-5728-9982"},{"last_name":"Enzler","first_name":"Rolf","full_name":"Enzler, Rolf"},{"full_name":"Walder, Herbert","first_name":"Herbert","last_name":"Walder"},{"full_name":"Beutel, Jan","first_name":"Jan","last_name":"Beutel"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"Thiele","first_name":"Lothar","full_name":"Thiele, Lothar"}],"title":"Reconfigurable Hardware in Wearable Computing Nodes","date_updated":"2022-01-06T06:56:13Z","_id":"2423","page":"215-222","status":"public","year":"2002","publication_identifier":{"isbn":["0-7695-1816-8"]},"type":"conference","publisher":"IEEE Computer Society","date_created":"2018-04-17T15:13:50Z","publication":"Proc. Int. Symp. on Wearable Computers (ISWC)"},{"page":"292-301","_id":"2424","volume":2438,"date_updated":"2022-01-06T06:56:13Z","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","date_created":"2018-04-17T15:14:39Z","publisher":"Springer","type":"conference","year":"2002","status":"public","series_title":"Lecture Notes in Computer Science (LNCS)","citation":{"bibtex":"@inproceedings{Dyer_Plessl_Platzner_2002, series={Lecture Notes in Computer Science (LNCS)}, title={Partially Reconfigurable Cores for Xilinx Virtex}, volume={2438}, DOI={<a href=\"https://doi.org/10.1007/3-540-46117-5\">10.1007/3-540-46117-5</a>}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Dyer, Matthias and Plessl, Christian and Platzner, Marco}, year={2002}, pages={292–301}, collection={Lecture Notes in Computer Science (LNCS)} }","mla":"Dyer, Matthias, et al. “Partially Reconfigurable Cores for Xilinx Virtex.” <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, vol. 2438, Springer, 2002, pp. 292–301, doi:<a href=\"https://doi.org/10.1007/3-540-46117-5\">10.1007/3-540-46117-5</a>.","short":"M. Dyer, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2002, pp. 292–301.","ama":"Dyer M, Plessl C, Platzner M. Partially Reconfigurable Cores for Xilinx Virtex. In: <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>. Vol 2438. Lecture Notes in Computer Science (LNCS). Springer; 2002:292-301. doi:<a href=\"https://doi.org/10.1007/3-540-46117-5\">10.1007/3-540-46117-5</a>","apa":"Dyer, M., Plessl, C., &#38; Platzner, M. (2002). Partially Reconfigurable Cores for Xilinx Virtex. In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i> (Vol. 2438, pp. 292–301). Springer. <a href=\"https://doi.org/10.1007/3-540-46117-5\">https://doi.org/10.1007/3-540-46117-5</a>","ieee":"M. Dyer, C. Plessl, and M. Platzner, “Partially Reconfigurable Cores for Xilinx Virtex,” in <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2002, vol. 2438, pp. 292–301.","chicago":"Dyer, Matthias, Christian Plessl, and Marco Platzner. “Partially Reconfigurable Cores for Xilinx Virtex.” In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2438:292–301. Lecture Notes in Computer Science (LNCS). Springer, 2002. <a href=\"https://doi.org/10.1007/3-540-46117-5\">https://doi.org/10.1007/3-540-46117-5</a>."},"user_id":"24135","keyword":["partial reconfiguration"],"department":[{"_id":"518"},{"_id":"78"}],"title":"Partially Reconfigurable Cores for Xilinx Virtex","author":[{"last_name":"Dyer","first_name":"Matthias","full_name":"Dyer, Matthias"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","last_name":"Plessl","id":"16153"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"abstract":[{"text":" Recent generations of high-density and high-speed FPGAs provide a sufficient capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid CPUs that combine standard CPU cores with reconfigurable coprocessors are an important subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded on demand while the CPU remains running. However, the lack of high-level design tools for partial reconfiguration makes practical implementations a challenging task. In this paper, we introduce a design flow to implement hybrid processors on Xilinx Virtex. The design flow is based on two techniques, virtual sockets and feed-through components, and can efficiently generate partial configurations from industry-quality cores. We discuss the design flow and present a fully operational audio streaming prototype to demonstrate its feasibility. ","lang":"eng"}],"intvolume":"      2438","doi":"10.1007/3-540-46117-5"},{"_id":"2425","page":"163-172","date_updated":"2022-01-06T06:56:13Z","publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","date_created":"2018-04-17T15:15:44Z","publisher":"IEEE Computer Society","year":"2002","type":"conference","status":"public","citation":{"chicago":"Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set Covering Problem.” In <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 163–72. IEEE Computer Society, 2002. <a href=\"https://doi.org/10.1109/FPGA.2002.1106671\">https://doi.org/10.1109/FPGA.2002.1106671</a>.","ieee":"C. Plessl and M. Platzner, “Custom Computing Machines for the Set Covering Problem,” in <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 2002, pp. 163–172.","apa":"Plessl, C., &#38; Platzner, M. (2002). Custom Computing Machines for the Set Covering Problem. In <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i> (pp. 163–172). IEEE Computer Society. <a href=\"https://doi.org/10.1109/FPGA.2002.1106671\">https://doi.org/10.1109/FPGA.2002.1106671</a>","ama":"Plessl C, Platzner M. Custom Computing Machines for the Set Covering Problem. In: <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>. IEEE Computer Society; 2002:163-172. doi:<a href=\"https://doi.org/10.1109/FPGA.2002.1106671\">10.1109/FPGA.2002.1106671</a>","short":"C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2002, pp. 163–172.","mla":"Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set Covering Problem.” <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, IEEE Computer Society, 2002, pp. 163–72, doi:<a href=\"https://doi.org/10.1109/FPGA.2002.1106671\">10.1109/FPGA.2002.1106671</a>.","bibtex":"@inproceedings{Plessl_Platzner_2002, title={Custom Computing Machines for the Set Covering Problem}, DOI={<a href=\"https://doi.org/10.1109/FPGA.2002.1106671\">10.1109/FPGA.2002.1106671</a>}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2002}, pages={163–172} }"},"user_id":"24135","department":[{"_id":"518"},{"_id":"78"}],"title":"Custom Computing Machines for the Set Covering Problem","author":[{"orcid":"0000-0001-5728-9982","first_name":"Christian","full_name":"Plessl, Christian","id":"16153","last_name":"Plessl"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"doi":"10.1109/FPGA.2002.1106671","abstract":[{"text":" We present instance-specific custom computing machines for the set covering problem. Four accelerator architectures are developed that implement branch \\& bound in 3-valued logic and many of the deduction techniques found in software solvers. We use set covering benchmarks from two-level logic minimization and Steiner triple systems to derive and discuss experimental results. The resulting raw speedups are in the order of four magnitudes on average. Finally, we propose a hybrid solver architecture that combines the raw speed of instance-specific reconfigurable hardware with flexible bounding schemes implemented in software. ","lang":"eng"}]},{"publisher":"CSREA Press","date_created":"2018-04-17T15:39:17Z","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","status":"public","type":"conference","year":"2001","page":"85-91","_id":"2428","date_updated":"2022-01-06T06:56:17Z","author":[{"orcid":"0000-0001-5728-9982","first_name":"Christian","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"}],"title":"Instance-Specific Accelerators for Minimum Covering","abstract":[{"lang":"eng","text":" In this paper we present instance-specific accelerators for minimum-cost covering problems. We first define the covering problem and discuss a branch&bound algorithm to solve it. Then we describe an instance-specific hardware architecture that implements branch&bound in 3-valued logic and uses reduction techniques usually found in software solvers. Results for small unate covering problems reveal significant raw speedups. "}],"keyword":["minimum covering","accelerator","funding-sundance"],"user_id":"24135","citation":{"ieee":"C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2001, pp. 85–91.","chicago":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 85–91. CSREA Press, 2001.","apa":"Plessl, C., &#38; Platzner, M. (2001). Instance-Specific Accelerators for Minimum Covering. In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i> (pp. 85–91). CSREA Press.","ama":"Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2001:85-91.","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91.","bibtex":"@inproceedings{Plessl_Platzner_2001, title={Instance-Specific Accelerators for Minimum Covering}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian and Platzner, Marco}, year={2001}, pages={85–91} }","mla":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2001, pp. 85–91."},"department":[{"_id":"518"},{"_id":"78"}]},{"department":[{"_id":"518"}],"citation":{"ieee":"C. Plessl and E. Wilde, “Server-Side-Techniken im Web – ein Überblick,” <i>iX</i>, pp. 88–93, 2001.","chicago":"Plessl, Christian, and Erik Wilde. “Server-Side-Techniken Im Web – Ein Überblick.” <i>IX</i>, 2001, 88–93.","apa":"Plessl, C., &#38; Wilde, E. (2001). Server-Side-Techniken im Web – ein Überblick. <i>IX</i>, 88–93.","ama":"Plessl C, Wilde E. Server-Side-Techniken im Web – ein Überblick. <i>iX</i>. 2001:88-93.","short":"C. Plessl, E. Wilde, IX (2001) 88–93.","bibtex":"@article{Plessl_Wilde_2001, title={Server-Side-Techniken im Web – ein Überblick}, journal={iX}, publisher={Heise Verlag}, author={Plessl, Christian and Wilde, Erik}, year={2001}, pages={88–93} }","mla":"Plessl, Christian, and Erik Wilde. “Server-Side-Techniken Im Web – Ein Überblick.” <i>IX</i>, Heise Verlag, 2001, pp. 88–93."},"user_id":"24135","title":"Server-Side-Techniken im Web – ein Überblick","author":[{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Wilde","first_name":"Erik","full_name":"Wilde, Erik"}],"date_updated":"2022-01-06T06:56:17Z","_id":"2429","page":"88-93","type":"journal_article","year":"2001","status":"public","publication":"iX","date_created":"2018-04-17T15:43:29Z","publisher":"Heise Verlag"},{"author":[{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"}],"title":"Reconfigurable Accelerators for Minimum Covering","abstract":[{"text":"In this report the design and implementation of an instance-specific accelerator for solving minimum covering problems will be presented. After an introduction to configurable computing in general, the minimum covering problem is defined and a branch and bound algorithm to solve it in software is presented. The remainder of the report shows how this branch and bound algorithm can be adopted to hardware. Specifically it is stressed how the various sophisticated strategies for deducing conditions for variables used by software solvers can be adopted to hardware and how a system which uses 3-valued logic to solve this problem can be designed. In addition to these considerations focusing on the architecture of the system, some important details of the actual implementation are given. A prototype has been implemented for showing the feasibility of the concept and for gaining information about speed and size of the hardware implementation. Cycle-accurate simulations for a set of benchmark problems have been done for determining the performance of the accelerator. The speed of the resulting accelerators has been compared to the time a reference software solver (espresso) needs and the resulting speedups have been calculated. I have shown that a raw speedup of several orders of maginitude can be achieved for many problems; for some problems no speedup is achieved yet. After a discussion of the results, ideas for future work are presented.","lang":"eng"}],"user_id":"24135","citation":{"mla":"Plessl, Christian. <i>Reconfigurable Accelerators for Minimum Covering</i>. Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2001.","bibtex":"@book{Plessl_2001, title={Reconfigurable Accelerators for Minimum Covering}, publisher={Computer Engineering and Networks Lab, ETH Zurich, Switzerland}, author={Plessl, Christian}, year={2001} }","short":"C. Plessl, Reconfigurable Accelerators for Minimum Covering, Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2001.","ama":"Plessl C. <i>Reconfigurable Accelerators for Minimum Covering</i>. Computer Engineering and Networks Lab, ETH Zurich, Switzerland; 2001.","apa":"Plessl, C. (2001). <i>Reconfigurable Accelerators for Minimum Covering</i>. Computer Engineering and Networks Lab, ETH Zurich, Switzerland.","chicago":"Plessl, Christian. <i>Reconfigurable Accelerators for Minimum Covering</i>. Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2001.","ieee":"C. Plessl, <i>Reconfigurable Accelerators for Minimum Covering</i>. Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2001."},"department":[{"_id":"518"}],"publisher":"Computer Engineering and Networks Lab, ETH Zurich, Switzerland","date_created":"2018-04-17T15:47:26Z","status":"public","type":"mastersthesis","year":"2001","_id":"2430","date_updated":"2022-01-06T06:56:17Z"},{"volume":4525,"page":"135-146","_id":"2432","date_updated":"2022-01-06T06:56:17Z","publication":"Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III","date_created":"2018-04-17T15:51:39Z","status":"public","year":"2001","type":"conference","user_id":"24135","keyword":["benchmark"],"series_title":"Proc. SPIE","citation":{"bibtex":"@inproceedings{Enzler_Platzner_Plessl_Thiele_Tröster_2001, series={Proc. SPIE}, title={Reconfigurable Processors for Handhelds and Wearables: Application Analysis}, volume={4525}, DOI={<a href=\"https://doi.org/10.1117/12.434376\">10.1117/12.434376</a>}, booktitle={Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III}, author={Enzler, Rolf and Platzner, Marco and Plessl, Christian and Thiele, Lothar and Tröster, Gerhard}, year={2001}, pages={135–146}, collection={Proc. SPIE} }","mla":"Enzler, Rolf, et al. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.” <i>Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III</i>, vol. 4525, 2001, pp. 135–46, doi:<a href=\"https://doi.org/10.1117/12.434376\">10.1117/12.434376</a>.","short":"R. Enzler, M. Platzner, C. Plessl, L. Thiele, G. Tröster, in: Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 2001, pp. 135–146.","apa":"Enzler, R., Platzner, M., Plessl, C., Thiele, L., &#38; Tröster, G. (2001). Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In <i>Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III</i> (Vol. 4525, pp. 135–146). <a href=\"https://doi.org/10.1117/12.434376\">https://doi.org/10.1117/12.434376</a>","ama":"Enzler R, Platzner M, Plessl C, Thiele L, Tröster G. Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In: <i>Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III</i>. Vol 4525. Proc. SPIE. ; 2001:135-146. doi:<a href=\"https://doi.org/10.1117/12.434376\">10.1117/12.434376</a>","ieee":"R. Enzler, M. Platzner, C. Plessl, L. Thiele, and G. Tröster, “Reconfigurable Processors for Handhelds and Wearables: Application Analysis,” in <i>Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III</i>, 2001, vol. 4525, pp. 135–146.","chicago":"Enzler, Rolf, Marco Platzner, Christian Plessl, Lothar Thiele, and Gerhard Tröster. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.” In <i>Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III</i>, 4525:135–46. Proc. SPIE, 2001. <a href=\"https://doi.org/10.1117/12.434376\">https://doi.org/10.1117/12.434376</a>."},"department":[{"_id":"518"},{"_id":"78"}],"author":[{"first_name":"Rolf","full_name":"Enzler, Rolf","last_name":"Enzler"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","first_name":"Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Thiele","full_name":"Thiele, Lothar","first_name":"Lothar"},{"last_name":"Tröster","full_name":"Tröster, Gerhard","first_name":"Gerhard"}],"title":"Reconfigurable Processors for Handhelds and Wearables: Application Analysis","doi":"10.1117/12.434376","abstract":[{"lang":"eng","text":"In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurable processors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core."}],"intvolume":"      4525"},{"_id":"2433","date_updated":"2022-01-06T06:56:17Z","date_created":"2018-04-17T15:56:00Z","publisher":"Computer Engineering and Networks Lab, ETH Zurich, Switzerland","year":"2000","type":"mastersthesis","status":"public","citation":{"ieee":"C. Plessl and S. Maurer, <i>Hardware/Software Codesign in Speech Compression Applications</i>. Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2000.","chicago":"Plessl, Christian, and Simon Maurer. <i>Hardware/Software Codesign in Speech Compression Applications</i>. Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2000.","apa":"Plessl, C., &#38; Maurer, S. (2000). <i>Hardware/Software Codesign in Speech Compression Applications</i>. Computer Engineering and Networks Lab, ETH Zurich, Switzerland.","ama":"Plessl C, Maurer S. <i>Hardware/Software Codesign in Speech Compression Applications</i>. Computer Engineering and Networks Lab, ETH Zurich, Switzerland; 2000.","short":"C. Plessl, S. Maurer, Hardware/Software Codesign in Speech Compression Applications, Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2000.","bibtex":"@book{Plessl_Maurer_2000, title={Hardware/Software Codesign in Speech Compression Applications}, publisher={Computer Engineering and Networks Lab, ETH Zurich, Switzerland}, author={Plessl, Christian and Maurer, Simon}, year={2000} }","mla":"Plessl, Christian, and Simon Maurer. <i>Hardware/Software Codesign in Speech Compression Applications</i>. Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2000."},"user_id":"24135","keyword":["co-design","speech processing"],"department":[{"_id":"518"}],"title":"Hardware/Software Codesign in Speech Compression Applications","author":[{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Maurer","first_name":"Simon","full_name":"Maurer, Simon"}]}]