[{"article_number":"082003","language":[{"iso":"eng"}],"_id":"1589","department":[{"_id":"27"},{"_id":"518"}],"user_id":"15278","status":"public","publication":"Journal of Physics: Conference Series","type":"journal_article","title":"High-Throughput and Low-Latency Network Communication with NetIO","doi":"10.1088/1742-6596/898/8/082003","date_updated":"2023-09-26T13:24:19Z","publisher":"IOP Publishing","volume":898,"author":[{"full_name":"Schumacher, Jörn","last_name":"Schumacher","first_name":"Jörn"},{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"},{"last_name":"Vandelli","full_name":"Vandelli, Wainer","first_name":"Wainer"}],"date_created":"2018-03-22T10:51:20Z","year":"2017","intvolume":"       898","citation":{"ieee":"J. Schumacher, C. Plessl, and W. Vandelli, “High-Throughput and Low-Latency Network Communication with NetIO,” <i>Journal of Physics: Conference Series</i>, vol. 898, Art. no. 082003, 2017, doi: <a href=\"https://doi.org/10.1088/1742-6596/898/8/082003\">10.1088/1742-6596/898/8/082003</a>.","chicago":"Schumacher, Jörn, Christian Plessl, and Wainer Vandelli. “High-Throughput and Low-Latency Network Communication with NetIO.” <i>Journal of Physics: Conference Series</i> 898 (2017). <a href=\"https://doi.org/10.1088/1742-6596/898/8/082003\">https://doi.org/10.1088/1742-6596/898/8/082003</a>.","ama":"Schumacher J, Plessl C, Vandelli W. High-Throughput and Low-Latency Network Communication with NetIO. <i>Journal of Physics: Conference Series</i>. 2017;898. doi:<a href=\"https://doi.org/10.1088/1742-6596/898/8/082003\">10.1088/1742-6596/898/8/082003</a>","apa":"Schumacher, J., Plessl, C., &#38; Vandelli, W. (2017). High-Throughput and Low-Latency Network Communication with NetIO. <i>Journal of Physics: Conference Series</i>, <i>898</i>, Article 082003. <a href=\"https://doi.org/10.1088/1742-6596/898/8/082003\">https://doi.org/10.1088/1742-6596/898/8/082003</a>","mla":"Schumacher, Jörn, et al. “High-Throughput and Low-Latency Network Communication with NetIO.” <i>Journal of Physics: Conference Series</i>, vol. 898, 082003, IOP Publishing, 2017, doi:<a href=\"https://doi.org/10.1088/1742-6596/898/8/082003\">10.1088/1742-6596/898/8/082003</a>.","short":"J. Schumacher, C. Plessl, W. Vandelli, Journal of Physics: Conference Series 898 (2017).","bibtex":"@article{Schumacher_Plessl_Vandelli_2017, title={High-Throughput and Low-Latency Network Communication with NetIO}, volume={898}, DOI={<a href=\"https://doi.org/10.1088/1742-6596/898/8/082003\">10.1088/1742-6596/898/8/082003</a>}, number={082003}, journal={Journal of Physics: Conference Series}, publisher={IOP Publishing}, author={Schumacher, Jörn and Plessl, Christian and Vandelli, Wainer}, year={2017} }"},"quality_controlled":"1"},{"language":[{"iso":"eng"}],"publication":"FPGAs for Software Programmers","abstract":[{"text":"In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems.","lang":"eng"}],"date_created":"2017-07-26T15:07:06Z","publisher":"Springer International Publishing","title":"ReconOS","quality_controlled":"1","year":"2016","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","_id":"29","project":[{"grant_number":"257906","_id":"31","name":"Engineering Proprioception in Computing Systems"}],"type":"book_chapter","status":"public","editor":[{"full_name":"Koch, Dirk","last_name":"Koch","first_name":"Dirk"},{"full_name":"Hannig, Frank","last_name":"Hannig","first_name":"Frank"},{"last_name":"Ziener","full_name":"Ziener, Daniel","first_name":"Daniel"}],"author":[{"full_name":"Agne, Andreas","last_name":"Agne","first_name":"Andreas"},{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"},{"id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"first_name":"Markus","last_name":"Happe","full_name":"Happe, Markus"},{"full_name":"Lübbers, Enno","last_name":"Lübbers","first_name":"Enno"}],"date_updated":"2023-09-26T13:25:38Z","doi":"10.1007/978-3-319-26408-0_13","publication_identifier":{"isbn":["978-3-319-26406-6","978-3-319-26408-0"]},"publication_status":"published","page":"227-244","citation":{"mla":"Agne, Andreas, et al. “ReconOS.” <i>FPGAs for Software Programmers</i>, edited by Dirk Koch et al., Springer International Publishing, 2016, pp. 227–44, doi:<a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">10.1007/978-3-319-26408-0_13</a>.","bibtex":"@inbook{Agne_Platzner_Plessl_Happe_Lübbers_2016, place={Cham}, title={ReconOS}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">10.1007/978-3-319-26408-0_13</a>}, booktitle={FPGAs for Software Programmers}, publisher={Springer International Publishing}, author={Agne, Andreas and Platzner, Marco and Plessl, Christian and Happe, Markus and Lübbers, Enno}, editor={Koch, Dirk and Hannig, Frank and Ziener, Daniel}, year={2016}, pages={227–244} }","short":"A. Agne, M. Platzner, C. Plessl, M. Happe, E. Lübbers, in: D. Koch, F. Hannig, D. Ziener (Eds.), FPGAs for Software Programmers, Springer International Publishing, Cham, 2016, pp. 227–244.","apa":"Agne, A., Platzner, M., Plessl, C., Happe, M., &#38; Lübbers, E. (2016). ReconOS. In D. Koch, F. Hannig, &#38; D. Ziener (Eds.), <i>FPGAs for Software Programmers</i> (pp. 227–244). Springer International Publishing. <a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">https://doi.org/10.1007/978-3-319-26408-0_13</a>","chicago":"Agne, Andreas, Marco Platzner, Christian Plessl, Markus Happe, and Enno Lübbers. “ReconOS.” In <i>FPGAs for Software Programmers</i>, edited by Dirk Koch, Frank Hannig, and Daniel Ziener, 227–44. Cham: Springer International Publishing, 2016. <a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">https://doi.org/10.1007/978-3-319-26408-0_13</a>.","ieee":"A. Agne, M. Platzner, C. Plessl, M. Happe, and E. Lübbers, “ReconOS,” in <i>FPGAs for Software Programmers</i>, D. Koch, F. Hannig, and D. Ziener, Eds. Cham: Springer International Publishing, 2016, pp. 227–244.","ama":"Agne A, Platzner M, Plessl C, Happe M, Lübbers E. ReconOS. In: Koch D, Hannig F, Ziener D, eds. <i>FPGAs for Software Programmers</i>. Springer International Publishing; 2016:227-244. doi:<a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">10.1007/978-3-319-26408-0_13</a>"},"place":"Cham"},{"file":[{"content_type":"application/pdf","relation":"main_file","success":1,"creator":"deffel","date_created":"2019-01-11T11:56:55Z","date_updated":"2019-01-11T11:56:55Z","file_id":"6626","access_level":"closed","file_name":"wrc_upb_polimi_final.pdf","file_size":394563}],"status":"public","type":"conference","publication":"Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)","file_date_updated":"2019-01-11T11:56:55Z","language":[{"iso":"eng"}],"ddc":["040"],"user_id":"15278","department":[{"_id":"27"},{"_id":"518"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2","grant_number":"160364472"},{"grant_number":"610996","_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"_id":"31","citation":{"apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., &#38; Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. <i>Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)</i>.","short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, C. Bolchini, in: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” <i>Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)</i>, 2016.","bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, booktitle={Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Bolchini, Cristiana}, year={2016} }","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, and Cristiana Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In <i>Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)</i>, 2016.","ieee":"H. Riebler, G. F. Vaz, C. Plessl, E. M. G. Trainiti, G. C. Durelli, and C. Bolchini, “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” 2016.","ama":"Riebler H, Vaz GF, Plessl C, Trainiti EMG, Durelli GC, Bolchini C. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: <i>Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)</i>. ; 2016."},"year":"2016","quality_controlled":"1","has_accepted_license":"1","title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","date_created":"2017-07-26T15:16:31Z","author":[{"first_name":"Heinrich","id":"8961","full_name":"Riebler, Heinrich","last_name":"Riebler"},{"last_name":"Vaz","id":"30332","full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis"},{"full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"},{"last_name":"Trainiti","full_name":"Trainiti, Ettore M. G.","first_name":"Ettore M. G."},{"full_name":"Durelli, Gianluca C.","last_name":"Durelli","first_name":"Gianluca C."},{"first_name":"Cristiana","full_name":"Bolchini, Cristiana","last_name":"Bolchini"}],"date_updated":"2023-09-26T13:25:59Z"},{"title":"Microdisk Cavity FDTD Simulation on FPGA using OpenCL","date_created":"2017-07-26T15:00:43Z","author":[{"first_name":"Tobias","id":"3145","full_name":"Kenter, Tobias","last_name":"Kenter"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian"}],"date_updated":"2023-09-26T13:26:17Z","citation":{"ama":"Kenter T, Plessl C. Microdisk Cavity FDTD Simulation on FPGA using OpenCL. In: <i>Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC)</i>. ; 2016.","chicago":"Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” In <i>Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC)</i>, 2016.","ieee":"T. Kenter and C. Plessl, “Microdisk Cavity FDTD Simulation on FPGA using OpenCL,” 2016.","apa":"Kenter, T., &#38; Plessl, C. (2016). Microdisk Cavity FDTD Simulation on FPGA using OpenCL. <i>Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC)</i>.","short":"T. Kenter, C. Plessl, in: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.","mla":"Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” <i>Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC)</i>, 2016.","bibtex":"@inproceedings{Kenter_Plessl_2016, title={Microdisk Cavity FDTD Simulation on FPGA using OpenCL}, booktitle={Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Kenter, Tobias and Plessl, Christian}, year={2016} }"},"year":"2016","quality_controlled":"1","has_accepted_license":"1","file_date_updated":"2018-11-14T12:38:45Z","language":[{"iso":"eng"}],"ddc":["004"],"user_id":"15278","department":[{"_id":"27"},{"_id":"518"}],"project":[{"_id":"32","name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1 / 320898746"},{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901 - Subproject C2","_id":"14","grant_number":"160364472"}],"_id":"24","file":[{"content_type":"application/pdf","success":1,"relation":"main_file","date_updated":"2018-11-14T12:38:45Z","creator":"kenter","date_created":"2018-11-14T12:38:45Z","file_size":129552,"file_name":"paper_26.pdf","access_level":"closed","file_id":"5602"}],"status":"public","type":"conference","publication":"Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)"},{"status":"public","publication":"Workshop on Approximate Computing (AC)","type":"conference","language":[{"iso":"eng"}],"_id":"25","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"user_id":"15278","year":"2016","citation":{"short":"M. Lass, T. Kühne, C. Plessl, in: Workshop on Approximate Computing (AC), 2016.","bibtex":"@inproceedings{Lass_Kühne_Plessl_2016, title={Using Approximate Computing in Scientific Codes}, booktitle={Workshop on Approximate Computing (AC)}, author={Lass, Michael and Kühne, Thomas and Plessl, Christian}, year={2016} }","mla":"Lass, Michael, et al. “Using Approximate Computing in Scientific Codes.” <i>Workshop on Approximate Computing (AC)</i>, 2016.","apa":"Lass, M., Kühne, T., &#38; Plessl, C. (2016). Using Approximate Computing in Scientific Codes. <i>Workshop on Approximate Computing (AC)</i>.","ama":"Lass M, Kühne T, Plessl C. Using Approximate Computing in Scientific Codes. In: <i>Workshop on Approximate Computing (AC)</i>. ; 2016.","chicago":"Lass, Michael, Thomas Kühne, and Christian Plessl. “Using Approximate Computing in Scientific Codes.” In <i>Workshop on Approximate Computing (AC)</i>, 2016.","ieee":"M. Lass, T. Kühne, and C. Plessl, “Using Approximate Computing in Scientific Codes,” 2016."},"quality_controlled":"1","title":"Using Approximate Computing in Scientific Codes","date_updated":"2023-09-26T13:25:17Z","author":[{"first_name":"Michael","orcid":"0000-0002-5708-7632","last_name":"Lass","id":"24135","full_name":"Lass, Michael"},{"first_name":"Thomas","full_name":"Kühne, Thomas","id":"49079","last_name":"Kühne"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"}],"date_created":"2017-07-26T15:02:20Z"},{"year":"2016","page":"1-5","citation":{"bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Del Sozzo_Santambrogio_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, DOI={<a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">10.1109/RTSI.2016.7740545</a>}, booktitle={Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)}, publisher={IEEE}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G.  and Durelli, Gianluca C. and Del Sozzo, Emanuele and Santambrogio, Marco D.  and Bolchini, Christina}, year={2016}, pages={1–5} }","mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>, IEEE, 2016, pp. 1–5, doi:<a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">10.1109/RTSI.2016.7740545</a>.","short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, E. Del Sozzo, M.D. Santambrogio, C. Bolchini, in: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5.","apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., Del Sozzo, E., Santambrogio, M. D., &#38; Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>, 1–5. <a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">https://doi.org/10.1109/RTSI.2016.7740545</a>","ama":"Riebler H, Vaz GF, Plessl C, et al. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>. IEEE; 2016:1-5. doi:<a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">10.1109/RTSI.2016.7740545</a>","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G.  Trainiti, Gianluca C. Durelli, Emanuele Del Sozzo, Marco D.  Santambrogio, and Christina Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>, 1–5. IEEE, 2016. <a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">https://doi.org/10.1109/RTSI.2016.7740545</a>.","ieee":"H. Riebler <i>et al.</i>, “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” in <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>, 2016, pp. 1–5, doi: <a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">10.1109/RTSI.2016.7740545</a>."},"has_accepted_license":"1","quality_controlled":"1","title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","doi":"10.1109/RTSI.2016.7740545","publisher":"IEEE","date_updated":"2023-09-26T13:28:11Z","author":[{"id":"8961","full_name":"Riebler, Heinrich","last_name":"Riebler","first_name":"Heinrich"},{"first_name":"Gavin Francis","last_name":"Vaz","full_name":"Vaz, Gavin Francis","id":"30332"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"full_name":"Trainiti, Ettore M. G. ","last_name":"Trainiti","first_name":"Ettore M. G. "},{"last_name":"Durelli","full_name":"Durelli, Gianluca C.","first_name":"Gianluca C."},{"first_name":"Emanuele","last_name":"Del Sozzo","full_name":"Del Sozzo, Emanuele"},{"full_name":"Santambrogio, Marco D. ","last_name":"Santambrogio","first_name":"Marco D. "},{"full_name":"Bolchini, Christina","last_name":"Bolchini","first_name":"Christina"}],"date_created":"2017-10-17T12:41:18Z","abstract":[{"lang":"eng","text":"Hardware accelerators are becoming popular in academia and industry. To move one step further from the state-of-the-art multicore plus accelerator approaches, we present in this paper our innovative SAVEHSA architecture. It comprises of a heterogeneous hardware platform with three different high-end accelerators attached over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads very efficiently whilst being more energy efficient than regular CPU systems. To leverage the heterogeneity, the workload has to be distributed among the computing units in a way that each unit is well-suited for the assigned task and executable code must be available. To tackle this problem we present two software components; the first can perform resource allocation at runtime while respecting system and application goals (in terms of throughput, energy, latency, etc.) and the second is able to analyze an application and generate executable code for an accelerator at runtime. We demonstrate the first proof-of-concept implementation of our framework on the heterogeneous platform, discuss different runtime policies and measure the introduced overheads."}],"status":"public","file":[{"file_size":184334,"access_level":"closed","file_id":"1560","file_name":"138-07740545.pdf","date_updated":"2018-03-21T13:01:09Z","date_created":"2018-03-21T13:01:09Z","creator":"florida","success":1,"relation":"main_file","content_type":"application/pdf"}],"publication":"Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)","type":"conference","ddc":["040"],"file_date_updated":"2018-03-21T13:01:09Z","language":[{"iso":"eng"}],"_id":"138","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"department":[{"_id":"27"},{"_id":"518"}],"user_id":"15278"},{"citation":{"apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., &#38; Platzner, M. (2016). Self-aware Compute Nodes. In <i>Self-aware Computing Systems</i> (pp. 145–165). Springer International Publishing. <a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">https://doi.org/10.1007/978-3-319-39675-0_8</a>","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, in: Self-Aware Computing Systems, Springer International Publishing, Cham, 2016, pp. 145–165.","bibtex":"@inbook{Agne_Happe_Lösch_Plessl_Platzner_2016, place={Cham}, series={Natural Computing Series (NCS)}, title={Self-aware Compute Nodes}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">10.1007/978-3-319-39675-0_8</a>}, booktitle={Self-aware Computing Systems}, publisher={Springer International Publishing}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2016}, pages={145–165}, collection={Natural Computing Series (NCS)} }","mla":"Agne, Andreas, et al. “Self-Aware Compute Nodes.” <i>Self-Aware Computing Systems</i>, Springer International Publishing, 2016, pp. 145–65, doi:<a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">10.1007/978-3-319-39675-0_8</a>.","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Aware Compute Nodes.” In <i>Self-Aware Computing Systems</i>, 145–65. Natural Computing Series (NCS). Cham: Springer International Publishing, 2016. <a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">https://doi.org/10.1007/978-3-319-39675-0_8</a>.","ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-aware Compute Nodes,” in <i>Self-aware Computing Systems</i>, Cham: Springer International Publishing, 2016, pp. 145–165.","ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-aware Compute Nodes. In: <i>Self-Aware Computing Systems</i>. Natural Computing Series (NCS). Springer International Publishing; 2016:145-165. doi:<a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">10.1007/978-3-319-39675-0_8</a>"},"page":"145-165","place":"Cham","has_accepted_license":"1","doi":"10.1007/978-3-319-39675-0_8","author":[{"full_name":"Agne, Andreas","last_name":"Agne","first_name":"Andreas"},{"full_name":"Happe, Markus","last_name":"Happe","first_name":"Markus"},{"first_name":"Achim","last_name":"Lösch","id":"43646","full_name":"Lösch, Achim"},{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"}],"date_updated":"2023-09-26T13:27:44Z","status":"public","type":"book_chapter","file_date_updated":"2018-11-14T13:20:32Z","series_title":"Natural Computing Series (NCS)","user_id":"15278","department":[{"_id":"518"},{"_id":"27"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"_id":"156","year":"2016","quality_controlled":"1","title":"Self-aware Compute Nodes","date_created":"2017-10-17T12:41:22Z","publisher":"Springer International Publishing","file":[{"access_level":"closed","file_name":"chapter8.pdf","file_id":"5613","file_size":833054,"creator":"aloesch","date_created":"2018-11-14T13:20:32Z","date_updated":"2018-11-14T13:20:32Z","relation":"main_file","success":1,"content_type":"application/pdf"}],"abstract":[{"lang":"eng","text":"Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level."}],"publication":"Self-aware Computing Systems","language":[{"iso":"eng"}],"ddc":["040"]},{"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"_id":"165","user_id":"15278","department":[{"_id":"27"},{"_id":"518"}],"file_date_updated":"2018-03-21T12:45:47Z","type":"journal_article","status":"public","date_updated":"2023-09-26T13:26:38Z","author":[{"last_name":"Vaz","full_name":"Vaz, Gavin Francis","id":"30332","first_name":"Gavin Francis"},{"first_name":"Heinrich","last_name":"Riebler","id":"8961","full_name":"Riebler, Heinrich"},{"first_name":"Tobias","full_name":"Kenter, Tobias","id":"3145","last_name":"Kenter"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"}],"volume":55,"doi":"10.1016/j.compeleceng.2016.04.021","publication_identifier":{"issn":["0045-7906"]},"has_accepted_license":"1","citation":{"ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. <i>Computers and Electrical Engineering</i>. 2016;55:91-111. doi:<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">10.1016/j.compeleceng.2016.04.021</a>","ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code,” <i>Computers and Electrical Engineering</i>, vol. 55, pp. 91–111, 2016, doi: <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">10.1016/j.compeleceng.2016.04.021</a>.","chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” <i>Computers and Electrical Engineering</i> 55 (2016): 91–111. <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">https://doi.org/10.1016/j.compeleceng.2016.04.021</a>.","bibtex":"@article{Vaz_Riebler_Kenter_Plessl_2016, title={Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code}, volume={55}, DOI={<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">10.1016/j.compeleceng.2016.04.021</a>}, journal={Computers and Electrical Engineering}, publisher={Elsevier}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2016}, pages={91–111} }","mla":"Vaz, Gavin Francis, et al. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” <i>Computers and Electrical Engineering</i>, vol. 55, Elsevier, 2016, pp. 91–111, doi:<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">10.1016/j.compeleceng.2016.04.021</a>.","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, Computers and Electrical Engineering 55 (2016) 91–111.","apa":"Vaz, G. F., Riebler, H., Kenter, T., &#38; Plessl, C. (2016). Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. <i>Computers and Electrical Engineering</i>, <i>55</i>, 91–111. <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">https://doi.org/10.1016/j.compeleceng.2016.04.021</a>"},"page":"91-111","intvolume":"        55","ddc":["040"],"language":[{"iso":"eng"}],"publication":"Computers and Electrical Engineering","abstract":[{"lang":"eng","text":"A broad spectrum of applications can be accelerated by offloading computation intensive parts to reconfigurable hardware. However, to achieve speedups, the number of loop it- erations (trip count) needs to be sufficiently large to amortize offloading overheads. Trip counts are frequently not known at compile time, but only at runtime just before entering a loop. Therefore, we propose to generate code for both the CPU and the coprocessor, and defer the offloading decision to the application runtime. We demonstrate how a toolflow, based on the LLVM compiler framework, can automatically embed dynamic offloading de- cisions into the application code. We perform in-depth static and dynamic analysis of pop- ular benchmarks, which confirm the general potential of such an approach. We also pro- pose to optimize the offloading process by decoupling the runtime decision from the loop execution (decision slack). The feasibility of our approach is demonstrated by a toolflow that automatically identifies suitable data-parallel loops and generates code for the FPGA coprocessor of a Convey HC-1. We evaluate the integrated toolflow with representative loops executed for different input data sizes."}],"file":[{"date_updated":"2018-03-21T12:45:47Z","date_created":"2018-03-21T12:45:47Z","creator":"florida","file_size":3037854,"file_name":"165-1-s2.0-S0045790616301021-main.pdf","access_level":"closed","file_id":"1544","content_type":"application/pdf","success":1,"relation":"main_file"}],"publisher":"Elsevier","date_created":"2017-10-17T12:41:24Z","title":"Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code","quality_controlled":"1","year":"2016"},{"publisher":"EDA Consortium / IEEE","date_created":"2017-10-17T12:41:24Z","title":"Performance-centric scheduling with task migration for a heterogeneous compute node in the data center","quality_controlled":"1","year":"2016","ddc":["040"],"language":[{"iso":"eng"}],"publication":"Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","abstract":[{"text":"The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative.","lang":"eng"}],"file":[{"file_size":261356,"access_level":"closed","file_id":"1541","file_name":"168-07459438.pdf","date_updated":"2018-03-21T12:41:55Z","date_created":"2018-03-21T12:41:55Z","creator":"florida","success":1,"relation":"main_file","content_type":"application/pdf"}],"date_updated":"2023-09-26T13:27:00Z","author":[{"first_name":"Achim","last_name":"Lösch","full_name":"Lösch, Achim","id":"43646"},{"full_name":"Beisel, Tobias","last_name":"Beisel","first_name":"Tobias"},{"first_name":"Tobias","last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145"},{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"}],"has_accepted_license":"1","citation":{"ama":"Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: <i>Proceedings of the 2016 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>. EDA Consortium / IEEE; 2016:912-917.","ieee":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric scheduling with task migration for a heterogeneous compute node in the data center,” in <i>Proceedings of the 2016 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>, 2016, pp. 912–917.","chicago":"Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” In <i>Proceedings of the 2016 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>, 912–17. EDA Consortium / IEEE, 2016.","apa":"Lösch, A., Beisel, T., Kenter, T., Plessl, C., &#38; Platzner, M. (2016). Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. <i>Proceedings of the 2016 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>, 912–917.","short":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917.","bibtex":"@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric scheduling with task migration for a heterogeneous compute node in the data center}, booktitle={Proceedings of the 2016 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco}, year={2016}, pages={912–917} }","mla":"Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” <i>Proceedings of the 2016 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE)</i>, EDA Consortium / IEEE, 2016, pp. 912–17."},"page":"912-917","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"01|H11004A","_id":"30","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models"}],"_id":"168","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"file_date_updated":"2018-03-21T12:41:55Z","type":"conference","status":"public"},{"quality_controlled":"1","has_accepted_license":"1","year":"2016","citation":{"ama":"Kenter T, Vaz GF, Riebler H, Plessl C. Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). In: <i>Workshop on Reconfigurable Computing (WRC)</i>. ; 2016.","ieee":"T. Kenter, G. F. Vaz, H. Riebler, and C. Plessl, “Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract),” 2016.","chicago":"Kenter, Tobias, Gavin Francis Vaz, Heinrich Riebler, and Christian Plessl. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” In <i>Workshop on Reconfigurable Computing (WRC)</i>, 2016.","apa":"Kenter, T., Vaz, G. F., Riebler, H., &#38; Plessl, C. (2016). Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). <i>Workshop on Reconfigurable Computing (WRC)</i>.","mla":"Kenter, Tobias, et al. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” <i>Workshop on Reconfigurable Computing (WRC)</i>, 2016.","short":"T. Kenter, G.F. Vaz, H. Riebler, C. Plessl, in: Workshop on Reconfigurable Computing (WRC), 2016.","bibtex":"@inproceedings{Kenter_Vaz_Riebler_Plessl_2016, title={Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)}, booktitle={Workshop on Reconfigurable Computing (WRC)}, author={Kenter, Tobias and Vaz, Gavin Francis and Riebler, Heinrich and Plessl, Christian}, year={2016} }"},"date_updated":"2023-09-26T13:27:21Z","date_created":"2017-10-17T12:41:25Z","author":[{"last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias","first_name":"Tobias"},{"first_name":"Gavin Francis","last_name":"Vaz","id":"30332","full_name":"Vaz, Gavin Francis"},{"first_name":"Heinrich","id":"8961","full_name":"Riebler, Heinrich","last_name":"Riebler"},{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"}],"title":"Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)","publication":"Workshop on Reconfigurable Computing (WRC)","type":"conference","status":"public","file":[{"file_size":54421,"file_id":"1538","access_level":"closed","file_name":"171-plessl16_fpl_wrc.pdf","date_updated":"2018-03-21T12:39:46Z","date_created":"2018-03-21T12:39:46Z","creator":"florida","success":1,"relation":"main_file","content_type":"application/pdf"}],"_id":"171","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"}],"user_id":"15278","ddc":["040"],"file_date_updated":"2018-03-21T12:39:46Z","language":[{"iso":"eng"}]},{"doi":"10.1109/MC.2015.205","date_updated":"2022-01-06T06:53:19Z","author":[{"first_name":"Jim","full_name":"Torresen, Jim","last_name":"Torresen"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Xin","last_name":"Yao","full_name":"Yao, Xin"}],"volume":48,"citation":{"short":"J. Torresen, C. Plessl, X. Yao, IEEE Computer 48 (2015) 18–20.","bibtex":"@article{Torresen_Plessl_Yao_2015, title={Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction}, volume={48}, DOI={<a href=\"https://doi.org/10.1109/MC.2015.205\">10.1109/MC.2015.205</a>}, number={7}, journal={IEEE Computer}, publisher={IEEE Computer Society}, author={Torresen, Jim and Plessl, Christian and Yao, Xin}, year={2015}, pages={18–20} }","mla":"Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” <i>IEEE Computer</i>, vol. 48, no. 7, IEEE Computer Society, 2015, pp. 18–20, doi:<a href=\"https://doi.org/10.1109/MC.2015.205\">10.1109/MC.2015.205</a>.","apa":"Torresen, J., Plessl, C., &#38; Yao, X. (2015). Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. <i>IEEE Computer</i>, <i>48</i>(7), 18–20. <a href=\"https://doi.org/10.1109/MC.2015.205\">https://doi.org/10.1109/MC.2015.205</a>","chicago":"Torresen, Jim, Christian Plessl, and Xin Yao. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” <i>IEEE Computer</i> 48, no. 7 (2015): 18–20. <a href=\"https://doi.org/10.1109/MC.2015.205\">https://doi.org/10.1109/MC.2015.205</a>.","ieee":"J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction,” <i>IEEE Computer</i>, vol. 48, no. 7, pp. 18–20, 2015.","ama":"Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. <i>IEEE Computer</i>. 2015;48(7):18-20. doi:<a href=\"https://doi.org/10.1109/MC.2015.205\">10.1109/MC.2015.205</a>"},"page":"18-20","intvolume":"        48","has_accepted_license":"1","file_date_updated":"2018-11-02T15:47:45Z","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901 - Subproject C2","_id":"14"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"_id":"1772","user_id":"16153","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"status":"public","type":"journal_article","title":"Self-Aware and Self-Expressive Systems – Guest Editor's Introduction","publisher":"IEEE Computer Society","date_created":"2018-03-23T14:06:12Z","year":"2015","issue":"7","ddc":["000"],"keyword":["self-awareness","self-expression"],"language":[{"iso":"eng"}],"file":[{"success":1,"relation":"main_file","content_type":"application/pdf","file_size":5605009,"file_name":"07163237.pdf","file_id":"5313","access_level":"closed","date_updated":"2018-11-02T15:47:45Z","date_created":"2018-11-02T15:47:45Z","creator":"ups"}],"publication":"IEEE Computer"},{"language":[{"iso":"eng"}],"ddc":["040"],"file":[{"success":1,"relation":"main_file","content_type":"application/pdf","file_size":2993898,"access_level":"closed","file_id":"1444","file_name":"296-859425.pdf","date_updated":"2018-03-20T07:47:56Z","creator":"florida","date_created":"2018-03-20T07:47:56Z"}],"abstract":[{"text":"FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x.","lang":"eng"}],"publication":"International Journal of Reconfigurable Computing (IJRC)","title":"Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study","date_created":"2017-10-17T12:41:49Z","publisher":"Hindawi","year":"2015","quality_controlled":"1","file_date_updated":"2018-03-20T07:47:56Z","article_number":"859425","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","_id":"296","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"status":"public","type":"journal_article","doi":"10.1155/2015/859425","volume":2015,"author":[{"first_name":"Tobias","last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145"},{"full_name":"Schmitz, Henning","last_name":"Schmitz","first_name":"Henning"},{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"}],"date_updated":"2023-09-26T13:29:08Z","intvolume":"      2015","citation":{"chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” <i>International Journal of Reconfigurable Computing (IJRC)</i> 2015 (2015). <a href=\"https://doi.org/10.1155/2015/859425\">https://doi.org/10.1155/2015/859425</a>.","ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study,” <i>International Journal of Reconfigurable Computing (IJRC)</i>, vol. 2015, Art. no. 859425, 2015, doi: <a href=\"https://doi.org/10.1155/2015/859425\">10.1155/2015/859425</a>.","ama":"Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. <i>International Journal of Reconfigurable Computing (IJRC)</i>. 2015;2015. doi:<a href=\"https://doi.org/10.1155/2015/859425\">10.1155/2015/859425</a>","short":"T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable Computing (IJRC) 2015 (2015).","mla":"Kenter, Tobias, et al. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” <i>International Journal of Reconfigurable Computing (IJRC)</i>, vol. 2015, 859425, Hindawi, 2015, doi:<a href=\"https://doi.org/10.1155/2015/859425\">10.1155/2015/859425</a>.","bibtex":"@article{Kenter_Schmitz_Plessl_2015, title={Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}, volume={2015}, DOI={<a href=\"https://doi.org/10.1155/2015/859425\">10.1155/2015/859425</a>}, number={859425}, journal={International Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2015} }","apa":"Kenter, T., Schmitz, H., &#38; Plessl, C. (2015). Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. <i>International Journal of Reconfigurable Computing (IJRC)</i>, <i>2015</i>, Article 859425. <a href=\"https://doi.org/10.1155/2015/859425\">https://doi.org/10.1155/2015/859425</a>"},"has_accepted_license":"1"},{"title":"Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores","date_created":"2017-10-17T12:41:51Z","year":"2015","quality_controlled":"1","ddc":["040"],"language":[{"iso":"eng"}],"external_id":{"arxiv":["1412.3906"]},"abstract":[{"lang":"eng","text":"This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement."}],"file":[{"file_id":"1442","file_name":"303-plessl15_adapt.pdf","access_level":"open_access","file_size":1176620,"creator":"florida","date_created":"2018-03-20T07:46:46Z","date_updated":"2019-08-01T09:10:44Z","relation":"main_file","content_type":"application/pdf"}],"publication":"Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)","oa":"1","date_updated":"2023-09-26T13:29:59Z","author":[{"first_name":"Marvin","last_name":"Damschen","full_name":"Damschen, Marvin"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"}],"citation":{"ama":"Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. In: <i>Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT)</i>. ; 2015.","chicago":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” In <i>Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT)</i>, 2015.","ieee":"M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores,” 2015.","short":"M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","mla":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” <i>Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT)</i>, 2015.","bibtex":"@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen, Marvin and Plessl, Christian}, year={2015} }","apa":"Damschen, M., &#38; Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. <i>Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT)</i>."},"has_accepted_license":"1","file_date_updated":"2019-08-01T09:10:44Z","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"_id":"303","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"status":"public","type":"conference"},{"language":[{"iso":"eng"}],"_id":"1773","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","status":"public","publication":"Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)","type":"conference","title":"Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm","doi":"10.1145/2675743.2771824","date_updated":"2023-09-26T13:31:01Z","publisher":"ACM","author":[{"full_name":"Schumacher, Jörn","last_name":"Schumacher","first_name":"Jörn"},{"first_name":"J.","last_name":"T. Anderson","full_name":"T. Anderson, J."},{"full_name":"Borga, A.","last_name":"Borga","first_name":"A."},{"first_name":"H.","last_name":"Boterenbrood","full_name":"Boterenbrood, H."},{"first_name":"H.","last_name":"Chen","full_name":"Chen, H."},{"last_name":"Chen","full_name":"Chen, K.","first_name":"K."},{"last_name":"Drake","full_name":"Drake, G.","first_name":"G."},{"full_name":"Francis, D.","last_name":"Francis","first_name":"D."},{"first_name":"B.","last_name":"Gorini","full_name":"Gorini, B."},{"first_name":"F.","last_name":"Lanni","full_name":"Lanni, F."},{"first_name":"Giovanna","full_name":"Lehmann-Miotto, Giovanna","last_name":"Lehmann-Miotto"},{"full_name":"Levinson, L.","last_name":"Levinson","first_name":"L."},{"first_name":"J.","full_name":"Narevicius, J.","last_name":"Narevicius"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153"},{"full_name":"Roich, A.","last_name":"Roich","first_name":"A."},{"first_name":"S.","full_name":"Ryu, S.","last_name":"Ryu"},{"first_name":"F.","last_name":"P. Schreuder","full_name":"P. Schreuder, F."},{"first_name":"Wainer","full_name":"Vandelli, Wainer","last_name":"Vandelli"},{"last_name":"Vermeulen","full_name":"Vermeulen, J.","first_name":"J."},{"first_name":"J.","last_name":"Zhang","full_name":"Zhang, J."}],"date_created":"2018-03-23T14:09:33Z","year":"2015","citation":{"short":"J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen, J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015.","bibtex":"@inproceedings{Schumacher_T. Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_et al._2015, title={Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm}, DOI={<a href=\"https://doi.org/10.1145/2675743.2771824\">10.1145/2675743.2771824</a>}, booktitle={Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher={ACM}, author={Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H. and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni, F. and et al.}, year={2015} }","mla":"Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” <i>Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)</i>, ACM, 2015, doi:<a href=\"https://doi.org/10.1145/2675743.2771824\">10.1145/2675743.2771824</a>.","apa":"Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli, W., Vermeulen, J., &#38; Zhang, J. (2015). Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. <i>Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)</i>. <a href=\"https://doi.org/10.1145/2675743.2771824\">https://doi.org/10.1145/2675743.2771824</a>","ama":"Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. In: <i>Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)</i>. ACM; 2015. doi:<a href=\"https://doi.org/10.1145/2675743.2771824\">10.1145/2675743.2771824</a>","ieee":"J. Schumacher <i>et al.</i>, “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,” 2015, doi: <a href=\"https://doi.org/10.1145/2675743.2771824\">10.1145/2675743.2771824</a>.","chicago":"Schumacher, Jörn, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” In <i>Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)</i>. ACM, 2015. <a href=\"https://doi.org/10.1145/2675743.2771824\">https://doi.org/10.1145/2675743.2771824</a>."},"quality_controlled":"1"},{"language":[{"iso":"eng"}],"keyword":["approximate computing","survey"],"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"263"},{"_id":"78"}],"_id":"1768","status":"public","type":"journal_article","publication":"Informatik Spektrum","doi":"10.1007/s00287-015-0911-z","title":"Aktuelles Schlagwort: Approximate Computing","author":[{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"Schreier, Peter J.","last_name":"Schreier","first_name":"Peter J."}],"date_created":"2018-03-23T13:58:34Z","date_updated":"2023-09-26T13:30:22Z","publisher":"Springer","citation":{"chicago":"Plessl, Christian, Marco Platzner, and Peter J. Schreier. “Aktuelles Schlagwort: Approximate Computing.” <i>Informatik Spektrum</i>, no. 5 (2015): 396–99. <a href=\"https://doi.org/10.1007/s00287-015-0911-z\">https://doi.org/10.1007/s00287-015-0911-z</a>.","ieee":"C. Plessl, M. Platzner, and P. J. Schreier, “Aktuelles Schlagwort: Approximate Computing,” <i>Informatik Spektrum</i>, no. 5, pp. 396–399, 2015, doi: <a href=\"https://doi.org/10.1007/s00287-015-0911-z\">10.1007/s00287-015-0911-z</a>.","ama":"Plessl C, Platzner M, Schreier PJ. Aktuelles Schlagwort: Approximate Computing. <i>Informatik Spektrum</i>. 2015;(5):396-399. doi:<a href=\"https://doi.org/10.1007/s00287-015-0911-z\">10.1007/s00287-015-0911-z</a>","apa":"Plessl, C., Platzner, M., &#38; Schreier, P. J. (2015). Aktuelles Schlagwort: Approximate Computing. <i>Informatik Spektrum</i>, <i>5</i>, 396–399. <a href=\"https://doi.org/10.1007/s00287-015-0911-z\">https://doi.org/10.1007/s00287-015-0911-z</a>","bibtex":"@article{Plessl_Platzner_Schreier_2015, title={Aktuelles Schlagwort: Approximate Computing}, DOI={<a href=\"https://doi.org/10.1007/s00287-015-0911-z\">10.1007/s00287-015-0911-z</a>}, number={5}, journal={Informatik Spektrum}, publisher={Springer}, author={Plessl, Christian and Platzner, Marco and Schreier, Peter J.}, year={2015}, pages={396–399} }","mla":"Plessl, Christian, et al. “Aktuelles Schlagwort: Approximate Computing.” <i>Informatik Spektrum</i>, no. 5, Springer, 2015, pp. 396–99, doi:<a href=\"https://doi.org/10.1007/s00287-015-0911-z\">10.1007/s00287-015-0911-z</a>.","short":"C. Plessl, M. Platzner, P.J. Schreier, Informatik Spektrum (2015) 396–399."},"page":"396-399","year":"2015","issue":"5","quality_controlled":"1"},{"quality_controlled":"1","year":"2015","publisher":"EDA Consortium / IEEE","date_created":"2017-10-17T12:41:38Z","title":"Transparent offloading of computational hotspots from binary code to Xeon Phi","publication":"Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)","abstract":[{"lang":"eng","text":"In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator."}],"file":[{"file_size":380552,"file_id":"1500","access_level":"closed","file_name":"238-plessl15_date.pdf","date_updated":"2018-03-21T10:29:49Z","creator":"florida","date_created":"2018-03-21T10:29:49Z","success":1,"relation":"main_file","content_type":"application/pdf"}],"ddc":["040"],"language":[{"iso":"eng"}],"has_accepted_license":"1","citation":{"apa":"Damschen, M., Riebler, H., Vaz, G. F., &#38; Plessl, C. (2015). Transparent offloading of computational hotspots from binary code to Xeon Phi. <i>Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)</i>, 1078–1083. <a href=\"https://doi.org/10.7873/DATE.2015.1124\">https://doi.org/10.7873/DATE.2015.1124</a>","bibtex":"@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading of computational hotspots from binary code to Xeon Phi}, DOI={<a href=\"https://doi.org/10.7873/DATE.2015.1124\">10.7873/DATE.2015.1124</a>}, booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015}, pages={1078–1083} }","mla":"Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” <i>Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)</i>, EDA Consortium / IEEE, 2015, pp. 1078–83, doi:<a href=\"https://doi.org/10.7873/DATE.2015.1124\">10.7873/DATE.2015.1124</a>.","short":"M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–1083.","ieee":"M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading of computational hotspots from binary code to Xeon Phi,” in <i>Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)</i>, 2015, pp. 1078–1083, doi: <a href=\"https://doi.org/10.7873/DATE.2015.1124\">10.7873/DATE.2015.1124</a>.","chicago":"Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” In <i>Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)</i>, 1078–83. EDA Consortium / IEEE, 2015. <a href=\"https://doi.org/10.7873/DATE.2015.1124\">https://doi.org/10.7873/DATE.2015.1124</a>.","ama":"Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational hotspots from binary code to Xeon Phi. In: <i>Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)</i>. EDA Consortium / IEEE; 2015:1078-1083. doi:<a href=\"https://doi.org/10.7873/DATE.2015.1124\">10.7873/DATE.2015.1124</a>"},"page":"1078-1083","date_updated":"2023-09-26T13:31:44Z","author":[{"first_name":"Marvin","last_name":"Damschen","full_name":"Damschen, Marvin"},{"full_name":"Riebler, Heinrich","id":"8961","last_name":"Riebler","first_name":"Heinrich"},{"full_name":"Vaz, Gavin Francis","id":"30332","last_name":"Vaz","first_name":"Gavin Francis"},{"full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"}],"doi":"10.7873/DATE.2015.1124","type":"conference","status":"public","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"_id":"238","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"file_date_updated":"2018-03-21T10:29:49Z"},{"year":"2015","intvolume":"       664","citation":{"chicago":"Anderson, J, A Borga, H Boterenbrood, H Chen, K Chen, G Drake, D Francis, et al. “FELIX: A High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades.” <i>Journal of Physics: Conference Series</i> 664 (2015). <a href=\"https://doi.org/10.1088/1742-6596/664/8/082050\">https://doi.org/10.1088/1742-6596/664/8/082050</a>.","ieee":"J. Anderson <i>et al.</i>, “FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades,” <i>Journal of Physics: Conference Series</i>, vol. 664, Art. no. 082050, 2015, doi: <a href=\"https://doi.org/10.1088/1742-6596/664/8/082050\">10.1088/1742-6596/664/8/082050</a>.","ama":"Anderson J, Borga A, Boterenbrood H, et al. FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades. <i>Journal of Physics: Conference Series</i>. 2015;664. doi:<a href=\"https://doi.org/10.1088/1742-6596/664/8/082050\">10.1088/1742-6596/664/8/082050</a>","bibtex":"@article{Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_Lehmann Miotto_et al._2015, title={FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades}, volume={664}, DOI={<a href=\"https://doi.org/10.1088/1742-6596/664/8/082050\">10.1088/1742-6596/664/8/082050</a>}, number={082050}, journal={Journal of Physics: Conference Series}, publisher={IOP Publishing}, author={Anderson, J and Borga, A and Boterenbrood, H and Chen, H and Chen, K and Drake, G and Francis, D and Gorini, B and Lanni, F and Lehmann Miotto, G and et al.}, year={2015} }","short":"J. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. Schreuder, J. Schumacher, W. Vandelli, J. Vermeulen, J. Zhang, Journal of Physics: Conference Series 664 (2015).","mla":"Anderson, J., et al. “FELIX: A High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades.” <i>Journal of Physics: Conference Series</i>, vol. 664, 082050, IOP Publishing, 2015, doi:<a href=\"https://doi.org/10.1088/1742-6596/664/8/082050\">10.1088/1742-6596/664/8/082050</a>.","apa":"Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., Schreuder, F., Schumacher, J., Vandelli, W., Vermeulen, J., &#38; Zhang, J. (2015). FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades. <i>Journal of Physics: Conference Series</i>, <i>664</i>, Article 082050. <a href=\"https://doi.org/10.1088/1742-6596/664/8/082050\">https://doi.org/10.1088/1742-6596/664/8/082050</a>"},"quality_controlled":"1","title":"FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades","doi":"10.1088/1742-6596/664/8/082050","publisher":"IOP Publishing","date_updated":"2023-09-26T13:31:23Z","volume":664,"author":[{"first_name":"J","full_name":"Anderson, J","last_name":"Anderson"},{"last_name":"Borga","full_name":"Borga, A","first_name":"A"},{"last_name":"Boterenbrood","full_name":"Boterenbrood, H","first_name":"H"},{"full_name":"Chen, H","last_name":"Chen","first_name":"H"},{"first_name":"K","full_name":"Chen, K","last_name":"Chen"},{"first_name":"G","full_name":"Drake, G","last_name":"Drake"},{"first_name":"D","full_name":"Francis, D","last_name":"Francis"},{"last_name":"Gorini","full_name":"Gorini, B","first_name":"B"},{"full_name":"Lanni, F","last_name":"Lanni","first_name":"F"},{"full_name":"Lehmann Miotto, G","last_name":"Lehmann Miotto","first_name":"G"},{"full_name":"Levinson, L","last_name":"Levinson","first_name":"L"},{"last_name":"Narevicius","full_name":"Narevicius, J","first_name":"J"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"},{"last_name":"Roich","full_name":"Roich, A","first_name":"A"},{"full_name":"Ryu, S","last_name":"Ryu","first_name":"S"},{"first_name":"F","full_name":"Schreuder, F","last_name":"Schreuder"},{"first_name":"Jörn","full_name":"Schumacher, Jörn","last_name":"Schumacher"},{"last_name":"Vandelli","full_name":"Vandelli, Wainer","first_name":"Wainer"},{"first_name":"J","last_name":"Vermeulen","full_name":"Vermeulen, J"},{"full_name":"Zhang, J","last_name":"Zhang","first_name":"J"}],"date_created":"2018-03-23T14:19:27Z","abstract":[{"lang":"eng","text":"The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. A new class of devices will be needed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper FELIX (Front End LInk eXchange) is presented, a PC-based device to route data from and to multiple GBT links via a high-performance general purpose network capable of a total throughput up to O(20 Tbps). FELIX implies architectural changes to the ATLAS data acquisition system, such as the use of industry standard COTS components early in the DAQ chain. Additionally the design and implementation of a FELIX demonstration platform is presented and hardware and software aspects will be discussed."}],"status":"public","publication":"Journal of Physics: Conference Series","type":"journal_article","article_number":"082050","language":[{"iso":"eng"}],"_id":"1775","department":[{"_id":"27"},{"_id":"518"}],"user_id":"15278"},{"status":"public","editor":[{"last_name":"Künsemöller","full_name":"Künsemöller, Jörn","first_name":"Jörn"},{"first_name":"Norber Otto","full_name":"Eke, Norber Otto","last_name":"Eke"},{"first_name":"Lioba","last_name":"Foit","full_name":"Foit, Lioba"},{"full_name":"Kaerlein, Timo","last_name":"Kaerlein","first_name":"Timo"}],"type":"book_chapter","file_date_updated":"2018-03-20T07:29:58Z","department":[{"_id":"518"},{"_id":"27"},{"_id":"78"}],"series_title":"Schriftenreihe des Graduiertenkollegs \"Automatismen\"","user_id":"15278","_id":"335","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"page":"123-144","citation":{"ama":"Platzner M, Plessl C. Verschiebungen an der Grenze zwischen Hardware und Software. In: Künsemöller J, Eke NO, Foit L, Kaerlein T, eds. <i>Logiken strukturbildender Prozesse: Automatismen</i>. Schriftenreihe des Graduiertenkollegs “Automatismen.” Wilhelm Fink; 2014:123-144.","ieee":"M. Platzner and C. Plessl, “Verschiebungen an der Grenze zwischen Hardware und Software,” in <i>Logiken strukturbildender Prozesse: Automatismen</i>, J. Künsemöller, N. O. Eke, L. Foit, and T. Kaerlein, Eds. Paderborn: Wilhelm Fink, 2014, pp. 123–144.","chicago":"Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” In <i>Logiken strukturbildender Prozesse: Automatismen</i>, edited by Jörn Künsemöller, Norber Otto Eke, Lioba Foit, and Timo Kaerlein, 123–44. Schriftenreihe des Graduiertenkollegs “Automatismen.” Paderborn: Wilhelm Fink, 2014.","bibtex":"@inbook{Platzner_Plessl_2014, place={Paderborn}, series={Schriftenreihe des Graduiertenkollegs “Automatismen”}, title={Verschiebungen an der Grenze zwischen Hardware und Software}, booktitle={Logiken strukturbildender Prozesse: Automatismen}, publisher={Wilhelm Fink}, author={Platzner, Marco and Plessl, Christian}, editor={Künsemöller, Jörn and Eke, Norber Otto and Foit, Lioba and Kaerlein, Timo}, year={2014}, pages={123–144}, collection={Schriftenreihe des Graduiertenkollegs “Automatismen”} }","mla":"Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” <i>Logiken strukturbildender Prozesse: Automatismen</i>, edited by Jörn Künsemöller et al., Wilhelm Fink, 2014, pp. 123–44.","short":"M. Platzner, C. Plessl, in: J. Künsemöller, N.O. Eke, L. Foit, T. Kaerlein (Eds.), Logiken strukturbildender Prozesse: Automatismen, Wilhelm Fink, Paderborn, 2014, pp. 123–144.","apa":"Platzner, M., &#38; Plessl, C. (2014). Verschiebungen an der Grenze zwischen Hardware und Software. In J. Künsemöller, N. O. Eke, L. Foit, &#38; T. Kaerlein (Eds.), <i>Logiken strukturbildender Prozesse: Automatismen</i> (pp. 123–144). Wilhelm Fink."},"place":"Paderborn","publication_identifier":{"isbn":["978-3-7705-5730-1"]},"has_accepted_license":"1","publication_status":"published","author":[{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"},{"full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"date_updated":"2023-09-26T13:32:49Z","file":[{"creator":"florida","date_created":"2018-03-20T07:29:58Z","date_updated":"2018-03-20T07:29:58Z","file_name":"335-2014_plessl_automatismen.pdf","file_id":"1424","access_level":"closed","file_size":2848154,"content_type":"application/pdf","relation":"main_file","success":1}],"abstract":[{"text":"Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung von neuen Forschungsrichtungen gef{\\\"u}hrt. In diesem Beitrag besch{\\\"a}ftigen wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\\\"a}ndige Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem Computersystem besser in Hardware und welche besser in Software realisiert werden sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\\\"u}hrt hat. Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze zwischen Hardware und Software w{\\\"a}hrend der Entwicklung eines Produktes statt, um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten Produkt hingegen k{\\\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption, dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware und Software autonom w{\\\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware eines Computers w{\\\"a}hrend der Laufzeit ver{\\\"a}ndert werden kann. Diese Technologie f{\\\"u}hrt zu einer durchl{\\\"a}ssigen Grenze zwischen Hardware und Software bzw. l{\\\"o}st sie die herk{\\\"o}mmliche Vorstellung einer festen Hardware und einer flexiblen Software damit auf.","lang":"eng"}],"publication":"Logiken strukturbildender Prozesse: Automatismen","language":[{"iso":"ger"}],"ddc":["040"],"year":"2014","quality_controlled":"1","title":"Verschiebungen an der Grenze zwischen Hardware und Software","date_created":"2017-10-17T12:41:57Z","publisher":"Wilhelm Fink"},{"status":"public","type":"conference","file_date_updated":"2018-03-20T07:02:02Z","_id":"388","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","series_title":"Lecture Notes in Computer Science (LNCS)","place":"Cham","intvolume":"      8405","page":"144-155","citation":{"ama":"Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>. Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>","ieee":"T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer,” in <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, 2014, vol. 8405, pp. 144–155, doi: <a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>.","chicago":"Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, 8405:144–55. Lecture Notes in Computer Science (LNCS). Cham: Springer International Publishing, 2014. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">https://doi.org/10.1007/978-3-319-05960-0_13</a>.","short":"T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155.","mla":"Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>.","bibtex":"@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}, volume={8405}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>}, booktitle={Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}, publisher={Springer International Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}, year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)} }","apa":"Kenter, T., Vaz, G. F., &#38; Plessl, C. (2014). Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, <i>8405</i>, 144–155. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">https://doi.org/10.1007/978-3-319-05960-0_13</a>"},"has_accepted_license":"1","doi":"10.1007/978-3-319-05960-0_13","date_updated":"2023-09-26T13:34:08Z","volume":8405,"author":[{"first_name":"Tobias","last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias"},{"first_name":"Gavin Francis","id":"30332","full_name":"Vaz, Gavin Francis","last_name":"Vaz"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"}],"abstract":[{"text":"In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties.","lang":"eng"}],"file":[{"success":1,"relation":"main_file","content_type":"application/pdf","file_size":330193,"file_name":"388-plessl14_arc.pdf","file_id":"1387","access_level":"closed","date_updated":"2018-03-20T07:02:02Z","date_created":"2018-03-20T07:02:02Z","creator":"florida"}],"publication":"Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)","ddc":["040"],"language":[{"iso":"eng"}],"year":"2014","quality_controlled":"1","title":"Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer","publisher":"Springer International Publishing","date_created":"2017-10-17T12:42:07Z"},{"doi":"10.1016/j.micpro.2013.12.001","title":"Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators","volume":38,"author":[{"first_name":"Andreas","last_name":"Agne","full_name":"Agne, Andreas"},{"full_name":"Hangmann, Hendrik","last_name":"Hangmann","first_name":"Hendrik"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"},{"id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"date_created":"2017-10-17T12:42:02Z","publisher":"Elsevier","date_updated":"2023-09-26T13:33:06Z","intvolume":"        38","page":"911-919","citation":{"ama":"Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. <i>Microprocessors and Microsystems</i>. 2014;38(8, Part B):911-919. doi:<a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>","chicago":"Agne, Andreas, Hendrik Hangmann, Markus Happe, Marco Platzner, and Christian Plessl. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” <i>Microprocessors and Microsystems</i> 38, no. 8, Part B (2014): 911–19. <a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">https://doi.org/10.1016/j.micpro.2013.12.001</a>.","ieee":"A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators,” <i>Microprocessors and Microsystems</i>, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi: <a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>.","mla":"Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” <i>Microprocessors and Microsystems</i>, vol. 38, no. 8, Part B, Elsevier, 2014, pp. 911–19, doi:<a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>.","short":"A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and Microsystems 38 (2014) 911–919.","bibtex":"@article{Agne_Hangmann_Happe_Platzner_Plessl_2014, title={Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators}, volume={38}, DOI={<a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>}, number={8, Part B}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco and Plessl, Christian}, year={2014}, pages={911–919} }","apa":"Agne, A., Hangmann, H., Happe, M., Platzner, M., &#38; Plessl, C. (2014). Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. <i>Microprocessors and Microsystems</i>, <i>38</i>(8, Part B), 911–919. <a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">https://doi.org/10.1016/j.micpro.2013.12.001</a>"},"year":"2014","issue":"8, Part B","has_accepted_license":"1","quality_controlled":"1","file_date_updated":"2018-03-20T07:20:31Z","language":[{"iso":"eng"}],"ddc":["040"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","_id":"363","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"status":"public","file":[{"date_updated":"2018-03-20T07:20:31Z","creator":"florida","date_created":"2018-03-20T07:20:31Z","file_size":1499996,"file_name":"363-plessl13_micpro.pdf","file_id":"1408","access_level":"closed","content_type":"application/pdf","success":1,"relation":"main_file"}],"abstract":[{"lang":"eng","text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices."}],"publication":"Microprocessors and Microsystems","type":"journal_article"}]