[{"year":"2014","quality_controlled":"1","title":"Reconstructing AES Key Schedules from Decayed Memory with FPGAs","date_created":"2017-10-17T12:42:05Z","publisher":"IEEE","file":[{"file_id":"1397","access_level":"closed","file_name":"377-FCCM14.pdf","file_size":1003907,"date_created":"2018-03-20T07:14:20Z","creator":"florida","date_updated":"2018-03-20T07:14:20Z","relation":"main_file","success":1,"content_type":"application/pdf"}],"abstract":[{"lang":"eng","text":"In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates."}],"publication":"Proceedings of Field-Programmable Custom Computing Machines (FCCM)","language":[{"iso":"eng"}],"ddc":["040"],"keyword":["coldboot"],"citation":{"ieee":"H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules from Decayed Memory with FPGAs,” in <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, 2014, pp. 222–229, doi: <a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>.","chicago":"Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, 222–29. IEEE, 2014. <a href=\"https://doi.org/10.1109/FCCM.2014.67\">https://doi.org/10.1109/FCCM.2014.67</a>.","ama":"Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>. IEEE; 2014:222-229. doi:<a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>","apa":"Riebler, H., Kenter, T., Plessl, C., &#38; Sorge, C. (2014). Reconstructing AES Key Schedules from Decayed Memory with FPGAs. <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, 222–229. <a href=\"https://doi.org/10.1109/FCCM.2014.67\">https://doi.org/10.1109/FCCM.2014.67</a>","short":"H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.","bibtex":"@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing AES Key Schedules from Decayed Memory with FPGAs}, DOI={<a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>}, booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}, year={2014}, pages={222–229} }","mla":"Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, IEEE, 2014, pp. 222–29, doi:<a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>."},"page":"222-229","has_accepted_license":"1","doi":"10.1109/FCCM.2014.67","author":[{"last_name":"Riebler","full_name":"Riebler, Heinrich","id":"8961","first_name":"Heinrich"},{"first_name":"Tobias","last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias"},{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl"},{"first_name":"Christoph","full_name":"Sorge, Christoph","last_name":"Sorge"}],"date_updated":"2023-09-26T13:33:50Z","status":"public","type":"conference","file_date_updated":"2018-03-20T07:14:20Z","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"_id":"377"},{"language":[{"iso":"eng"}],"ddc":["040"],"file":[{"success":1,"relation":"main_file","content_type":"application/pdf","file_size":916052,"file_name":"365-plessl14_trets_01.pdf","access_level":"closed","file_id":"1406","date_updated":"2018-03-20T07:19:19Z","creator":"florida","date_created":"2018-03-20T07:19:19Z"}],"abstract":[{"lang":"eng","text":"Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems."}],"publication":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","title":"Self-awareness as a Model for Designing and Operating Heterogeneous Multicores","date_created":"2017-10-17T12:42:03Z","publisher":"ACM","year":"2014","issue":"2","quality_controlled":"1","file_date_updated":"2018-03-20T07:19:19Z","article_number":"13","department":[{"_id":"27"},{"_id":"78"},{"_id":"518"}],"user_id":"15278","_id":"365","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"status":"public","type":"journal_article","doi":"10.1145/2617596","volume":7,"author":[{"first_name":"Andreas","last_name":"Agne","full_name":"Agne, Andreas"},{"first_name":"Markus","last_name":"Happe","full_name":"Happe, Markus"},{"full_name":"Lösch, Achim","id":"43646","last_name":"Lösch","first_name":"Achim"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"}],"date_updated":"2023-09-26T13:33:31Z","intvolume":"         7","citation":{"ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>. 2014;7(2). doi:<a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i> 7, no. 2 (2014). <a href=\"https://doi.org/10.1145/2617596\">https://doi.org/10.1145/2617596</a>.","ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness as a Model for Designing and Operating Heterogeneous Multicores,” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, vol. 7, no. 2, Art. no. 13, 2014, doi: <a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>.","apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., &#38; Platzner, M. (2014). Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, <i>7</i>(2), Article 13. <a href=\"https://doi.org/10.1145/2617596\">https://doi.org/10.1145/2617596</a>","mla":"Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, vol. 7, no. 2, 13, ACM, 2014, doi:<a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>.","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2014).","bibtex":"@article{Agne_Happe_Lösch_Plessl_Platzner_2014, title={Self-awareness as a Model for Designing and Operating Heterogeneous Multicores}, volume={7}, DOI={<a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>}, number={213}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={ACM}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2014} }"},"has_accepted_license":"1"},{"file_date_updated":"2018-03-20T07:31:40Z","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"_id":"328","status":"public","type":"journal_article","doi":"10.1109/MM.2013.110","author":[{"full_name":"Agne, Andreas","last_name":"Agne","first_name":"Andreas"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"full_name":"Keller, Ariane","last_name":"Keller","first_name":"Ariane"},{"first_name":"Enno","full_name":"Lübbers, Enno","last_name":"Lübbers"},{"first_name":"Bernhard","last_name":"Plattner","full_name":"Plattner, Bernhard"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian"}],"volume":34,"date_updated":"2023-09-26T13:32:31Z","citation":{"ama":"Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for Reconfigurable Computing. <i>IEEE Micro</i>. 2014;34(1):60-71. doi:<a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>","ieee":"A. Agne <i>et al.</i>, “ReconOS - An Operating System Approach for Reconfigurable Computing,” <i>IEEE Micro</i>, vol. 34, no. 1, pp. 60–71, 2014, doi: <a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>.","chicago":"Agne, Andreas, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner, Marco Platzner, and Christian Plessl. “ReconOS - An Operating System Approach for Reconfigurable Computing.” <i>IEEE Micro</i> 34, no. 1 (2014): 60–71. <a href=\"https://doi.org/10.1109/MM.2013.110\">https://doi.org/10.1109/MM.2013.110</a>.","apa":"Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., &#38; Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing. <i>IEEE Micro</i>, <i>34</i>(1), 60–71. <a href=\"https://doi.org/10.1109/MM.2013.110\">https://doi.org/10.1109/MM.2013.110</a>","short":"A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl, IEEE Micro 34 (2014) 60–71.","mla":"Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable Computing.” <i>IEEE Micro</i>, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:<a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>.","bibtex":"@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS - An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={<a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>}, number={1}, journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco and Plessl, Christian}, year={2014}, pages={60–71} }"},"intvolume":"        34","page":"60-71","has_accepted_license":"1","language":[{"iso":"eng"}],"ddc":["040"],"file":[{"content_type":"application/pdf","success":1,"relation":"main_file","date_updated":"2018-03-20T07:31:40Z","creator":"florida","date_created":"2018-03-20T07:31:40Z","file_size":1877185,"access_level":"closed","file_name":"328-plessl14_micro_01.pdf","file_id":"1426"}],"abstract":[{"text":"The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications","lang":"eng"}],"publication":"IEEE Micro","title":"ReconOS - An Operating System Approach for Reconfigurable Computing","date_created":"2017-10-17T12:41:55Z","publisher":"IEEE","year":"2014","issue":"1","quality_controlled":"1"},{"publisher":"IEEE","date_updated":"2023-09-26T13:35:40Z","author":[{"last_name":"C. Durelli","full_name":"C. Durelli, Gianluca","first_name":"Gianluca"},{"first_name":"Marcello","full_name":"Pogliani, Marcello","last_name":"Pogliani"},{"full_name":"Miele, Antonio","last_name":"Miele","first_name":"Antonio"},{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"},{"first_name":"Heinrich","last_name":"Riebler","id":"8961","full_name":"Riebler, Heinrich"},{"last_name":"Vaz","full_name":"Vaz, Gavin Francis","id":"30332","first_name":"Gavin Francis"},{"first_name":"Marco","full_name":"D. Santambrogio, Marco","last_name":"D. Santambrogio"},{"last_name":"Bolchini","full_name":"Bolchini, Cristiana","first_name":"Cristiana"}],"date_created":"2018-03-26T13:40:14Z","title":"Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach","doi":"10.1109/ISPA.2014.27","quality_controlled":"1","year":"2014","citation":{"short":"G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.","bibtex":"@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014, title={Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}, DOI={<a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149} }","mla":"C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, IEEE, 2014, pp. 142–49, doi:<a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>.","apa":"C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., D. Santambrogio, M., &#38; Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, 142–149. <a href=\"https://doi.org/10.1109/ISPA.2014.27\">https://doi.org/10.1109/ISPA.2014.27</a>","ieee":"G. C. Durelli <i>et al.</i>, “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach,” in <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, 2014, pp. 142–149, doi: <a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>.","chicago":"C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl, Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” In <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, 142–49. IEEE, 2014. <a href=\"https://doi.org/10.1109/ISPA.2014.27\">https://doi.org/10.1109/ISPA.2014.27</a>.","ama":"C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>. IEEE; 2014:142-149. doi:<a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>"},"page":"142-149","project":[{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"_id":"1778","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"language":[{"iso":"eng"}],"type":"conference","publication":"Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)","status":"public"},{"abstract":[{"lang":"eng","text":"Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes."}],"file":[{"file_size":557362,"file_id":"1353","access_level":"closed","file_name":"439-plessl14a_reconfig.pdf","date_updated":"2018-03-16T11:29:52Z","creator":"florida","date_created":"2018-03-16T11:29:52Z","success":1,"relation":"main_file","content_type":"application/pdf"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","ddc":["040"],"language":[{"iso":"eng"}],"year":"2014","quality_controlled":"1","title":"Deferring Accelerator Offloading Decisions to Application Runtime","publisher":"IEEE","date_created":"2017-10-17T12:42:17Z","status":"public","type":"conference","file_date_updated":"2018-03-16T11:29:52Z","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"_id":"439","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"citation":{"chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Deferring Accelerator Offloading Decisions to Application Runtime.” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2014. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">https://doi.org/10.1109/ReConFig.2014.7032509</a>.","ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2014, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>.","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2014:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","bibtex":"@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator Offloading Decisions to Application Runtime}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }","mla":"Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2014, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>.","apa":"Vaz, G. F., Riebler, H., Kenter, T., &#38; Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">https://doi.org/10.1109/ReConFig.2014.7032509</a>"},"page":"1-8","has_accepted_license":"1","doi":"10.1109/ReConFig.2014.7032509","date_updated":"2023-09-26T13:37:02Z","author":[{"first_name":"Gavin Francis","last_name":"Vaz","id":"30332","full_name":"Vaz, Gavin Francis"},{"full_name":"Riebler, Heinrich","id":"8961","last_name":"Riebler","first_name":"Heinrich"},{"full_name":"Kenter, Tobias","id":"3145","last_name":"Kenter","first_name":"Tobias"},{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"}]},{"ddc":["040"],"language":[{"iso":"eng"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","abstract":[{"text":"Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design.","lang":"eng"}],"file":[{"success":1,"relation":"main_file","content_type":"application/pdf","file_size":932852,"access_level":"closed","file_id":"1366","file_name":"406-ReConFig14.pdf","date_updated":"2018-03-16T11:37:42Z","creator":"florida","date_created":"2018-03-16T11:37:42Z"}],"publisher":"IEEE","date_created":"2017-10-17T12:42:11Z","title":"Kernel-Centric Acceleration of High Accuracy Stereo-Matching","quality_controlled":"1","year":"2014","_id":"406","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","file_date_updated":"2018-03-16T11:37:42Z","type":"conference","status":"public","date_updated":"2023-09-26T13:36:40Z","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","id":"3145","last_name":"Kenter"},{"first_name":"Henning","last_name":"Schmitz","full_name":"Schmitz, Henning"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"}],"doi":"10.1109/ReConFig.2014.7032535","has_accepted_license":"1","page":"1-8","citation":{"ama":"Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2014:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>","ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High Accuracy Stereo-Matching,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2014, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>.","chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2014. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">https://doi.org/10.1109/ReConFig.2014.7032535</a>.","bibtex":"@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration of High Accuracy Stereo-Matching}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2014}, pages={1–8} }","mla":"Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2014, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>.","short":"T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","apa":"Kenter, T., Schmitz, H., &#38; Plessl, C. (2014). Kernel-Centric Acceleration of High Accuracy Stereo-Matching. <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">https://doi.org/10.1109/ReConFig.2014.7032535</a>"}},{"status":"public","type":"conference","publication":"Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)","language":[{"iso":"eng"}],"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"_id":"1780","citation":{"apa":"C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino, M., Pell, O., Plessl, C., D. Santambrogio, M., &#38; Bolchini, C. (2014). SAVE: Towards efficient resource management in heterogeneous system architectures. <i>Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)</i>. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_38\">https://doi.org/10.1007/978-3-319-05960-0_38</a>","short":"G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino, O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014.","mla":"C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” <i>Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)</i>, Springer, 2014, doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_38\">10.1007/978-3-319-05960-0_38</a>.","bibtex":"@inproceedings{C. Durelli_Copolla_Djafarian_Koranaros_Miele_Paolino_Pell_Plessl_D. Santambrogio_Bolchini_2014, title={SAVE: Towards efficient resource management in heterogeneous system architectures}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-05960-0_38\">10.1007/978-3-319-05960-0_38</a>}, booktitle={Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)}, publisher={Springer}, author={C. Durelli, Gianluca and Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014} }","ama":"C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource management in heterogeneous system architectures. In: <i>Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)</i>. Springer; 2014. doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_38\">10.1007/978-3-319-05960-0_38</a>","chicago":"C. Durelli, Gianluca, Marcello Copolla, Karim Djafarian, George Koranaros, Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio, and Cristiana Bolchini. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” In <i>Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)</i>. Springer, 2014. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_38\">https://doi.org/10.1007/978-3-319-05960-0_38</a>.","ieee":"G. C. Durelli <i>et al.</i>, “SAVE: Towards efficient resource management in heterogeneous system architectures,” 2014, doi: <a href=\"https://doi.org/10.1007/978-3-319-05960-0_38\">10.1007/978-3-319-05960-0_38</a>."},"year":"2014","quality_controlled":"1","doi":"10.1007/978-3-319-05960-0_38","title":"SAVE: Towards efficient resource management in heterogeneous system architectures","date_created":"2018-03-26T13:45:35Z","author":[{"first_name":"Gianluca","last_name":"C. Durelli","full_name":"C. Durelli, Gianluca"},{"last_name":"Copolla","full_name":"Copolla, Marcello","first_name":"Marcello"},{"full_name":"Djafarian, Karim","last_name":"Djafarian","first_name":"Karim"},{"last_name":"Koranaros","full_name":"Koranaros, George","first_name":"George"},{"first_name":"Antonio","full_name":"Miele, Antonio","last_name":"Miele"},{"full_name":"Paolino, Michele","last_name":"Paolino","first_name":"Michele"},{"last_name":"Pell","full_name":"Pell, Oliver","first_name":"Oliver"},{"full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"},{"first_name":"Marco","last_name":"D. Santambrogio","full_name":"D. Santambrogio, Marco"},{"first_name":"Cristiana","last_name":"Bolchini","full_name":"Bolchini, Cristiana"}],"date_updated":"2023-09-26T13:36:20Z","publisher":"Springer"},{"publication_identifier":{"issn":["0163-5964"]},"page":"65-70","intvolume":"        41","citation":{"ama":"Giefers H, Plessl C, Förstner J. Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. <i>ACM SIGARCH Computer Architecture News</i>. 2014;41(5):65-70. doi:<a href=\"https://doi.org/10.1145/2641361.2641372\">10.1145/2641361.2641372</a>","ieee":"H. Giefers, C. Plessl, and J. Förstner, “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers,” <i>ACM SIGARCH Computer Architecture News</i>, vol. 41, no. 5, pp. 65–70, 2014, doi: <a href=\"https://doi.org/10.1145/2641361.2641372\">10.1145/2641361.2641372</a>.","chicago":"Giefers, Heiner, Christian Plessl, and Jens Förstner. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” <i>ACM SIGARCH Computer Architecture News</i> 41, no. 5 (2014): 65–70. <a href=\"https://doi.org/10.1145/2641361.2641372\">https://doi.org/10.1145/2641361.2641372</a>.","bibtex":"@article{Giefers_Plessl_Förstner_2014, title={Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers}, volume={41}, DOI={<a href=\"https://doi.org/10.1145/2641361.2641372\">10.1145/2641361.2641372</a>}, number={5}, journal={ACM SIGARCH Computer Architecture News}, publisher={ACM}, author={Giefers, Heiner and Plessl, Christian and Förstner, Jens}, year={2014}, pages={65–70} }","short":"H. Giefers, C. Plessl, J. Förstner, ACM SIGARCH Computer Architecture News 41 (2014) 65–70.","mla":"Giefers, Heiner, et al. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” <i>ACM SIGARCH Computer Architecture News</i>, vol. 41, no. 5, ACM, 2014, pp. 65–70, doi:<a href=\"https://doi.org/10.1145/2641361.2641372\">10.1145/2641361.2641372</a>.","apa":"Giefers, H., Plessl, C., &#38; Förstner, J. (2014). Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. <i>ACM SIGARCH Computer Architecture News</i>, <i>41</i>(5), 65–70. <a href=\"https://doi.org/10.1145/2641361.2641372\">https://doi.org/10.1145/2641361.2641372</a>"},"date_updated":"2023-09-26T13:35:58Z","volume":41,"author":[{"last_name":"Giefers","full_name":"Giefers, Heiner","first_name":"Heiner"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian"},{"first_name":"Jens","id":"158","full_name":"Förstner, Jens","last_name":"Förstner","orcid":"0000-0001-7059-9862"}],"doi":"10.1145/2641361.2641372","type":"journal_article","status":"public","_id":"1779","department":[{"_id":"27"},{"_id":"518"},{"_id":"61"},{"_id":"78"}],"user_id":"15278","quality_controlled":"1","issue":"5","year":"2014","publisher":"ACM","date_created":"2018-03-26T13:42:34Z","title":"Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers","publication":"ACM SIGARCH Computer Architecture News","keyword":["funding-maxup","tet_topic_hpc"],"language":[{"iso":"eng"}]},{"citation":{"ama":"Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>. IEEE; 2013:386-389. doi:<a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>","chicago":"Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, 386–89. IEEE, 2013. <a href=\"https://doi.org/10.1109/FPT.2013.6718394\">https://doi.org/10.1109/FPT.2013.6718394</a>.","ieee":"H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,” in <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, 2013, pp. 386–389, doi: <a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>.","bibtex":"@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated Key Search for Cold-Boot Attacks against AES}, DOI={<a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}, year={2013}, pages={386–389} }","mla":"Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, IEEE, 2013, pp. 386–89, doi:<a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>.","short":"H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.","apa":"Riebler, H., Kenter, T., Sorge, C., &#38; Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, 386–389. <a href=\"https://doi.org/10.1109/FPT.2013.6718394\">https://doi.org/10.1109/FPT.2013.6718394</a>"},"page":"386-389","year":"2013","quality_controlled":"1","has_accepted_license":"1","doi":"10.1109/FPT.2013.6718394","title":"FPGA-accelerated Key Search for Cold-Boot Attacks against AES","date_created":"2017-10-17T12:42:35Z","author":[{"id":"8961","full_name":"Riebler, Heinrich","last_name":"Riebler","first_name":"Heinrich"},{"first_name":"Tobias","last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145"},{"full_name":"Sorge, Christoph","last_name":"Sorge","first_name":"Christoph"},{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl"}],"date_updated":"2023-09-26T13:37:35Z","publisher":"IEEE","file":[{"content_type":"application/pdf","relation":"main_file","success":1,"creator":"florida","date_created":"2018-03-15T10:36:08Z","date_updated":"2018-03-15T10:36:08Z","file_name":"528-plessl13_fpt.pdf","access_level":"closed","file_id":"1294","file_size":822680}],"status":"public","abstract":[{"text":"Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES.","lang":"eng"}],"type":"conference","publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","file_date_updated":"2018-03-15T10:36:08Z","language":[{"iso":"eng"}],"ddc":["040"],"keyword":["coldboot"],"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"13","name":"SFB 901 - Subproject C1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"_id":"528"},{"has_accepted_license":"1","quality_controlled":"1","year":"2013","citation":{"ieee":"M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: <a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">10.1109/ISORC.2013.6913232</a>.","chicago":"Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” In <i>Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS)</i>. IEEE, 2013. <a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">https://doi.org/10.1109/ISORC.2013.6913232</a>.","ama":"Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In: <i>Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS)</i>. IEEE; 2013. doi:<a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">10.1109/ISORC.2013.6913232</a>","apa":"Happe, M., Kling, P., Plessl, C., Platzner, M., &#38; Meyer auf der Heide, F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. <i>Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS)</i>. <a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">https://doi.org/10.1109/ISORC.2013.6913232</a>","mla":"Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” <i>Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS)</i>, IEEE, 2013, doi:<a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">10.1109/ISORC.2013.6913232</a>.","short":"M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013.","bibtex":"@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly Computing: A Novel Paradigm for Individualized IT Services}, DOI={<a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">10.1109/ISORC.2013.6913232</a>}, booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide, Friedhelm}, year={2013} }"},"publisher":"IEEE","date_updated":"2023-09-26T13:38:20Z","date_created":"2017-10-17T12:42:30Z","author":[{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"full_name":"Kling, Peter","last_name":"Kling","first_name":"Peter"},{"id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"},{"last_name":"Meyer auf der Heide","id":"15523","full_name":"Meyer auf der Heide, Friedhelm","first_name":"Friedhelm"}],"title":"On-The-Fly Computing: A Novel Paradigm for Individualized IT Services","doi":"10.1109/ISORC.2013.6913232","publication":"Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)","type":"conference","abstract":[{"text":"In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas.","lang":"eng"}],"status":"public","file":[{"content_type":"application/pdf","success":1,"relation":"main_file","date_updated":"2018-03-15T13:38:56Z","date_created":"2018-03-15T13:38:56Z","creator":"florida","file_size":1040834,"access_level":"closed","file_id":"1308","file_name":"505-Plessl13_seus.pdf"}],"_id":"505","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"department":[{"_id":"63"},{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","ddc":["040"],"language":[{"iso":"eng"}],"file_date_updated":"2018-03-15T13:38:56Z"},{"language":[{"iso":"eng"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"},{"_id":"63"}],"user_id":"15278","_id":"1787","project":[{"grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30"}],"status":"public","publication":"Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)","type":"conference","doi":"10.1109/IPDPSW.2013.136","title":"Parallel Macro Pipelining on the Intel SCC Many-Core Computer","author":[{"last_name":"Suess","full_name":"Suess, Tim","first_name":"Tim"},{"full_name":"Schoenrock, Andrew","last_name":"Schoenrock","first_name":"Andrew"},{"first_name":"Sebastian","last_name":"Meisner","full_name":"Meisner, Sebastian"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian"}],"date_created":"2018-03-26T14:51:05Z","publisher":"IEEE Computer Society","date_updated":"2023-09-26T13:38:05Z","page":"64-73","citation":{"short":"T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, Washington, DC, USA, 2013, pp. 64–73.","bibtex":"@inproceedings{Suess_Schoenrock_Meisner_Plessl_2013, place={Washington, DC, USA}, title={Parallel Macro Pipelining on the Intel SCC Many-Core Computer}, DOI={<a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">10.1109/IPDPSW.2013.136</a>}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE Computer Society}, author={Suess, Tim and Schoenrock, Andrew and Meisner, Sebastian and Plessl, Christian}, year={2013}, pages={64–73} }","mla":"Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” <i>Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)</i>, IEEE Computer Society, 2013, pp. 64–73, doi:<a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">10.1109/IPDPSW.2013.136</a>.","apa":"Suess, T., Schoenrock, A., Meisner, S., &#38; Plessl, C. (2013). Parallel Macro Pipelining on the Intel SCC Many-Core Computer. <i>Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)</i>, 64–73. <a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">https://doi.org/10.1109/IPDPSW.2013.136</a>","ama":"Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the Intel SCC Many-Core Computer. In: <i>Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)</i>. IEEE Computer Society; 2013:64-73. doi:<a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">10.1109/IPDPSW.2013.136</a>","ieee":"T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining on the Intel SCC Many-Core Computer,” in <i>Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)</i>, 2013, pp. 64–73, doi: <a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">10.1109/IPDPSW.2013.136</a>.","chicago":"Suess, Tim, Andrew Schoenrock, Sebastian Meisner, and Christian Plessl. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” In <i>Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)</i>, 64–73. Washington, DC, USA: IEEE Computer Society, 2013. <a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">https://doi.org/10.1109/IPDPSW.2013.136</a>."},"place":"Washington, DC, USA","year":"2013","quality_controlled":"1","publication_identifier":{"isbn":["978-0-7695-4979-8"]}},{"status":"public","file":[{"file_size":353057,"file_name":"587-2012_plessl_awareness_magazine.pdf","access_level":"closed","file_id":"1260","date_updated":"2018-03-15T08:37:02Z","creator":"florida","date_created":"2018-03-15T08:37:02Z","success":1,"relation":"main_file","content_type":"application/pdf"}],"type":"misc","language":[{"iso":"eng"}],"file_date_updated":"2018-03-15T08:37:02Z","ddc":["040"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"398","_id":"587","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"}],"citation":{"chicago":"Plessl, Christian, Marco Platzner, Andreas Agne, Markus Happe, and Enno Lübbers. <i>Programming Models for Reconfigurable Heterogeneous Multi-Cores</i>. Awareness Magazine, 2012.","ieee":"C. Plessl, M. Platzner, A. Agne, M. Happe, and E. Lübbers, <i>Programming models for reconfigurable heterogeneous multi-cores</i>. Awareness Magazine, 2012.","ama":"Plessl C, Platzner M, Agne A, Happe M, Lübbers E. <i>Programming Models for Reconfigurable Heterogeneous Multi-Cores</i>. Awareness Magazine; 2012.","apa":"Plessl, C., Platzner, M., Agne, A., Happe, M., &#38; Lübbers, E. (2012). <i>Programming models for reconfigurable heterogeneous multi-cores</i>. Awareness Magazine.","bibtex":"@book{Plessl_Platzner_Agne_Happe_Lübbers_2012, title={Programming models for reconfigurable heterogeneous multi-cores}, publisher={Awareness Magazine}, author={Plessl, Christian and Platzner, Marco and Agne, Andreas and Happe, Markus and Lübbers, Enno}, year={2012} }","mla":"Plessl, Christian, et al. <i>Programming Models for Reconfigurable Heterogeneous Multi-Cores</i>. Awareness Magazine, 2012.","short":"C. Plessl, M. Platzner, A. Agne, M. Happe, E. Lübbers, Programming Models for Reconfigurable Heterogeneous Multi-Cores, Awareness Magazine, 2012."},"year":"2012","has_accepted_license":"1","title":"Programming models for reconfigurable heterogeneous multi-cores","date_created":"2017-10-17T12:42:46Z","author":[{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"},{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"full_name":"Happe, Markus","last_name":"Happe","first_name":"Markus"},{"last_name":"Lübbers","full_name":"Lübbers, Enno","first_name":"Enno"}],"date_updated":"2022-01-06T07:02:44Z","publisher":"Awareness Magazine"},{"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"_id":"2106","file_date_updated":"2019-02-13T09:04:46Z","type":"conference","status":"public","author":[{"last_name":"Meyer","full_name":"Meyer, Björn","first_name":"Björn"},{"first_name":"Jörn","last_name":"Schumacher","full_name":"Schumacher, Jörn"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Jens","last_name":"Förstner","orcid":"0000-0001-7059-9862","id":"158","full_name":"Förstner, Jens"}],"date_updated":"2023-09-26T13:39:13Z","conference":{"name":"22nd International Conference on Field Programmable Logic and Applicaitons (FPL)"},"doi":"10.1109/FPL.2012.6339370","has_accepted_license":"1","citation":{"apa":"Meyer, B., Schumacher, J., Plessl, C., &#38; Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 189–196. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>","short":"B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196.","bibtex":"@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}, year={2012}, pages={189–196} }","mla":"Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2012, pp. 189–96, doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","ama":"Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2012:189-196. doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>","ieee":"B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?,” in <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2012, pp. 189–196, doi: <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","chicago":"Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 189–96. IEEE, 2012. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>."},"page":"189-196","language":[{"iso":"eng"}],"ddc":["000"],"keyword":["funding-upb-forschungspreis","funding-maxup","tet_topic_hpc"],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","file":[{"content_type":"application/pdf","success":1,"relation":"main_file","date_updated":"2019-02-13T09:04:46Z","creator":"fossie","date_created":"2019-02-13T09:04:46Z","file_size":2148787,"file_id":"7638","file_name":"2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA acceleratin with an openmp-like programming effort.pdf","access_level":"closed"}],"abstract":[{"text":"Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator.\r\nIn this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like\r\nprogramming environment exists. As case study we use an application from computational nanophotonics. Our results\r\nshow that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view.","lang":"eng"}],"date_created":"2018-03-29T15:04:25Z","publisher":"IEEE","title":"Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?","quality_controlled":"1","year":"2012"},{"year":"2012","citation":{"chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” <i>Microprocessors and Microsystems</i> 36, no. 2 (2012): 110–26. <a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">https://doi.org/10.1016/j.micpro.2011.04.002</a>.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators,” <i>Microprocessors and Microsystems</i>, vol. 36, no. 2, pp. 110–126, 2012, doi: <a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>.","ama":"Schumacher T, Plessl C, Platzner M. IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. <i>Microprocessors and Microsystems</i>. 2012;36(2):110-126. doi:<a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>","apa":"Schumacher, T., Plessl, C., &#38; Platzner, M. (2012). IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. <i>Microprocessors and Microsystems</i>, <i>36</i>(2), 110–126. <a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">https://doi.org/10.1016/j.micpro.2011.04.002</a>","short":"T. Schumacher, C. Plessl, M. Platzner, Microprocessors and Microsystems 36 (2012) 110–126.","bibtex":"@article{Schumacher_Plessl_Platzner_2012, title={IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators}, volume={36}, DOI={<a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>}, number={2}, journal={Microprocessors and Microsystems}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2012}, pages={110–126} }","mla":"Schumacher, Tobias, et al. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” <i>Microprocessors and Microsystems</i>, vol. 36, no. 2, 2012, pp. 110–26, doi:<a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>."},"intvolume":"        36","page":"110-126","publication_identifier":{"issn":["0141-9331"]},"quality_controlled":"1","issue":"2","title":"IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators","doi":"10.1016/j.micpro.2011.04.002","date_updated":"2023-09-26T13:39:30Z","author":[{"first_name":"Tobias","last_name":"Schumacher","full_name":"Schumacher, Tobias"},{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"date_created":"2018-03-29T15:12:38Z","volume":36,"status":"public","type":"journal_article","publication":"Microprocessors and Microsystems","keyword":["funding-altera"],"language":[{"iso":"eng"}],"_id":"2108","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"quality_controlled":"1","year":"2012","date_created":"2017-10-17T12:42:51Z","publisher":"IEEE","title":"Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators","publication":"Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)","file":[{"date_updated":"2018-03-15T06:48:32Z","date_created":"2018-03-15T06:48:32Z","creator":"florida","file_size":730144,"access_level":"closed","file_id":"1246","file_name":"615-ReConFig12_01.pdf","content_type":"application/pdf","success":1,"relation":"main_file"}],"abstract":[{"lang":"eng","text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices."}],"language":[{"iso":"eng"}],"ddc":["040"],"has_accepted_license":"1","page":"1-8","citation":{"ieee":"M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators,” in <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 2012, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>.","chicago":"Happe, Markus, Hendrik Hangmann, Andreas Agne, and Christian Plessl. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” In <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2012. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">https://doi.org/10.1109/ReConFig.2012.6416745</a>.","ama":"Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2012:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>","apa":"Happe, M., Hangmann, H., Agne, A., &#38; Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">https://doi.org/10.1109/ReConFig.2012.6416745</a>","bibtex":"@inproceedings{Happe_Hangmann_Agne_Plessl_2012, title={Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>}, booktitle={Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}, year={2012}, pages={1–8} }","short":"M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","mla":"Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2012, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>."},"author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"first_name":"Hendrik","full_name":"Hangmann, Hendrik","last_name":"Hangmann"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"}],"date_updated":"2023-09-26T13:42:26Z","doi":"10.1109/ReConFig.2012.6416745","type":"conference","status":"public","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","_id":"615","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"257906","_id":"31","name":"Engineering Proprioception in Computing Systems"}],"file_date_updated":"2018-03-15T06:48:32Z"},{"title":"Pragma based parallelization - Trading hardware efficiency for ease of use?","publisher":"IEEE","date_created":"2017-10-17T12:42:47Z","year":"2012","quality_controlled":"1","ddc":["040"],"language":[{"iso":"eng"}],"abstract":[{"text":"One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort.","lang":"eng"}],"file":[{"date_created":"2018-03-15T08:33:18Z","creator":"florida","date_updated":"2018-03-15T08:33:18Z","access_level":"closed","file_name":"591-ReConFig2012Kenter_Schmitz_Plessl.pdf","file_id":"1257","file_size":371235,"content_type":"application/pdf","relation":"main_file","success":1}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","doi":"10.1109/ReConFig.2012.6416773","date_updated":"2023-09-26T13:41:08Z","author":[{"first_name":"Tobias","id":"3145","full_name":"Kenter, Tobias","last_name":"Kenter"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Henning","last_name":"Schmitz","full_name":"Schmitz, Henning"}],"citation":{"ieee":"T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2012, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>.","chicago":"Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2012. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">https://doi.org/10.1109/ReConFig.2012.6416773</a>.","ama":"Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2012:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>","apa":"Kenter, T., Plessl, C., &#38; Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">https://doi.org/10.1109/ReConFig.2012.6416773</a>","short":"T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","bibtex":"@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization - Trading hardware efficiency for ease of use?}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian and Schmitz, Henning}, year={2012}, pages={1–8} }","mla":"Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2012, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>."},"page":"1-8","has_accepted_license":"1","file_date_updated":"2018-03-15T08:33:18Z","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"_id":"591","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"status":"public","type":"conference"},{"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"_id":"609","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"ddc":["040"],"language":[{"iso":"eng"}],"file_date_updated":"2018-03-15T08:14:17Z","type":"conference","publication":"Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)","abstract":[{"lang":"eng","text":"Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method."}],"file":[{"success":1,"relation":"main_file","content_type":"application/pdf","file_size":146789,"access_level":"closed","file_id":"1249","file_name":"609-happe12_fpl_awareness.pdf","date_updated":"2018-03-15T08:14:17Z","date_created":"2018-03-15T08:14:17Z","creator":"florida"}],"status":"public","date_updated":"2023-09-26T13:41:36Z","date_created":"2017-10-17T12:42:50Z","author":[{"full_name":"Happe, Markus","last_name":"Happe","first_name":"Markus"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"}],"title":"Hardware/Software Platform for Self-aware Compute Nodes","has_accepted_license":"1","quality_controlled":"1","year":"2012","citation":{"mla":"Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 2012, pp. 8–9.","bibtex":"@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012}, pages={8–9} }","short":"M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","apa":"Happe, M., Agne, A., Plessl, C., &#38; Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 8–9.","ama":"Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>. ; 2012:8-9.","chicago":"Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software Platform for Self-Aware Compute Nodes.” In <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 8–9, 2012.","ieee":"M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 2012, pp. 8–9."},"page":"8-9"},{"date_created":"2017-10-17T12:42:42Z","publisher":"IEEE","title":"Turning control flow graphs into function calls: Code generation for heterogeneous architectures","quality_controlled":"1","year":"2012","language":[{"iso":"eng"}],"ddc":["040"],"publication":"Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)","file":[{"content_type":"application/pdf","relation":"main_file","success":1,"date_created":"2018-03-15T10:20:24Z","creator":"florida","date_updated":"2018-03-15T10:20:24Z","file_name":"567-ba-ca-12a.pdf","file_id":"1275","access_level":"closed","file_size":288508}],"abstract":[{"text":"Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided.","lang":"eng"}],"author":[{"first_name":"Pablo","full_name":"Barrio, Pablo","last_name":"Barrio"},{"first_name":"Carlos","full_name":"Carreras, Carlos","last_name":"Carreras"},{"first_name":"Roberto","last_name":"Sierra","full_name":"Sierra, Roberto"},{"first_name":"Tobias","last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias"},{"full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"date_updated":"2023-09-26T13:42:54Z","doi":"10.1109/HPCSim.2012.6266973","has_accepted_license":"1","citation":{"short":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–565.","bibtex":"@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning control flow graphs into function calls: Code generation for heterogeneous architectures}, DOI={<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>}, booktitle={Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012}, pages={559–565} }","mla":"Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, IEEE, 2012, pp. 559–65, doi:<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>.","apa":"Barrio, P., Carreras, C., Sierra, R., Kenter, T., &#38; Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 559–565. <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">https://doi.org/10.1109/HPCSim.2012.6266973</a>","ieee":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,” in <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 2012, pp. 559–565, doi: <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>.","chicago":"Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” In <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 559–65. IEEE, 2012. <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">https://doi.org/10.1109/HPCSim.2012.6266973</a>.","ama":"Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>. IEEE; 2012:559-565. doi:<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>"},"page":"559-565","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"_id":"567","file_date_updated":"2018-03-15T10:20:24Z","type":"conference","status":"public"},{"title":"Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs","doi":"10.1109/FPL.2012.6339370","publisher":"IEEE","date_updated":"2023-09-26T13:42:03Z","date_created":"2017-10-17T12:42:51Z","author":[{"first_name":"Christoph","last_name":"Rüthing","full_name":"Rüthing, Christoph"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"first_name":"Andreas","last_name":"Agne","full_name":"Agne, Andreas"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian"}],"year":"2012","citation":{"ama":"Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2012:559-562. doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>","ieee":"C. Rüthing, M. Happe, A. Agne, and C. Plessl, “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs,” in <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 2012, pp. 559–562, doi: <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","chicago":"Rüthing, Christoph, Markus Happe, Andreas Agne, and Christian Plessl. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” In <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 559–62. IEEE, 2012. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>.","short":"C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–562.","bibtex":"@inproceedings{Rüthing_Happe_Agne_Plessl_2012, title={Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}, DOI={<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2012}, pages={559–562} }","mla":"Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2012, pp. 559–62, doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","apa":"Rüthing, C., Happe, M., Agne, A., &#38; Plessl, C. (2012). Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 559–562. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>"},"page":"559-562","quality_controlled":"1","has_accepted_license":"1","ddc":["040"],"file_date_updated":"2018-03-15T06:49:03Z","language":[{"iso":"eng"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"_id":"612","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"abstract":[{"lang":"eng","text":"While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA."}],"file":[{"file_id":"1247","access_level":"closed","file_name":"612-ruething_fpl12.pdf","file_size":202923,"creator":"florida","date_created":"2018-03-15T06:49:03Z","date_updated":"2018-03-15T06:49:03Z","relation":"main_file","success":1,"content_type":"application/pdf"}],"status":"public","type":"conference","publication":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)"},{"year":"2012","citation":{"ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux,” 2012.","chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” In <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>, 2012.","ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. In: <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>. ; 2012.","apa":"Beisel, T., Wiersema, T., Plessl, C., &#38; Brinkmann, A. (2012). Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>.","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2012, title={Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux}, booktitle={Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2012} }","mla":"Beisel, Tobias, et al. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>, 2012."},"quality_controlled":"1","title":"Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux","date_updated":"2023-09-26T13:40:17Z","author":[{"first_name":"Tobias","last_name":"Beisel","full_name":"Beisel, Tobias"},{"last_name":"Wiersema","full_name":"Wiersema, Tobias","id":"3118","first_name":"Tobias"},{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982"},{"full_name":"Brinkmann, André","last_name":"Brinkmann","first_name":"André"}],"date_created":"2018-04-03T09:18:33Z","status":"public","publication":"Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)","type":"conference","keyword":["funding-enhance"],"language":[{"iso":"eng"}],"_id":"2180","project":[{"grant_number":"01|H11004A","_id":"30","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278"}]