[{"status":"public","publication":"Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)","type":"conference","language":[{"iso":"eng"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"},{"_id":"63"}],"user_id":"15278","_id":"1787","project":[{"name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30","grant_number":"01|H11004A"}],"page":"64-73","citation":{"apa":"Suess, T., Schoenrock, A., Meisner, S., &#38; Plessl, C. (2013). Parallel Macro Pipelining on the Intel SCC Many-Core Computer. <i>Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)</i>, 64–73. <a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">https://doi.org/10.1109/IPDPSW.2013.136</a>","bibtex":"@inproceedings{Suess_Schoenrock_Meisner_Plessl_2013, place={Washington, DC, USA}, title={Parallel Macro Pipelining on the Intel SCC Many-Core Computer}, DOI={<a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">10.1109/IPDPSW.2013.136</a>}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE Computer Society}, author={Suess, Tim and Schoenrock, Andrew and Meisner, Sebastian and Plessl, Christian}, year={2013}, pages={64–73} }","short":"T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, Washington, DC, USA, 2013, pp. 64–73.","mla":"Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” <i>Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)</i>, IEEE Computer Society, 2013, pp. 64–73, doi:<a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">10.1109/IPDPSW.2013.136</a>.","ieee":"T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining on the Intel SCC Many-Core Computer,” in <i>Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)</i>, 2013, pp. 64–73, doi: <a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">10.1109/IPDPSW.2013.136</a>.","chicago":"Suess, Tim, Andrew Schoenrock, Sebastian Meisner, and Christian Plessl. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” In <i>Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)</i>, 64–73. Washington, DC, USA: IEEE Computer Society, 2013. <a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">https://doi.org/10.1109/IPDPSW.2013.136</a>.","ama":"Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the Intel SCC Many-Core Computer. In: <i>Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)</i>. IEEE Computer Society; 2013:64-73. doi:<a href=\"https://doi.org/10.1109/IPDPSW.2013.136\">10.1109/IPDPSW.2013.136</a>"},"year":"2013","place":"Washington, DC, USA","publication_identifier":{"isbn":["978-0-7695-4979-8"]},"quality_controlled":"1","doi":"10.1109/IPDPSW.2013.136","title":"Parallel Macro Pipelining on the Intel SCC Many-Core Computer","date_created":"2018-03-26T14:51:05Z","author":[{"full_name":"Suess, Tim","last_name":"Suess","first_name":"Tim"},{"full_name":"Schoenrock, Andrew","last_name":"Schoenrock","first_name":"Andrew"},{"first_name":"Sebastian","full_name":"Meisner, Sebastian","last_name":"Meisner"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"}],"date_updated":"2023-09-26T13:38:05Z","publisher":"IEEE Computer Society"},{"file_date_updated":"2018-03-15T08:37:02Z","language":[{"iso":"eng"}],"ddc":["040"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"398","_id":"587","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"}],"status":"public","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","file_size":353057,"access_level":"closed","file_id":"1260","file_name":"587-2012_plessl_awareness_magazine.pdf","date_updated":"2018-03-15T08:37:02Z","date_created":"2018-03-15T08:37:02Z","creator":"florida"}],"type":"misc","title":"Programming models for reconfigurable heterogeneous multi-cores","author":[{"full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"},{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"full_name":"Lübbers, Enno","last_name":"Lübbers","first_name":"Enno"}],"date_created":"2017-10-17T12:42:46Z","date_updated":"2022-01-06T07:02:44Z","publisher":"Awareness Magazine","citation":{"short":"C. Plessl, M. Platzner, A. Agne, M. Happe, E. Lübbers, Programming Models for Reconfigurable Heterogeneous Multi-Cores, Awareness Magazine, 2012.","mla":"Plessl, Christian, et al. <i>Programming Models for Reconfigurable Heterogeneous Multi-Cores</i>. Awareness Magazine, 2012.","bibtex":"@book{Plessl_Platzner_Agne_Happe_Lübbers_2012, title={Programming models for reconfigurable heterogeneous multi-cores}, publisher={Awareness Magazine}, author={Plessl, Christian and Platzner, Marco and Agne, Andreas and Happe, Markus and Lübbers, Enno}, year={2012} }","apa":"Plessl, C., Platzner, M., Agne, A., Happe, M., &#38; Lübbers, E. (2012). <i>Programming models for reconfigurable heterogeneous multi-cores</i>. Awareness Magazine.","ama":"Plessl C, Platzner M, Agne A, Happe M, Lübbers E. <i>Programming Models for Reconfigurable Heterogeneous Multi-Cores</i>. Awareness Magazine; 2012.","ieee":"C. Plessl, M. Platzner, A. Agne, M. Happe, and E. Lübbers, <i>Programming models for reconfigurable heterogeneous multi-cores</i>. Awareness Magazine, 2012.","chicago":"Plessl, Christian, Marco Platzner, Andreas Agne, Markus Happe, and Enno Lübbers. <i>Programming Models for Reconfigurable Heterogeneous Multi-Cores</i>. Awareness Magazine, 2012."},"year":"2012","has_accepted_license":"1"},{"status":"public","type":"conference","file_date_updated":"2019-02-13T09:04:46Z","_id":"2106","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"citation":{"ama":"Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2012:189-196. doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>","ieee":"B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?,” in <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2012, pp. 189–196, doi: <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","chicago":"Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 189–96. IEEE, 2012. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>.","short":"B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196.","bibtex":"@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}, year={2012}, pages={189–196} }","mla":"Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2012, pp. 189–96, doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","apa":"Meyer, B., Schumacher, J., Plessl, C., &#38; Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 189–196. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>"},"page":"189-196","has_accepted_license":"1","conference":{"name":"22nd International Conference on Field Programmable Logic and Applicaitons (FPL)"},"doi":"10.1109/FPL.2012.6339370","date_updated":"2023-09-26T13:39:13Z","author":[{"last_name":"Meyer","full_name":"Meyer, Björn","first_name":"Björn"},{"first_name":"Jörn","last_name":"Schumacher","full_name":"Schumacher, Jörn"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian"},{"first_name":"Jens","id":"158","full_name":"Förstner, Jens","orcid":"0000-0001-7059-9862","last_name":"Förstner"}],"abstract":[{"lang":"eng","text":"Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator.\r\nIn this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like\r\nprogramming environment exists. As case study we use an application from computational nanophotonics. Our results\r\nshow that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view."}],"file":[{"date_updated":"2019-02-13T09:04:46Z","date_created":"2019-02-13T09:04:46Z","creator":"fossie","file_size":2148787,"file_name":"2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA acceleratin with an openmp-like programming effort.pdf","file_id":"7638","access_level":"closed","content_type":"application/pdf","success":1,"relation":"main_file"}],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","ddc":["000"],"keyword":["funding-upb-forschungspreis","funding-maxup","tet_topic_hpc"],"language":[{"iso":"eng"}],"year":"2012","quality_controlled":"1","title":"Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?","publisher":"IEEE","date_created":"2018-03-29T15:04:25Z"},{"volume":36,"date_created":"2018-03-29T15:12:38Z","author":[{"full_name":"Schumacher, Tobias","last_name":"Schumacher","first_name":"Tobias"},{"full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"},{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"}],"date_updated":"2023-09-26T13:39:30Z","doi":"10.1016/j.micpro.2011.04.002","title":"IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators","issue":"2","quality_controlled":"1","publication_identifier":{"issn":["0141-9331"]},"page":"110-126","intvolume":"        36","citation":{"ama":"Schumacher T, Plessl C, Platzner M. IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. <i>Microprocessors and Microsystems</i>. 2012;36(2):110-126. doi:<a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators,” <i>Microprocessors and Microsystems</i>, vol. 36, no. 2, pp. 110–126, 2012, doi: <a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>.","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” <i>Microprocessors and Microsystems</i> 36, no. 2 (2012): 110–26. <a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">https://doi.org/10.1016/j.micpro.2011.04.002</a>.","apa":"Schumacher, T., Plessl, C., &#38; Platzner, M. (2012). IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. <i>Microprocessors and Microsystems</i>, <i>36</i>(2), 110–126. <a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">https://doi.org/10.1016/j.micpro.2011.04.002</a>","bibtex":"@article{Schumacher_Plessl_Platzner_2012, title={IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators}, volume={36}, DOI={<a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>}, number={2}, journal={Microprocessors and Microsystems}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2012}, pages={110–126} }","mla":"Schumacher, Tobias, et al. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” <i>Microprocessors and Microsystems</i>, vol. 36, no. 2, 2012, pp. 110–26, doi:<a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>.","short":"T. Schumacher, C. Plessl, M. Platzner, Microprocessors and Microsystems 36 (2012) 110–126."},"year":"2012","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","_id":"2108","language":[{"iso":"eng"}],"keyword":["funding-altera"],"publication":"Microprocessors and Microsystems","type":"journal_article","status":"public"},{"language":[{"iso":"eng"}],"ddc":["040"],"publication":"Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)","file":[{"content_type":"application/pdf","success":1,"relation":"main_file","date_updated":"2018-03-15T06:48:32Z","creator":"florida","date_created":"2018-03-15T06:48:32Z","file_size":730144,"file_id":"1246","access_level":"closed","file_name":"615-ReConFig12_01.pdf"}],"abstract":[{"text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices.","lang":"eng"}],"date_created":"2017-10-17T12:42:51Z","publisher":"IEEE","title":"Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators","quality_controlled":"1","year":"2012","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"_id":"615","file_date_updated":"2018-03-15T06:48:32Z","type":"conference","status":"public","author":[{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"full_name":"Hangmann, Hendrik","last_name":"Hangmann","first_name":"Hendrik"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"}],"date_updated":"2023-09-26T13:42:26Z","doi":"10.1109/ReConFig.2012.6416745","has_accepted_license":"1","citation":{"mla":"Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2012, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>.","bibtex":"@inproceedings{Happe_Hangmann_Agne_Plessl_2012, title={Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>}, booktitle={Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}, year={2012}, pages={1–8} }","short":"M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","apa":"Happe, M., Hangmann, H., Agne, A., &#38; Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">https://doi.org/10.1109/ReConFig.2012.6416745</a>","ama":"Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2012:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>","chicago":"Happe, Markus, Hendrik Hangmann, Andreas Agne, and Christian Plessl. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” In <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2012. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">https://doi.org/10.1109/ReConFig.2012.6416745</a>.","ieee":"M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators,” in <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 2012, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>."},"page":"1-8"},{"year":"2012","quality_controlled":"1","title":"Pragma based parallelization - Trading hardware efficiency for ease of use?","publisher":"IEEE","date_created":"2017-10-17T12:42:47Z","abstract":[{"text":"One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort.","lang":"eng"}],"file":[{"date_created":"2018-03-15T08:33:18Z","creator":"florida","date_updated":"2018-03-15T08:33:18Z","file_id":"1257","file_name":"591-ReConFig2012Kenter_Schmitz_Plessl.pdf","access_level":"closed","file_size":371235,"content_type":"application/pdf","relation":"main_file","success":1}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","ddc":["040"],"language":[{"iso":"eng"}],"citation":{"ieee":"T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2012, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>.","chicago":"Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2012. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">https://doi.org/10.1109/ReConFig.2012.6416773</a>.","ama":"Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2012:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>","bibtex":"@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization - Trading hardware efficiency for ease of use?}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian and Schmitz, Henning}, year={2012}, pages={1–8} }","short":"T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","mla":"Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2012, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>.","apa":"Kenter, T., Plessl, C., &#38; Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">https://doi.org/10.1109/ReConFig.2012.6416773</a>"},"page":"1-8","has_accepted_license":"1","doi":"10.1109/ReConFig.2012.6416773","date_updated":"2023-09-26T13:41:08Z","author":[{"first_name":"Tobias","last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"full_name":"Schmitz, Henning","last_name":"Schmitz","first_name":"Henning"}],"status":"public","type":"conference","file_date_updated":"2018-03-15T08:33:18Z","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"_id":"591","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"date_updated":"2023-09-26T13:41:36Z","author":[{"first_name":"Markus","last_name":"Happe","full_name":"Happe, Markus"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"}],"date_created":"2017-10-17T12:42:50Z","title":"Hardware/Software Platform for Self-aware Compute Nodes","has_accepted_license":"1","quality_controlled":"1","year":"2012","citation":{"ieee":"M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 2012, pp. 8–9.","chicago":"Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software Platform for Self-Aware Compute Nodes.” In <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 8–9, 2012.","ama":"Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>. ; 2012:8-9.","bibtex":"@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012}, pages={8–9} }","mla":"Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 2012, pp. 8–9.","short":"M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","apa":"Happe, M., Agne, A., Plessl, C., &#38; Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 8–9."},"page":"8-9","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"_id":"609","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"ddc":["040"],"language":[{"iso":"eng"}],"file_date_updated":"2018-03-15T08:14:17Z","type":"conference","publication":"Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)","abstract":[{"lang":"eng","text":"Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method."}],"file":[{"content_type":"application/pdf","success":1,"relation":"main_file","date_updated":"2018-03-15T08:14:17Z","creator":"florida","date_created":"2018-03-15T08:14:17Z","file_size":146789,"file_id":"1249","access_level":"closed","file_name":"609-happe12_fpl_awareness.pdf"}],"status":"public"},{"file_date_updated":"2018-03-15T10:20:24Z","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","_id":"567","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"}],"status":"public","type":"conference","doi":"10.1109/HPCSim.2012.6266973","author":[{"first_name":"Pablo","full_name":"Barrio, Pablo","last_name":"Barrio"},{"last_name":"Carreras","full_name":"Carreras, Carlos","first_name":"Carlos"},{"first_name":"Roberto","last_name":"Sierra","full_name":"Sierra, Roberto"},{"last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145","first_name":"Tobias"},{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"}],"date_updated":"2023-09-26T13:42:54Z","page":"559-565","citation":{"ama":"Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>. IEEE; 2012:559-565. doi:<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>","ieee":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,” in <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 2012, pp. 559–565, doi: <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>.","chicago":"Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” In <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 559–65. IEEE, 2012. <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">https://doi.org/10.1109/HPCSim.2012.6266973</a>.","apa":"Barrio, P., Carreras, C., Sierra, R., Kenter, T., &#38; Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 559–565. <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">https://doi.org/10.1109/HPCSim.2012.6266973</a>","short":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–565.","mla":"Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, IEEE, 2012, pp. 559–65, doi:<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>.","bibtex":"@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning control flow graphs into function calls: Code generation for heterogeneous architectures}, DOI={<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>}, booktitle={Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012}, pages={559–565} }"},"has_accepted_license":"1","language":[{"iso":"eng"}],"ddc":["040"],"file":[{"creator":"florida","date_created":"2018-03-15T10:20:24Z","date_updated":"2018-03-15T10:20:24Z","access_level":"closed","file_id":"1275","file_name":"567-ba-ca-12a.pdf","file_size":288508,"content_type":"application/pdf","relation":"main_file","success":1}],"abstract":[{"text":"Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided.","lang":"eng"}],"publication":"Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)","title":"Turning control flow graphs into function calls: Code generation for heterogeneous architectures","date_created":"2017-10-17T12:42:42Z","publisher":"IEEE","year":"2012","quality_controlled":"1"},{"language":[{"iso":"eng"}],"file_date_updated":"2018-03-15T06:49:03Z","ddc":["040"],"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"_id":"612","file":[{"content_type":"application/pdf","success":1,"relation":"main_file","date_updated":"2018-03-15T06:49:03Z","creator":"florida","date_created":"2018-03-15T06:49:03Z","file_size":202923,"access_level":"closed","file_name":"612-ruething_fpl12.pdf","file_id":"1247"}],"status":"public","abstract":[{"lang":"eng","text":"While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA."}],"type":"conference","publication":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","doi":"10.1109/FPL.2012.6339370","title":"Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs","date_created":"2017-10-17T12:42:51Z","author":[{"first_name":"Christoph","full_name":"Rüthing, Christoph","last_name":"Rüthing"},{"full_name":"Happe, Markus","last_name":"Happe","first_name":"Markus"},{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153"}],"publisher":"IEEE","date_updated":"2023-09-26T13:42:03Z","citation":{"ama":"Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2012:559-562. doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>","ieee":"C. Rüthing, M. Happe, A. Agne, and C. Plessl, “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs,” in <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 2012, pp. 559–562, doi: <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","chicago":"Rüthing, Christoph, Markus Happe, Andreas Agne, and Christian Plessl. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” In <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 559–62. IEEE, 2012. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>.","apa":"Rüthing, C., Happe, M., Agne, A., &#38; Plessl, C. (2012). Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 559–562. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>","mla":"Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2012, pp. 559–62, doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","short":"C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–562.","bibtex":"@inproceedings{Rüthing_Happe_Agne_Plessl_2012, title={Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}, DOI={<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2012}, pages={559–562} }"},"page":"559-562","year":"2012","has_accepted_license":"1","quality_controlled":"1"},{"status":"public","type":"conference","publication":"Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)","keyword":["funding-enhance"],"language":[{"iso":"eng"}],"project":[{"grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30"}],"_id":"2180","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"year":"2012","citation":{"chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” In <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>, 2012.","ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux,” 2012.","ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. In: <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>. ; 2012.","apa":"Beisel, T., Wiersema, T., Plessl, C., &#38; Brinkmann, A. (2012). Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>.","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2012, title={Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux}, booktitle={Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2012} }","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","mla":"Beisel, Tobias, et al. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>, 2012."},"quality_controlled":"1","title":"Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux","date_updated":"2023-09-26T13:40:17Z","author":[{"first_name":"Tobias","full_name":"Beisel, Tobias","last_name":"Beisel"},{"first_name":"Tobias","last_name":"Wiersema","full_name":"Wiersema, Tobias","id":"3118"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"}],"date_created":"2018-04-03T09:18:33Z"},{"title":"On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors","doi":"10.1155/2012/418315","date_updated":"2023-09-26T13:39:48Z","publisher":"Hindawi Publishing Corp.","author":[{"first_name":"Mariusz","full_name":"Grad, Mariusz","last_name":"Grad"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982"}],"date_created":"2018-04-03T09:13:22Z","year":"2012","citation":{"bibtex":"@article{Grad_Plessl_2012, title={On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors}, DOI={<a href=\"https://doi.org/10.1155/2012/418315\">10.1155/2012/418315</a>}, journal={Int. Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi Publishing Corp.}, author={Grad, Mariusz and Plessl, Christian}, year={2012} }","mla":"Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.” <i>Int. Journal of Reconfigurable Computing (IJRC)</i>, Hindawi Publishing Corp., 2012, doi:<a href=\"https://doi.org/10.1155/2012/418315\">10.1155/2012/418315</a>.","short":"M. Grad, C. Plessl, Int. Journal of Reconfigurable Computing (IJRC) (2012).","apa":"Grad, M., &#38; Plessl, C. (2012). On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. <i>Int. Journal of Reconfigurable Computing (IJRC)</i>. <a href=\"https://doi.org/10.1155/2012/418315\">https://doi.org/10.1155/2012/418315</a>","ama":"Grad M, Plessl C. On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. <i>Int Journal of Reconfigurable Computing (IJRC)</i>. Published online 2012. doi:<a href=\"https://doi.org/10.1155/2012/418315\">10.1155/2012/418315</a>","chicago":"Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.” <i>Int. Journal of Reconfigurable Computing (IJRC)</i>, 2012. <a href=\"https://doi.org/10.1155/2012/418315\">https://doi.org/10.1155/2012/418315</a>.","ieee":"M. Grad and C. Plessl, “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors,” <i>Int. Journal of Reconfigurable Computing (IJRC)</i>, 2012, doi: <a href=\"https://doi.org/10.1155/2012/418315\">10.1155/2012/418315</a>."},"quality_controlled":"1","language":[{"iso":"eng"}],"_id":"2177","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","status":"public","publication":"Int. Journal of Reconfigurable Computing (IJRC)","type":"journal_article"},{"keyword":["funding-intel"],"_id":"2191","user_id":"24135","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"status":"public","type":"conference","publication":"Intel European Research and Innovation Conference","title":"Estimation and Partitioning for CPU-Accelerator Architectures","date_updated":"2022-01-06T06:55:19Z","author":[{"first_name":"Tobias","id":"3145","full_name":"Kenter, Tobias","last_name":"Kenter"},{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"first_name":"Michael","last_name":"Kauschke","full_name":"Kauschke, Michael"}],"date_created":"2018-04-03T14:34:57Z","year":"2011","citation":{"apa":"Kenter, T., Plessl, C., Platzner, M., &#38; Kauschke, M. (2011). Estimation and Partitioning for CPU-Accelerator Architectures. In <i>Intel European Research and Innovation Conference</i>.","short":"T. Kenter, C. Plessl, M. Platzner, M. Kauschke, in: Intel European Research and Innovation Conference, 2011.","bibtex":"@inproceedings{Kenter_Plessl_Platzner_Kauschke_2011, title={Estimation and Partitioning for CPU-Accelerator Architectures}, booktitle={Intel European Research and Innovation Conference}, author={Kenter, Tobias and Plessl, Christian and Platzner, Marco and Kauschke, Michael}, year={2011} }","mla":"Kenter, Tobias, et al. “Estimation and Partitioning for CPU-Accelerator Architectures.” <i>Intel European Research and Innovation Conference</i>, 2011.","ama":"Kenter T, Plessl C, Platzner M, Kauschke M. Estimation and Partitioning for CPU-Accelerator Architectures. In: <i>Intel European Research and Innovation Conference</i>. ; 2011.","chicago":"Kenter, Tobias, Christian Plessl, Marco Platzner, and Michael Kauschke. “Estimation and Partitioning for CPU-Accelerator Architectures.” In <i>Intel European Research and Innovation Conference</i>, 2011.","ieee":"T. Kenter, C. Plessl, M. Platzner, and M. Kauschke, “Estimation and Partitioning for CPU-Accelerator Architectures,” in <i>Intel European Research and Innovation Conference</i>, 2011."}},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"24135","_id":"2202","project":[{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"status":"public","editor":[{"full_name":"Khalgui, Mohamed","last_name":"Khalgui","first_name":"Mohamed"},{"first_name":"Hans-Michael","last_name":"Hanisch","full_name":"Hanisch, Hans-Michael"}],"publication":"Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility","type":"book_chapter","doi":"10.4018/978-1-60960-086-0","title":"Hardware Virtualization on Dynamically Reconfigurable Embedded Processors","date_created":"2018-04-03T15:11:16Z","author":[{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"date_updated":"2022-01-06T06:55:22Z","publisher":"IGI Global","citation":{"chicago":"Plessl, Christian, and Marco Platzner. “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors.” In <i>Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility</i>, edited by Mohamed Khalgui and Hans-Michael Hanisch. Hershey, PA, USA: IGI Global, 2011. <a href=\"https://doi.org/10.4018/978-1-60960-086-0\">https://doi.org/10.4018/978-1-60960-086-0</a>.","ieee":"C. Plessl and M. Platzner, “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors,” in <i>Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility</i>, M. Khalgui and H.-M. Hanisch, Eds. Hershey, PA, USA: IGI Global, 2011.","ama":"Plessl C, Platzner M. Hardware Virtualization on Dynamically Reconfigurable Embedded Processors. In: Khalgui M, Hanisch H-M, eds. <i>Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility</i>. Hershey, PA, USA: IGI Global; 2011. doi:<a href=\"https://doi.org/10.4018/978-1-60960-086-0\">10.4018/978-1-60960-086-0</a>","bibtex":"@inbook{Plessl_Platzner_2011, place={Hershey, PA, USA}, title={Hardware Virtualization on Dynamically Reconfigurable Embedded Processors}, DOI={<a href=\"https://doi.org/10.4018/978-1-60960-086-0\">10.4018/978-1-60960-086-0</a>}, booktitle={Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility}, publisher={IGI Global}, author={Plessl, Christian and Platzner, Marco}, editor={Khalgui, Mohamed and Hanisch, Hans-MichaelEditors}, year={2011} }","short":"C. Plessl, M. Platzner, in: M. Khalgui, H.-M. Hanisch (Eds.), Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility, IGI Global, Hershey, PA, USA, 2011.","mla":"Plessl, Christian, and Marco Platzner. “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors.” <i>Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility</i>, edited by Mohamed Khalgui and Hans-Michael Hanisch, IGI Global, 2011, doi:<a href=\"https://doi.org/10.4018/978-1-60960-086-0\">10.4018/978-1-60960-086-0</a>.","apa":"Plessl, C., &#38; Platzner, M. (2011). Hardware Virtualization on Dynamically Reconfigurable Embedded Processors. In M. Khalgui &#38; H.-M. Hanisch (Eds.), <i>Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility</i>. Hershey, PA, USA: IGI Global. <a href=\"https://doi.org/10.4018/978-1-60960-086-0\">https://doi.org/10.4018/978-1-60960-086-0</a>"},"year":"2011","place":"Hershey, PA, USA","publication_identifier":{"isbn":["978-1-60960-086-0"]}},{"language":[{"iso":"eng"}],"department":[{"_id":"78"},{"_id":"518"}],"user_id":"3118","series_title":"Natural Computing Series","_id":"10737","status":"public","publication":"Cartesian Genetic Programming","type":"book_chapter","title":"Evolution of Electronic Circuits","author":[{"full_name":"Sekanina, Lukas","last_name":"Sekanina","first_name":"Lukas"},{"full_name":"Walker, James Alfred","last_name":"Walker","first_name":"James Alfred"},{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"date_created":"2019-07-10T11:59:35Z","publisher":"Springer Berlin Heidelberg","date_updated":"2022-01-06T06:50:50Z","page":"125-179","citation":{"ieee":"L. Sekanina, J. A. Walker, P. Kaufmann, C. Plessl, and M. Platzner, “Evolution of Electronic Circuits,” in <i>Cartesian Genetic Programming</i>, Springer Berlin Heidelberg, 2011, pp. 125–179.","chicago":"Sekanina, Lukas, James Alfred Walker, Paul Kaufmann, Christian Plessl, and Marco Platzner. “Evolution of Electronic Circuits.” In <i>Cartesian Genetic Programming</i>, 125–79. Natural Computing Series. Springer Berlin Heidelberg, 2011.","ama":"Sekanina L, Walker JA, Kaufmann P, Plessl C, Platzner M. Evolution of Electronic Circuits. In: <i>Cartesian Genetic Programming</i>. Natural Computing Series. Springer Berlin Heidelberg; 2011:125-179.","short":"L. Sekanina, J.A. Walker, P. Kaufmann, C. Plessl, M. Platzner, in: Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 125–179.","bibtex":"@inbook{Sekanina_Walker_Kaufmann_Plessl_Platzner_2011, series={Natural Computing Series}, title={Evolution of Electronic Circuits}, booktitle={Cartesian Genetic Programming}, publisher={Springer Berlin Heidelberg}, author={Sekanina, Lukas and Walker, James Alfred and Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2011}, pages={125–179}, collection={Natural Computing Series} }","mla":"Sekanina, Lukas, et al. “Evolution of Electronic Circuits.” <i>Cartesian Genetic Programming</i>, Springer Berlin Heidelberg, 2011, pp. 125–79.","apa":"Sekanina, L., Walker, J. A., Kaufmann, P., Plessl, C., &#38; Platzner, M. (2011). Evolution of Electronic Circuits. In <i>Cartesian Genetic Programming</i> (pp. 125–179). Springer Berlin Heidelberg."},"year":"2011"},{"quality_controlled":"1","year":"2011","citation":{"short":"B. Meyer, C. Plessl, J. Förstner, in: Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63.","mla":"Meyer, Björn, et al. “Transformation of Scientific Algorithms to Parallel Computing Code: Subdomain Support in a MPI-Multi-GPU Backend.” <i>Symp. on Application Accelerators in High Performance Computing (SAAHPC)</i>, IEEE Computer Society, 2011, pp. 60–63, doi:<a href=\"https://doi.org/10.1109/SAAHPC.2011.12\">10.1109/SAAHPC.2011.12</a>.","bibtex":"@inproceedings{Meyer_Plessl_Förstner_2011, title={Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend}, DOI={<a href=\"https://doi.org/10.1109/SAAHPC.2011.12\">10.1109/SAAHPC.2011.12</a>}, booktitle={Symp. on Application Accelerators in High Performance Computing (SAAHPC)}, publisher={IEEE Computer Society}, author={Meyer, Björn and Plessl, Christian and Förstner, Jens}, year={2011}, pages={60–63} }","apa":"Meyer, B., Plessl, C., &#38; Förstner, J. (2011). Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. <i>Symp. on Application Accelerators in High Performance Computing (SAAHPC)</i>, 60–63. <a href=\"https://doi.org/10.1109/SAAHPC.2011.12\">https://doi.org/10.1109/SAAHPC.2011.12</a>","chicago":"Meyer, Björn, Christian Plessl, and Jens Förstner. “Transformation of Scientific Algorithms to Parallel Computing Code: Subdomain Support in a MPI-Multi-GPU Backend.” In <i>Symp. on Application Accelerators in High Performance Computing (SAAHPC)</i>, 60–63. IEEE Computer Society, 2011. <a href=\"https://doi.org/10.1109/SAAHPC.2011.12\">https://doi.org/10.1109/SAAHPC.2011.12</a>.","ieee":"B. Meyer, C. Plessl, and J. Förstner, “Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend,” in <i>Symp. on Application Accelerators in High Performance Computing (SAAHPC)</i>, 2011, pp. 60–63, doi: <a href=\"https://doi.org/10.1109/SAAHPC.2011.12\">10.1109/SAAHPC.2011.12</a>.","ama":"Meyer B, Plessl C, Förstner J. Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. In: <i>Symp. on Application Accelerators in High Performance Computing (SAAHPC)</i>. IEEE Computer Society; 2011:60-63. doi:<a href=\"https://doi.org/10.1109/SAAHPC.2011.12\">10.1109/SAAHPC.2011.12</a>"},"page":"60-63","date_updated":"2023-09-26T13:44:11Z","publisher":"IEEE Computer Society","date_created":"2018-04-03T14:55:57Z","author":[{"last_name":"Meyer","full_name":"Meyer, Björn","first_name":"Björn"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"},{"first_name":"Jens","id":"158","full_name":"Förstner, Jens","last_name":"Förstner","orcid":"0000-0001-7059-9862"}],"title":"Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend","doi":"10.1109/SAAHPC.2011.12","type":"conference","publication":"Symp. on Application Accelerators in High Performance Computing (SAAHPC)","status":"public","project":[{"_id":"30","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A"}],"_id":"2194","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"keyword":["tet_topic_hpc"],"language":[{"iso":"eng"}]},{"quality_controlled":"1","citation":{"apa":"Beisel, T., Wiersema, T., Plessl, C., &#38; Brinkmann, A. (2011). Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 223–226. <a href=\"https://doi.org/10.1109/ASAP.2011.6043273\">https://doi.org/10.1109/ASAP.2011.6043273</a>","mla":"Beisel, Tobias, et al. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, IEEE Computer Society, 2011, pp. 223–26, doi:<a href=\"https://doi.org/10.1109/ASAP.2011.6043273\">10.1109/ASAP.2011.6043273</a>.","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2011, title={Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler}, DOI={<a href=\"https://doi.org/10.1109/ASAP.2011.6043273\">10.1109/ASAP.2011.6043273</a>}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2011}, pages={223–226} }","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–226.","ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. In: <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>. IEEE Computer Society; 2011:223-226. doi:<a href=\"https://doi.org/10.1109/ASAP.2011.6043273\">10.1109/ASAP.2011.6043273</a>","ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler,” in <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 2011, pp. 223–226, doi: <a href=\"https://doi.org/10.1109/ASAP.2011.6043273\">10.1109/ASAP.2011.6043273</a>.","chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” In <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 223–26. IEEE Computer Society, 2011. <a href=\"https://doi.org/10.1109/ASAP.2011.6043273\">https://doi.org/10.1109/ASAP.2011.6043273</a>."},"page":"223-226","year":"2011","author":[{"first_name":"Tobias","full_name":"Beisel, Tobias","last_name":"Beisel"},{"last_name":"Wiersema","id":"3118","full_name":"Wiersema, Tobias","first_name":"Tobias"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"},{"first_name":"André","last_name":"Brinkmann","full_name":"Brinkmann, André"}],"date_created":"2018-04-03T14:37:14Z","publisher":"IEEE Computer Society","date_updated":"2023-09-26T13:43:48Z","doi":"10.1109/ASAP.2011.6043273","title":"Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler","type":"conference","publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","status":"public","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30"}],"_id":"2193","language":[{"iso":"eng"}]},{"year":"2011","page":"55-60","citation":{"ieee":"M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,” in <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 2011, pp. 55–60, doi: <a href=\"https://doi.org/10.1109/ReConFig.2011.59\">10.1109/ReConFig.2011.59</a>.","chicago":"Happe, Markus, Andreas Agne, and Christian Plessl. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” In <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 55–60. IEEE, 2011. <a href=\"https://doi.org/10.1109/ReConFig.2011.59\">https://doi.org/10.1109/ReConFig.2011.59</a>.","ama":"Happe M, Agne A, Plessl C. Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. In: <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2011:55-60. doi:<a href=\"https://doi.org/10.1109/ReConFig.2011.59\">10.1109/ReConFig.2011.59</a>","apa":"Happe, M., Agne, A., &#38; Plessl, C. (2011). Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 55–60. <a href=\"https://doi.org/10.1109/ReConFig.2011.59\">https://doi.org/10.1109/ReConFig.2011.59</a>","short":"M. Happe, A. Agne, C. Plessl, in: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60.","bibtex":"@inproceedings{Happe_Agne_Plessl_2011, title={Measuring and Predicting Temperature Distributions on FPGAs at Run-Time}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2011.59\">10.1109/ReConFig.2011.59</a>}, booktitle={Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2011}, pages={55–60} }","mla":"Happe, Markus, et al. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2011, pp. 55–60, doi:<a href=\"https://doi.org/10.1109/ReConFig.2011.59\">10.1109/ReConFig.2011.59</a>."},"has_accepted_license":"1","quality_controlled":"1","title":"Measuring and Predicting Temperature Distributions on FPGAs at Run-Time","doi":"10.1109/ReConFig.2011.59","publisher":"IEEE","date_updated":"2023-09-26T13:46:08Z","author":[{"full_name":"Happe, Markus","last_name":"Happe","first_name":"Markus"},{"first_name":"Andreas","last_name":"Agne","full_name":"Agne, Andreas"},{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982"}],"date_created":"2017-10-17T12:42:59Z","abstract":[{"lang":"eng","text":"In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time."}],"status":"public","file":[{"file_size":502244,"file_name":"656-2011_happe_reconfig.pdf","file_id":"1220","access_level":"closed","date_updated":"2018-03-14T13:49:39Z","date_created":"2018-03-14T13:49:39Z","creator":"florida","success":1,"relation":"main_file","content_type":"application/pdf"}],"publication":"Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","type":"conference","ddc":["040"],"language":[{"iso":"eng"}],"file_date_updated":"2018-03-14T13:49:39Z","_id":"656","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278"},{"date_created":"2018-04-03T15:08:13Z","author":[{"last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias","first_name":"Tobias"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982"},{"first_name":"Michael","last_name":"Kauschke","full_name":"Kauschke, Michael"}],"date_updated":"2023-09-26T13:45:04Z","publisher":"ACM","doi":"10.1145/1950413.1950448","title":"Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures","publication_identifier":{"isbn":["978-1-4503-0554-9"]},"quality_controlled":"1","citation":{"apa":"Kenter, T., Platzner, M., Plessl, C., &#38; Kauschke, M. (2011). Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 177–180. <a href=\"https://doi.org/10.1145/1950413.1950448\">https://doi.org/10.1145/1950413.1950448</a>","mla":"Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, ACM, 2011, pp. 177–80, doi:<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>.","bibtex":"@inproceedings{Kenter_Platzner_Plessl_Kauschke_2011, place={New York, NY, USA}, title={Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures}, DOI={<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>}, booktitle={Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}, publisher={ACM}, author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}, year={2011}, pages={177–180} }","short":"T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, New York, NY, USA, 2011, pp. 177–180.","chicago":"Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” In <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 177–80. New York, NY, USA: ACM, 2011. <a href=\"https://doi.org/10.1145/1950413.1950448\">https://doi.org/10.1145/1950413.1950448</a>.","ieee":"T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures,” in <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 2011, pp. 177–180, doi: <a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>.","ama":"Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. In: <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>. ACM; 2011:177-180. doi:<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>"},"page":"177-180","year":"2011","place":"New York, NY, USA","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"_id":"2200","language":[{"iso":"eng"}],"keyword":["design space exploration","LLVM","partitioning","performance","estimation","funding-intel"],"type":"conference","publication":"Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)","status":"public"},{"status":"public","type":"journal_article","publication":"Int. Journal of Recon- figurable Computing (IJRC)","language":[{"iso":"eng"}],"keyword":["funding-altera"],"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"_id":"2201","citation":{"ama":"Schumacher T, Süß T, Plessl C, Platzner M. FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. <i>Int Journal of Recon- figurable Computing (IJRC)</i>. Published online 2011. doi:<a href=\"https://doi.org/10.1155/2011/760954\">10.1155/2011/760954</a>","chicago":"Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study.” <i>Int. Journal of Recon- Figurable Computing (IJRC)</i>, 2011. <a href=\"https://doi.org/10.1155/2011/760954\">https://doi.org/10.1155/2011/760954</a>.","ieee":"T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study,” <i>Int. Journal of Recon- figurable Computing (IJRC)</i>, 2011, doi: <a href=\"https://doi.org/10.1155/2011/760954\">10.1155/2011/760954</a>.","bibtex":"@article{Schumacher_Süß_Plessl_Platzner_2011, title={FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study}, DOI={<a href=\"https://doi.org/10.1155/2011/760954\">10.1155/2011/760954</a>}, journal={Int. Journal of Recon- figurable Computing (IJRC)}, publisher={Hindawi Publishing Corp.}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2011} }","short":"T. Schumacher, T. Süß, C. Plessl, M. Platzner, Int. Journal of Recon- Figurable Computing (IJRC) (2011).","mla":"Schumacher, Tobias, et al. “FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study.” <i>Int. Journal of Recon- Figurable Computing (IJRC)</i>, Hindawi Publishing Corp., 2011, doi:<a href=\"https://doi.org/10.1155/2011/760954\">10.1155/2011/760954</a>.","apa":"Schumacher, T., Süß, T., Plessl, C., &#38; Platzner, M. (2011). FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. <i>Int. Journal of Recon- Figurable Computing (IJRC)</i>. <a href=\"https://doi.org/10.1155/2011/760954\">https://doi.org/10.1155/2011/760954</a>"},"year":"2011","quality_controlled":"1","doi":"10.1155/2011/760954","title":"FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study","author":[{"first_name":"Tobias","last_name":"Schumacher","full_name":"Schumacher, Tobias"},{"full_name":"Süß, Tim","last_name":"Süß","first_name":"Tim"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"}],"date_created":"2018-04-03T15:09:49Z","publisher":"Hindawi Publishing Corp.","date_updated":"2023-09-26T13:45:46Z"},{"year":"2011","citation":{"ama":"Grad M, Plessl C. Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. In: <i>Proc. Reconfigurable Architectures Workshop (RAW)</i>. IEEE Computer Society; 2011:278-285. doi:<a href=\"https://doi.org/10.1109/IPDPS.2011.153\">10.1109/IPDPS.2011.153</a>","ieee":"M. Grad and C. Plessl, “Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture,” in <i>Proc. Reconfigurable Architectures Workshop (RAW)</i>, 2011, pp. 278–285, doi: <a href=\"https://doi.org/10.1109/IPDPS.2011.153\">10.1109/IPDPS.2011.153</a>.","chicago":"Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” In <i>Proc. Reconfigurable Architectures Workshop (RAW)</i>, 278–85. IEEE Computer Society, 2011. <a href=\"https://doi.org/10.1109/IPDPS.2011.153\">https://doi.org/10.1109/IPDPS.2011.153</a>.","mla":"Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” <i>Proc. Reconfigurable Architectures Workshop (RAW)</i>, IEEE Computer Society, 2011, pp. 278–85, doi:<a href=\"https://doi.org/10.1109/IPDPS.2011.153\">10.1109/IPDPS.2011.153</a>.","short":"M. Grad, C. Plessl, in: Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–285.","bibtex":"@inproceedings{Grad_Plessl_2011, title={Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture}, DOI={<a href=\"https://doi.org/10.1109/IPDPS.2011.153\">10.1109/IPDPS.2011.153</a>}, booktitle={Proc. Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE Computer Society}, author={Grad, Mariusz and Plessl, Christian}, year={2011}, pages={278–285} }","apa":"Grad, M., &#38; Plessl, C. (2011). Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. <i>Proc. Reconfigurable Architectures Workshop (RAW)</i>, 278–285. <a href=\"https://doi.org/10.1109/IPDPS.2011.153\">https://doi.org/10.1109/IPDPS.2011.153</a>"},"page":"278-285","quality_controlled":"1","title":"Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture","doi":"10.1109/IPDPS.2011.153","publisher":"IEEE Computer Society","date_updated":"2023-09-26T13:44:39Z","author":[{"first_name":"Mariusz","last_name":"Grad","full_name":"Grad, Mariusz"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"}],"date_created":"2018-04-03T15:05:52Z","status":"public","type":"conference","publication":"Proc. Reconfigurable Architectures Workshop (RAW)","language":[{"iso":"eng"}],"_id":"2198","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]}]