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Journal of Reconfigurable Computing (IJRC)</i>, Hindawi Publishing Corp., 2012, doi:<a href=\"https://doi.org/10.1155/2012/418315\">10.1155/2012/418315</a>.","bibtex":"@article{Grad_Plessl_2012, title={On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors}, DOI={<a href=\"https://doi.org/10.1155/2012/418315\">10.1155/2012/418315</a>}, journal={Int. Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi Publishing Corp.}, author={Grad, Mariusz and Plessl, Christian}, year={2012} }","short":"M. Grad, C. Plessl, Int. Journal of Reconfigurable Computing (IJRC) (2012).","ama":"Grad M, Plessl C. On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. <i>Int Journal of Reconfigurable Computing (IJRC)</i>. Published online 2012. doi:<a href=\"https://doi.org/10.1155/2012/418315\">10.1155/2012/418315</a>","apa":"Grad, M., &#38; Plessl, C. (2012). On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. <i>Int. Journal of Reconfigurable Computing (IJRC)</i>. <a href=\"https://doi.org/10.1155/2012/418315\">https://doi.org/10.1155/2012/418315</a>","chicago":"Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.” <i>Int. Journal of Reconfigurable Computing (IJRC)</i>, 2012. <a href=\"https://doi.org/10.1155/2012/418315\">https://doi.org/10.1155/2012/418315</a>.","ieee":"M. Grad and C. Plessl, “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors,” <i>Int. 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Hardware Virtualization on Dynamically Reconfigurable Embedded Processors. In: Khalgui M, Hanisch H-M, eds. <i>Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility</i>. Hershey, PA, USA: IGI Global; 2011. doi:<a href=\"https://doi.org/10.4018/978-1-60960-086-0\">10.4018/978-1-60960-086-0</a>","apa":"Plessl, C., &#38; Platzner, M. (2011). Hardware Virtualization on Dynamically Reconfigurable Embedded Processors. In M. Khalgui &#38; H.-M. Hanisch (Eds.), <i>Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility</i>. Hershey, PA, USA: IGI Global. <a href=\"https://doi.org/10.4018/978-1-60960-086-0\">https://doi.org/10.4018/978-1-60960-086-0</a>","chicago":"Plessl, Christian, and Marco Platzner. “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors.” In <i>Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility</i>, edited by Mohamed Khalgui and Hans-Michael Hanisch. Hershey, PA, USA: IGI Global, 2011. <a href=\"https://doi.org/10.4018/978-1-60960-086-0\">https://doi.org/10.4018/978-1-60960-086-0</a>.","ieee":"C. Plessl and M. Platzner, “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors,” in <i>Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility</i>, M. Khalgui and H.-M. Hanisch, Eds. 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Hanisch (Eds.), Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility, IGI Global, Hershey, PA, USA, 2011."},"user_id":"24135","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"publisher":"Springer Berlin Heidelberg","date_created":"2019-07-10T11:59:35Z","publication":"Cartesian Genetic Programming","status":"public","language":[{"iso":"eng"}],"type":"book_chapter","year":"2011","_id":"10737","page":"125-179","date_updated":"2022-01-06T06:50:50Z","author":[{"last_name":"Sekanina","full_name":"Sekanina, Lukas","first_name":"Lukas"},{"last_name":"Walker","full_name":"Walker, James Alfred","first_name":"James Alfred"},{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"title":"Evolution of Electronic Circuits","user_id":"3118","citation":{"short":"L. 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Meyer, C. Plessl, J. Förstner, in: Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63."},"user_id":"15278","keyword":["tet_topic_hpc"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"title":"Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend","author":[{"full_name":"Meyer, Björn","first_name":"Björn","last_name":"Meyer"},{"last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian","orcid":"0000-0001-5728-9982"},{"orcid":"0000-0001-7059-9862","first_name":"Jens","full_name":"Förstner, Jens","id":"158","last_name":"Förstner"}],"project":[{"_id":"30","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A"}],"doi":"10.1109/SAAHPC.2011.12","_id":"2194","page":"60-63","date_updated":"2023-09-26T13:44:11Z","publication":"Symp. on Application Accelerators in High Performance Computing (SAAHPC)","quality_controlled":"1","date_created":"2018-04-03T14:55:57Z","publisher":"IEEE Computer Society","type":"conference","year":"2011","language":[{"iso":"eng"}],"status":"public"},{"author":[{"first_name":"Tobias","full_name":"Beisel, Tobias","last_name":"Beisel"},{"last_name":"Wiersema","id":"3118","first_name":"Tobias","full_name":"Wiersema, Tobias"},{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"}],"title":"Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler","doi":"10.1109/ASAP.2011.6043273","project":[{"grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30"}],"user_id":"15278","citation":{"ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler,” in <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 2011, pp. 223–226, doi: <a href=\"https://doi.org/10.1109/ASAP.2011.6043273\">10.1109/ASAP.2011.6043273</a>.","chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” In <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 223–26. IEEE Computer Society, 2011. <a href=\"https://doi.org/10.1109/ASAP.2011.6043273\">https://doi.org/10.1109/ASAP.2011.6043273</a>.","apa":"Beisel, T., Wiersema, T., Plessl, C., &#38; Brinkmann, A. (2011). Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 223–226. <a href=\"https://doi.org/10.1109/ASAP.2011.6043273\">https://doi.org/10.1109/ASAP.2011.6043273</a>","ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. In: <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>. IEEE Computer Society; 2011:223-226. doi:<a href=\"https://doi.org/10.1109/ASAP.2011.6043273\">10.1109/ASAP.2011.6043273</a>","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–226.","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2011, title={Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler}, DOI={<a href=\"https://doi.org/10.1109/ASAP.2011.6043273\">10.1109/ASAP.2011.6043273</a>}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2011}, pages={223–226} }","mla":"Beisel, Tobias, et al. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” <i>Proc. Int. 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Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time.","lang":"eng"}],"doi":"10.1109/ReConFig.2011.59","page":"55-60","quality_controlled":"1","publication":"Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","ddc":["040"],"type":"conference","citation":{"ieee":"M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,” in <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 2011, pp. 55–60, doi: <a href=\"https://doi.org/10.1109/ReConFig.2011.59\">10.1109/ReConFig.2011.59</a>.","chicago":"Happe, Markus, Andreas Agne, and Christian Plessl. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” In <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 55–60. IEEE, 2011. <a href=\"https://doi.org/10.1109/ReConFig.2011.59\">https://doi.org/10.1109/ReConFig.2011.59</a>.","ama":"Happe M, Agne A, Plessl C. Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. In: <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2011:55-60. doi:<a href=\"https://doi.org/10.1109/ReConFig.2011.59\">10.1109/ReConFig.2011.59</a>","apa":"Happe, M., Agne, A., &#38; Plessl, C. (2011). Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 55–60. <a href=\"https://doi.org/10.1109/ReConFig.2011.59\">https://doi.org/10.1109/ReConFig.2011.59</a>","short":"M. Happe, A. Agne, C. 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IEEE Computer Society, 2010. <a href=\"https://doi.org/10.1109/ASAP.2010.5540798\">https://doi.org/10.1109/ASAP.2010.5540798</a>.","ieee":"T. Beisel, M. Niekamp, and C. Plessl, “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators,” in <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 2010, pp. 65–72, doi: <a href=\"https://doi.org/10.1109/ASAP.2010.5540798\">10.1109/ASAP.2010.5540798</a>."},"user_id":"15278","language":[{"iso":"eng"}],"type":"conference","year":"2010","publication_identifier":{"isbn":["978-1-4244-6965-9"]},"status":"public","date_created":"2018-04-05T16:39:34Z","quality_controlled":"1","publication":"Proc. Int. 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IEEE Globecom Workshop on Network of the Future (FutureNet)</i>. IEEE; 2010:372-376. doi:<a href=\"https://doi.org/10.1109/GLOCOMW.2010.5700341\">10.1109/GLOCOMW.2010.5700341</a>","apa":"Keller, A., Plattner, B., Lübbers, E., Platzner, M., &#38; Plessl, C. (2010). Reconfigurable Nodes for Future Networks. <i>Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)</i>, 372–376. <a href=\"https://doi.org/10.1109/GLOCOMW.2010.5700341\">https://doi.org/10.1109/GLOCOMW.2010.5700341</a>","short":"A. Keller, B. Plattner, E. Lübbers, M. Platzner, C. Plessl, in: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–376.","mla":"Keller, Ariane, et al. “Reconfigurable Nodes for Future Networks.” <i>Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)</i>, IEEE, 2010, pp. 372–76, doi:<a href=\"https://doi.org/10.1109/GLOCOMW.2010.5700341\">10.1109/GLOCOMW.2010.5700341</a>.","bibtex":"@inproceedings{Keller_Plattner_Lübbers_Platzner_Plessl_2010, title={Reconfigurable Nodes for Future Networks}, DOI={<a href=\"https://doi.org/10.1109/GLOCOMW.2010.5700341\">10.1109/GLOCOMW.2010.5700341</a>}, booktitle={Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)}, publisher={IEEE}, author={Keller, Ariane and Plattner, Bernhard and Lübbers, Enno and Platzner, Marco and Plessl, Christian}, year={2010}, pages={372–376} }"},"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"author":[{"first_name":"Ariane","full_name":"Keller, Ariane","last_name":"Keller"},{"last_name":"Plattner","first_name":"Bernhard","full_name":"Plattner, Bernhard"},{"full_name":"Lübbers, Enno","first_name":"Enno","last_name":"Lübbers"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"},{"id":"16153","last_name":"Plessl","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"title":"Reconfigurable Nodes for Future Networks","doi":"10.1109/GLOCOMW.2010.5700341","page":"372-376","_id":"2206","date_updated":"2023-09-26T13:51:00Z","publisher":"IEEE","date_created":"2018-04-04T09:36:16Z","publication":"Proc. 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Networked Sensing Systems (INSS)</i>. IEEE; 2010:245-248. doi:<a href=\"https://doi.org/10.1109/INSS.2010.5572211\">10.1109/INSS.2010.5572211</a>","ieee":"M. Woehrle, C. Plessl, and L. Thiele, “Rupeas: Ruby Powered Event Analysis DSL,” in <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>, 2010, pp. 245–248, doi: <a href=\"https://doi.org/10.1109/INSS.2010.5572211\">10.1109/INSS.2010.5572211</a>.","chicago":"Woehrle, Matthias, Christian Plessl, and Lothar Thiele. “Rupeas: Ruby Powered Event Analysis DSL.” In <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>, 245–48. IEEE, 2010. <a href=\"https://doi.org/10.1109/INSS.2010.5572211\">https://doi.org/10.1109/INSS.2010.5572211</a>.","bibtex":"@inproceedings{Woehrle_Plessl_Thiele_2010, title={Rupeas: Ruby Powered Event Analysis DSL}, DOI={<a href=\"https://doi.org/10.1109/INSS.2010.5572211\">10.1109/INSS.2010.5572211</a>}, booktitle={Proc. Int. Conf. Networked Sensing Systems (INSS)}, publisher={IEEE}, author={Woehrle, Matthias and Plessl, Christian and Thiele, Lothar}, year={2010}, pages={245–248} }","mla":"Woehrle, Matthias, et al. “Rupeas: Ruby Powered Event Analysis DSL.” <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>, IEEE, 2010, pp. 245–48, doi:<a href=\"https://doi.org/10.1109/INSS.2010.5572211\">10.1109/INSS.2010.5572211</a>.","short":"M. Woehrle, C. Plessl, L. Thiele, in: Proc. Int. Conf. Networked Sensing Systems (INSS), IEEE, 2010, pp. 245–248."},"user_id":"15278","doi":"10.1109/INSS.2010.5572211","title":"Rupeas: Ruby Powered Event Analysis DSL","author":[{"full_name":"Woehrle, Matthias","first_name":"Matthias","last_name":"Woehrle"},{"full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982"},{"first_name":"Lothar","full_name":"Thiele, Lothar","last_name":"Thiele"}],"extern":"1"},{"citation":{"bibtex":"@inproceedings{Kenter_Platzner_Plessl_Kauschke_2010, title={Performance Estimation for the Exploration of CPU-Accelerator Architectures}, booktitle={Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)}, author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}, editor={Hammami, Omar and Larrabee, Sandra}, year={2010} }","mla":"Kenter, Tobias, et al. “Performance Estimation for the Exploration of CPU-Accelerator Architectures.” <i>Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)</i>, edited by Omar Hammami and Sandra Larrabee, 2010.","short":"T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: O. Hammami, S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), 2010.","apa":"Kenter, T., Platzner, M., Plessl, C., &#38; Kauschke, M. (2010). Performance Estimation for the Exploration of CPU-Accelerator Architectures. In O. Hammami &#38; S. Larrabee (Eds.), <i>Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)</i>.","ama":"Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation for the Exploration of CPU-Accelerator Architectures. In: Hammami O, Larrabee S, eds. <i>Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)</i>. ; 2010.","ieee":"T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation for the Exploration of CPU-Accelerator Architectures,” in <i>Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)</i>, 2010.","chicago":"Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation for the Exploration of CPU-Accelerator Architectures.” In <i>Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)</i>, edited by Omar Hammami and Sandra Larrabee, 2010."},"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Performance Estimation for the Exploration of CPU-Accelerator Architectures","author":[{"id":"3145","last_name":"Kenter","first_name":"Tobias","full_name":"Kenter, Tobias"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"},{"full_name":"Plessl, Christian","first_name":"Christian","last_name":"Plessl","id":"16153","orcid":"0000-0001-5728-9982"},{"last_name":"Kauschke","full_name":"Kauschke, Michael","first_name":"Michael"}],"editor":[{"first_name":"Omar","full_name":"Hammami, Omar","last_name":"Hammami"},{"first_name":"Sandra","full_name":"Larrabee, Sandra","last_name":"Larrabee"}],"_id":"2228","date_updated":"2023-09-26T13:50:04Z","quality_controlled":"1","publication":"Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)","date_created":"2018-04-05T16:43:04Z","year":"2010","type":"conference","language":[{"iso":"eng"}],"status":"public"},{"date_created":"2018-04-16T15:09:19Z","year":"2009","type":"report","language":[{"iso":"eng"}],"status":"public","_id":"2353","report_number":"TIK-Report 290","date_updated":"2022-01-06T06:55:56Z","title":"Rupeas: Ruby Powered Event Analysis DSL","author":[{"last_name":"Woehrle","full_name":"Woehrle, Matthias","first_name":"Matthias"},{"full_name":"Plessl, Christian","first_name":"Christian","last_name":"Plessl","id":"16153","orcid":"0000-0001-5728-9982"},{"last_name":"Thiele","full_name":"Thiele, Lothar","first_name":"Lothar"}],"extern":"1","place":"Computer Engineering and Networks Lab, ETH Zurich","abstract":[{"lang":"eng","text":"Wireless Sensor Networks (WSNs) are unique embedded computation systems for distributed sensing of a dispersed phenomenon. While being a strongly concurrent distributed system, its embedded aspects with severe resource limitations and the wireless communication requires a fusion of technologies and methodologies from very different fields. As WSNs are deployed in remote locations for long-term unattended operation, assurance of correct functioning of the system is of prime concern. Thus, the design and development of WSNs requires specialized tools to allow for testing and debugging the system. To this end, we present a framework for analyzing and checking WSNs based on collected events during system operation. It allows for abstracting from the event trace by means of behavioral queries and uses assertions for checking the accordance of an execution to its specification. The framework is independent from WSN test platforms, applications and logging semantics and thus generally applicable for analyzing event logs of WSN test executions. "}],"citation":{"short":"M. Woehrle, C. Plessl, L. Thiele, Rupeas: Ruby Powered Event Analysis DSL, Computer Engineering and Networks Lab, ETH Zurich, 2009.","mla":"Woehrle, Matthias, et al. <i>Rupeas: Ruby Powered Event Analysis DSL</i>. 2009.","bibtex":"@book{Woehrle_Plessl_Thiele_2009, place={Computer Engineering and Networks Lab, ETH Zurich}, title={Rupeas: Ruby Powered Event Analysis DSL}, author={Woehrle, Matthias and Plessl, Christian and Thiele, Lothar}, year={2009} }","chicago":"Woehrle, Matthias, Christian Plessl, and Lothar Thiele. <i>Rupeas: Ruby Powered Event Analysis DSL</i>. Computer Engineering and Networks Lab, ETH Zurich, 2009.","ieee":"M. Woehrle, C. Plessl, and L. Thiele, <i>Rupeas: Ruby Powered Event Analysis DSL</i>. Computer Engineering and Networks Lab, ETH Zurich, 2009.","apa":"Woehrle, M., Plessl, C., &#38; Thiele, L. (2009). <i>Rupeas: Ruby Powered Event Analysis DSL</i>. Computer Engineering and Networks Lab, ETH Zurich.","ama":"Woehrle M, Plessl C, Thiele L. <i>Rupeas: Ruby Powered Event Analysis DSL</i>. Computer Engineering and Networks Lab, ETH Zurich; 2009."},"user_id":"16153","keyword":["Rupeas","DSL","WSN","testing"],"department":[{"_id":"27"},{"_id":"518"}]}]