---
_id: '2392'
author:
- first_name: Matthias
full_name: Woehrle, Matthias
last_name: Woehrle
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Jan
full_name: Beutel, Jan
last_name: Beutel
- first_name: Lothar
full_name: Thiele, Lothar
last_name: Thiele
citation:
ama: 'Woehrle M, Plessl C, Beutel J, Thiele L. Increasing the Reliability of Wireless
Sensor Networks with a Distributed Testing Framework. In: Proc. Workshop on
Embedded Networked Sensors (EmNets). ACM; 2007:93-97. doi:10.1145/1278972.1278996'
apa: Woehrle, M., Plessl, C., Beutel, J., & Thiele, L. (2007). Increasing the
Reliability of Wireless Sensor Networks with a Distributed Testing Framework.
Proc. Workshop on Embedded Networked Sensors (EmNets), 93–97. https://doi.org/10.1145/1278972.1278996
bibtex: '@inproceedings{Woehrle_Plessl_Beutel_Thiele_2007, place={New York, NY,
USA}, title={Increasing the Reliability of Wireless Sensor Networks with a Distributed
Testing Framework}, DOI={10.1145/1278972.1278996},
booktitle={Proc. Workshop on Embedded Networked Sensors (EmNets)}, publisher={ACM},
author={Woehrle, Matthias and Plessl, Christian and Beutel, Jan and Thiele, Lothar},
year={2007}, pages={93–97} }'
chicago: 'Woehrle, Matthias, Christian Plessl, Jan Beutel, and Lothar Thiele. “Increasing
the Reliability of Wireless Sensor Networks with a Distributed Testing Framework.”
In Proc. Workshop on Embedded Networked Sensors (EmNets), 93–97. New York,
NY, USA: ACM, 2007. https://doi.org/10.1145/1278972.1278996.'
ieee: 'M. Woehrle, C. Plessl, J. Beutel, and L. Thiele, “Increasing the Reliability
of Wireless Sensor Networks with a Distributed Testing Framework,” in Proc.
Workshop on Embedded Networked Sensors (EmNets), 2007, pp. 93–97, doi: 10.1145/1278972.1278996.'
mla: Woehrle, Matthias, et al. “Increasing the Reliability of Wireless Sensor Networks
with a Distributed Testing Framework.” Proc. Workshop on Embedded Networked
Sensors (EmNets), ACM, 2007, pp. 93–97, doi:10.1145/1278972.1278996.
short: 'M. Woehrle, C. Plessl, J. Beutel, L. Thiele, in: Proc. Workshop on Embedded
Networked Sensors (EmNets), ACM, New York, NY, USA, 2007, pp. 93–97.'
date_created: 2018-04-17T13:34:42Z
date_updated: 2023-09-26T14:00:38Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/1278972.1278996
keyword:
- WSN
- testing
- distributed
- embedded
language:
- iso: eng
page: 93-97
place: New York, NY, USA
publication: Proc. Workshop on Embedded Networked Sensors (EmNets)
publication_identifier:
isbn:
- 978-1-59593-694-3
publisher: ACM
quality_controlled: '1'
status: public
title: Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing
Framework
type: conference
user_id: '15278'
year: '2007'
...
---
_id: '2393'
author:
- first_name: Jan
full_name: Beutel, Jan
last_name: Beutel
- first_name: Matthias
full_name: Dyer, Matthias
last_name: Dyer
- first_name: Roman
full_name: Lim, Roman
last_name: Lim
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Matthias
full_name: Woehrle, Matthias
last_name: Woehrle
- first_name: Mustafa
full_name: Yuecel, Mustafa
last_name: Yuecel
- first_name: Lothar
full_name: Thiele, Lothar
last_name: Thiele
citation:
ama: 'Beutel J, Dyer M, Lim R, et al. Automated Wireless Sensor Network Testing.
In: Proc. Int. Conf. Networked Sensing Systems (INSS). IEEE; 2007:303-303.
doi:10.1109/INSS.2007.4297445'
apa: Beutel, J., Dyer, M., Lim, R., Plessl, C., Woehrle, M., Yuecel, M., & Thiele,
L. (2007). Automated Wireless Sensor Network Testing. Proc. Int. Conf. Networked
Sensing Systems (INSS), 303–303. https://doi.org/10.1109/INSS.2007.4297445
bibtex: '@inproceedings{Beutel_Dyer_Lim_Plessl_Woehrle_Yuecel_Thiele_2007, place={Piscataway,
NJ, USA}, title={Automated Wireless Sensor Network Testing}, DOI={10.1109/INSS.2007.4297445},
booktitle={Proc. Int. Conf. Networked Sensing Systems (INSS)}, publisher={IEEE},
author={Beutel, Jan and Dyer, Matthias and Lim, Roman and Plessl, Christian and
Woehrle, Matthias and Yuecel, Mustafa and Thiele, Lothar}, year={2007}, pages={303–303}
}'
chicago: 'Beutel, Jan, Matthias Dyer, Roman Lim, Christian Plessl, Matthias Woehrle,
Mustafa Yuecel, and Lothar Thiele. “Automated Wireless Sensor Network Testing.”
In Proc. Int. Conf. Networked Sensing Systems (INSS), 303–303. Piscataway,
NJ, USA: IEEE, 2007. https://doi.org/10.1109/INSS.2007.4297445.'
ieee: 'J. Beutel et al., “Automated Wireless Sensor Network Testing,” in
Proc. Int. Conf. Networked Sensing Systems (INSS), 2007, pp. 303–303, doi:
10.1109/INSS.2007.4297445.'
mla: Beutel, Jan, et al. “Automated Wireless Sensor Network Testing.” Proc. Int.
Conf. Networked Sensing Systems (INSS), IEEE, 2007, pp. 303–303, doi:10.1109/INSS.2007.4297445.
short: 'J. Beutel, M. Dyer, R. Lim, C. Plessl, M. Woehrle, M. Yuecel, L. Thiele,
in: Proc. Int. Conf. Networked Sensing Systems (INSS), IEEE, Piscataway, NJ, USA,
2007, pp. 303–303.'
date_created: 2018-04-17T13:35:55Z
date_updated: 2023-09-26T14:00:58Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/INSS.2007.4297445
keyword:
- WSN
- testing
- verification
language:
- iso: eng
page: 303-303
place: Piscataway, NJ, USA
publication: Proc. Int. Conf. Networked Sensing Systems (INSS)
publication_identifier:
isbn:
- 1-4244-1231-5
publisher: IEEE
quality_controlled: '1'
status: public
title: Automated Wireless Sensor Network Testing
type: conference
user_id: '15278'
year: '2007'
...
---
_id: '2404'
abstract:
- lang: eng
text: ' In this thesis, we propose to use a reconfigurable processor as main computation
element in embedded systems for applications from the multi-media and communications
domain. A reconfigurable processor integrates an embedded CPU core with a Reconfigurable
Processing Unit (RPU). Many of our target applications require real-time signal-processing
of data streams and expose a high computational demand. The key challenge in designing
embedded systems for these applications is to find an implementation that satisfies
the performance goals and is adaptable to new applications, while the system cost
is minimized. Implementations that solely use an embedded CPU are likely to miss
the performance goals. Application-Specific Integrated Circuit (ASIC)-based coprocessors
can be used for some high-volume products with fixed functions, but fall short
for systems with varying applications. We argue that a reconfigurable processor
with a coarse-grained, dynamically reconfigurable array of modest size provides
an attractive implementation platform for our application domain. The computational
intensive application kernels are executed on the RPU, while the remaining parts
of the application are executed on the CPU. Reconfigurable hardware allows for
implementing application specific coprocessors with a high performance, while
the function of the coprocessor can still be adapted due to the programmability.
So far, reconfigurable technology is used in embedded systems primarily with static
configurations, e.g., for implementing glue-logic, replacing ASICs, and for implementing
fixed-function coprocessors. Changing the configuration at runtime enables a number
of interesting application modes, e.g., on-demand loading of coprocessors and
time-multiplexed execution of coprocessors, which is commonly denoted as hardware
virtualization. While the use of static configurations is well understood and
supported by design-tools, the role of dynamic reconfiguration is not well investigated
yet. Current application specification methods and design-tools do not provide
an end-to-end tool-flow that considers dynamic reconfiguration. A key idea of
our approach is to reduce system cost by keeping the size of the reconfigurable
array small and to use hardware virtualization techniques to compensate for the
limited hardware resources. The main contribution of this thesis is the codesign
of a reconfigurable processor architecture named ZIPPY, the corresponding hardware
and software implementation tools, and an application specification model which
explicitly considers hardware virtualization. The ZIPPY architecture is widely
parametrized and allows for specifying a whole family of processor architectures.
The implementation tools are also parametrized and can target any architectural
variant. We evaluate the performance of the architecture with a system-level,
cycle-accurate cosimulation framework. This framework enables us to perform design-space
exploration for a variety of reconfigurable processor architectures. With two
case studies, we demonstrate, that hardware virtualization on the Zippy architecture
is feasible and enables us to trade-off performance for area in embedded systems.
Finally, we present a novel method for optimal temporal partitioning of sequential
circuits, which is an important form of hardware virtualization. The method based
on Slowdown and Retiming allows us to decompose any sequential circuit into a
number of smaller, communicating subcircuits that can be executed on a dynamically
reconfigurable architecture. '
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Plessl C. Hardware Virtualization on a Coarse-Grained Reconfigurable Processor.
Aachen, Germany: Shaker Verlag; 2006. doi:10.2370/9783832255619'
apa: 'Plessl, C. (2006). Hardware virtualization on a coarse-grained reconfigurable
processor. Aachen, Germany: Shaker Verlag. https://doi.org/10.2370/9783832255619'
bibtex: '@book{Plessl_2006, place={Aachen, Germany}, series={Technische Informatik},
title={Hardware virtualization on a coarse-grained reconfigurable processor},
DOI={10.2370/9783832255619},
publisher={Shaker Verlag}, author={Plessl, Christian}, year={2006}, collection={Technische
Informatik} }'
chicago: 'Plessl, Christian. Hardware Virtualization on a Coarse-Grained Reconfigurable
Processor. Technische Informatik. Aachen, Germany: Shaker Verlag, 2006. https://doi.org/10.2370/9783832255619.'
ieee: 'C. Plessl, Hardware virtualization on a coarse-grained reconfigurable
processor. Aachen, Germany: Shaker Verlag, 2006.'
mla: Plessl, Christian. Hardware Virtualization on a Coarse-Grained Reconfigurable
Processor. Shaker Verlag, 2006, doi:10.2370/9783832255619.
short: C. Plessl, Hardware Virtualization on a Coarse-Grained Reconfigurable Processor,
Shaker Verlag, Aachen, Germany, 2006.
date_created: 2018-04-17T13:46:27Z
date_updated: 2022-01-06T06:56:06Z
department:
- _id: '518'
doi: 10.2370/9783832255619
keyword:
- Zippy
place: Aachen, Germany
publication_identifier:
isbn:
- 978-3-8322-5561-3
publisher: Shaker Verlag
series_title: Technische Informatik
status: public
title: Hardware virtualization on a coarse-grained reconfigurable processor
type: dissertation
user_id: '24135'
year: '2006'
...
---
_id: '2401'
abstract:
- lang: eng
text: ' This paper presents a novel method for optimal temporal partitioning of
sequential circuits for time-multiplexed reconfigurable architectures. The method
bases on slowdown and retiming and maximizes the circuit''s performance during
execution while restricting the size of the partitions to respect the resource
constraints of the reconfigurable architecture. We provide a mixed integer linear
program (MILP) formulation of the problem, which can be solved exactly. In contrast
to related work, our approach optimizes performance directly, takes structural
modifications of the circuit into account, and is extensible. We present the application
of the new method to temporal partitioning for a coarse-grained reconfigurable
architecture. '
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Lothar
full_name: Thiele, Lothar
last_name: Thiele
citation:
ama: 'Plessl C, Platzner M, Thiele L. Optimal Temporal Partitioning based on Slowdown
and Retiming. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT).
IEEE Computer Society; 2006:345-348. doi:10.1109/FPT.2006.270344'
apa: Plessl, C., Platzner, M., & Thiele, L. (2006). Optimal Temporal Partitioning
based on Slowdown and Retiming. In Proc. Int. Conf. on Field Programmable Technology
(ICFPT) (pp. 345–348). IEEE Computer Society. https://doi.org/10.1109/FPT.2006.270344
bibtex: '@inproceedings{Plessl_Platzner_Thiele_2006, title={Optimal Temporal Partitioning
based on Slowdown and Retiming}, DOI={10.1109/FPT.2006.270344},
booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE
Computer Society}, author={Plessl, Christian and Platzner, Marco and Thiele, Lothar},
year={2006}, pages={345–348} }'
chicago: Plessl, Christian, Marco Platzner, and Lothar Thiele. “Optimal Temporal
Partitioning Based on Slowdown and Retiming.” In Proc. Int. Conf. on Field
Programmable Technology (ICFPT), 345–48. IEEE Computer Society, 2006. https://doi.org/10.1109/FPT.2006.270344.
ieee: C. Plessl, M. Platzner, and L. Thiele, “Optimal Temporal Partitioning based
on Slowdown and Retiming,” in Proc. Int. Conf. on Field Programmable Technology
(ICFPT), 2006, pp. 345–348.
mla: Plessl, Christian, et al. “Optimal Temporal Partitioning Based on Slowdown
and Retiming.” Proc. Int. Conf. on Field Programmable Technology (ICFPT),
IEEE Computer Society, 2006, pp. 345–48, doi:10.1109/FPT.2006.270344.
short: 'C. Plessl, M. Platzner, L. Thiele, in: Proc. Int. Conf. on Field Programmable
Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–348.'
date_created: 2018-04-17T13:43:21Z
date_updated: 2022-01-06T06:56:05Z
department:
- _id: '518'
- _id: '78'
doi: 10.1109/FPT.2006.270344
keyword:
- temporal partitioning
- retiming
- ILP
page: 345-348
publication: Proc. Int. Conf. on Field Programmable Technology (ICFPT)
publisher: IEEE Computer Society
status: public
title: Optimal Temporal Partitioning based on Slowdown and Retiming
type: conference
user_id: '24135'
year: '2006'
...
---
_id: '2411'
abstract:
- lang: eng
text: ' This paper motivates the use of hardware virtualization on coarse-grained
reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context
hybrid CPU with architectural support for efficient hardware virtualization. The
architectural details and the corresponding tool flow are outlined. As a case
study, we compare the non-virtualized and the virtualized execution of an ADPCM
decoder. '
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Plessl C, Platzner M. Zippy – A coarse-grained reconfigurable array with support
for hardware virtualization. In: Proc. Int. Conf. on Application-Specific Systems,
Architectures, and Processors (ASAP). IEEE Computer Society; 2005:213-218.
doi:10.1109/ASAP.2005.69'
apa: Plessl, C., & Platzner, M. (2005). Zippy – A coarse-grained reconfigurable
array with support for hardware virtualization. In Proc. Int. Conf. on Application-Specific
Systems, Architectures, and Processors (ASAP) (pp. 213–218). IEEE Computer
Society. https://doi.org/10.1109/ASAP.2005.69
bibtex: '@inproceedings{Plessl_Platzner_2005, title={Zippy – A coarse-grained reconfigurable
array with support for hardware virtualization}, DOI={10.1109/ASAP.2005.69},
booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and
Processors (ASAP)}, publisher={IEEE Computer Society}, author={Plessl, Christian
and Platzner, Marco}, year={2005}, pages={213–218} }'
chicago: Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable
Array with Support for Hardware Virtualization.” In Proc. Int. Conf. on Application-Specific
Systems, Architectures, and Processors (ASAP), 213–18. IEEE Computer Society,
2005. https://doi.org/10.1109/ASAP.2005.69.
ieee: C. Plessl and M. Platzner, “Zippy – A coarse-grained reconfigurable array
with support for hardware virtualization,” in Proc. Int. Conf. on Application-Specific
Systems, Architectures, and Processors (ASAP), 2005, pp. 213–218.
mla: Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable
Array with Support for Hardware Virtualization.” Proc. Int. Conf. on Application-Specific
Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005,
pp. 213–18, doi:10.1109/ASAP.2005.69.
short: 'C. Plessl, M. Platzner, in: Proc. Int. Conf. on Application-Specific Systems,
Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–218.'
date_created: 2018-04-17T14:34:03Z
date_updated: 2022-01-06T06:56:07Z
department:
- _id: '518'
- _id: '78'
doi: 10.1109/ASAP.2005.69
keyword:
- Zippy
page: 213-218
publication: Proc. Int. Conf. on Application-Specific Systems, Architectures, and
Processors (ASAP)
publisher: IEEE Computer Society
status: public
title: Zippy – A coarse-grained reconfigurable array with support for hardware virtualization
type: conference
user_id: '24135'
year: '2005'
...
---
_id: '2412'
abstract:
- lang: eng
text: ' Reconfigurable architectures that tightly integrate a standard CPU core
with a field-programmable hardware structure have recently been receiving impact
of these design decisions on the overall system performance is a challenging task.
In this paper, we first present a framework for the cycle-accurate performance
evaluation of hybrid reconfigurable processors on the system level. Then, we discuss
a reconfigurable processor for data-streaming applications, which attaches a coarse-grained
reconfigurable unit to the coprocessor interface of a standard embedded CPU core.
By means of a case study we evaluate the system-level impact of certain design
features for the reconfigurable unit, such as multiple contexts, register replication,
and hardware context scheduling. The results illustrate that a system-level evaluation
framework is of paramount importance for studying the architectural trade-offs
and optimizing design parameters for reconfigurable processors.'
author:
- first_name: Rolf
full_name: Enzler, Rolf
last_name: Enzler
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Enzler R, Plessl C, Platzner M. System-level performance evaluation of reconfigurable
processors. Microprocessors and Microsystems. 2005;29(2-3):63-73. doi:10.1016/j.micpro.2004.06.004
apa: Enzler, R., Plessl, C., & Platzner, M. (2005). System-level performance
evaluation of reconfigurable processors. Microprocessors and Microsystems,
29(2–3), 63–73. https://doi.org/10.1016/j.micpro.2004.06.004
bibtex: '@article{Enzler_Plessl_Platzner_2005, title={System-level performance evaluation
of reconfigurable processors}, volume={29}, DOI={10.1016/j.micpro.2004.06.004},
number={2–3}, journal={Microprocessors and Microsystems}, publisher={Elsevier},
author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2005},
pages={63–73} }'
chicago: 'Enzler, Rolf, Christian Plessl, and Marco Platzner. “System-Level Performance
Evaluation of Reconfigurable Processors.” Microprocessors and Microsystems
29, no. 2–3 (2005): 63–73. https://doi.org/10.1016/j.micpro.2004.06.004.'
ieee: R. Enzler, C. Plessl, and M. Platzner, “System-level performance evaluation
of reconfigurable processors,” Microprocessors and Microsystems, vol. 29,
no. 2–3, pp. 63–73, 2005.
mla: Enzler, Rolf, et al. “System-Level Performance Evaluation of Reconfigurable
Processors.” Microprocessors and Microsystems, vol. 29, no. 2–3, Elsevier,
2005, pp. 63–73, doi:10.1016/j.micpro.2004.06.004.
short: R. Enzler, C. Plessl, M. Platzner, Microprocessors and Microsystems 29 (2005)
63–73.
date_created: 2018-04-17T14:36:10Z
date_updated: 2022-01-06T06:56:07Z
department:
- _id: '518'
- _id: '78'
doi: 10.1016/j.micpro.2004.06.004
intvolume: ' 29'
issue: 2-3
keyword:
- FPGA
- reconfigurable computing
- co-simulation
- Zippy
page: 63-73
publication: Microprocessors and Microsystems
publisher: Elsevier
status: public
title: System-level performance evaluation of reconfigurable processors
type: journal_article
user_id: '24135'
volume: 29
year: '2005'
...
---
_id: '2415'
abstract:
- lang: eng
text: 'In this paper we introduce to virtualization of hardware on reconfigurable
devices. We identify three main approaches denoted with temporal partitioning,
virtualized execution, and virtual machine. For each virtualization approach,
we discuss the application models, the required execution architectures, the design
tools and the run-time systems. Then, we survey a selection of important projects
in the field. '
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Plessl C, Platzner M. Virtualization of Hardware – Introduction and Survey.
In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA). CSREA Press; 2004:63-69.'
apa: Plessl, C., & Platzner, M. (2004). Virtualization of Hardware – Introduction
and Survey. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and
Algorithms (ERSA) (pp. 63–69). CSREA Press.
bibtex: '@inproceedings{Plessl_Platzner_2004, title={Virtualization of Hardware
– Introduction and Survey}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian
and Platzner, Marco}, year={2004}, pages={63–69} }'
chicago: Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction
and Survey.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and
Algorithms (ERSA), 63–69. CSREA Press, 2004.
ieee: C. Plessl and M. Platzner, “Virtualization of Hardware – Introduction and
Survey,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA), 2004, pp. 63–69.
mla: Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction
and Survey.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and
Algorithms (ERSA), CSREA Press, 2004, pp. 63–69.
short: 'C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), CSREA Press, 2004, pp. 63–69.'
date_created: 2018-04-17T14:45:57Z
date_updated: 2022-01-06T06:56:08Z
department:
- _id: '518'
- _id: '78'
keyword:
- hardware virtualization
page: 63-69
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publisher: CSREA Press
status: public
title: Virtualization of Hardware – Introduction and Survey
type: conference
user_id: '24135'
year: '2004'
...
---
_id: '2418'
abstract:
- lang: eng
text: ' This paper presents TKDM, a PC-based high-performance reconfigurable computing
environment. The TKDM hardware consists of an FPGA module that uses the DIMM (dual
inline memory module) bus for high-bandwidth and low-latency communication with
the host CPU. The system''s firmware is integrated with the Linux host operating
system and offers functions for data communication and FPGA reconfiguration. The
intended use of TKDM is that of a dynamically reconfigurable co-processor for
data streaming applications. The system''s firmware can be customized for specific
application domains to facilitate simple and easy-to-use programming interfaces. '
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Plessl C, Platzner M. TKDM – A Reconfigurable Co-processor in a PC’s Memory
Slot. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE
Computer Society; 2003:252-259. doi:10.1109/FPT.2003.1275755'
apa: Plessl, C., & Platzner, M. (2003). TKDM – A Reconfigurable Co-processor
in a PC’s Memory Slot. In Proc. Int. Conf. on Field Programmable Technology
(ICFPT) (pp. 252–259). IEEE Computer Society. https://doi.org/10.1109/FPT.2003.1275755
bibtex: '@inproceedings{Plessl_Platzner_2003, title={TKDM – A Reconfigurable Co-processor
in a PC’s Memory Slot}, DOI={10.1109/FPT.2003.1275755},
booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE
Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2003},
pages={252–259} }'
chicago: Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor
in a PC’s Memory Slot.” In Proc. Int. Conf. on Field Programmable Technology
(ICFPT), 252–59. IEEE Computer Society, 2003. https://doi.org/10.1109/FPT.2003.1275755.
ieee: C. Plessl and M. Platzner, “TKDM – A Reconfigurable Co-processor in a PC’s
Memory Slot,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT),
2003, pp. 252–259.
mla: Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor
in a PC’s Memory Slot.” Proc. Int. Conf. on Field Programmable Technology (ICFPT),
IEEE Computer Society, 2003, pp. 252–59, doi:10.1109/FPT.2003.1275755.
short: 'C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Technology
(ICFPT), IEEE Computer Society, 2003, pp. 252–259.'
date_created: 2018-04-17T15:03:34Z
date_updated: 2022-01-06T06:56:09Z
department:
- _id: '518'
- _id: '78'
doi: 10.1109/FPT.2003.1275755
keyword:
- coprocessor
- DIMM
- memory bus
- FPGA
- high performance computing
page: 252-259
publication: Proc. Int. Conf. on Field Programmable Technology (ICFPT)
publisher: IEEE Computer Society
status: public
title: TKDM – A Reconfigurable Co-processor in a PC's Memory Slot
type: conference
user_id: '24135'
year: '2003'
...
---
_id: '2419'
abstract:
- lang: eng
text: 'Wearable computers are embedded into the mobile environment of their users.
A design challenge for wearable systems is to combine the high performance required
for tasks such as video decoding with the low energy consumption required to maximise
battery runtimes and the flexibility demanded by the dynamics of the environment
and the applications. In this paper, we demonstrate that reconfigurable hardware
technology is able to answer this challenge. We present the concept and the prototype
implementation of an autonomous wearable unit with reconfigurable modules (WURM).
We discuss experiments that show the uses of reconfigurable hardware in WURM:
ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with
an operating system layer for WURM.'
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Rolf
full_name: Enzler, Rolf
last_name: Enzler
- first_name: Herbert
full_name: Walder, Herbert
last_name: Walder
- first_name: Jan
full_name: Beutel, Jan
last_name: Beutel
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Lothar
full_name: Thiele, Lothar
last_name: Thiele
- first_name: Gerhard
full_name: Tröster, Gerhard
last_name: Tröster
citation:
ama: Plessl C, Enzler R, Walder H, et al. The Case for Reconfigurable Hardware in
Wearable Computing. Personal and Ubiquitous Computing. 2003;7(5):299-308.
doi:10.1007/s00779-003-0243-x
apa: Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., Thiele, L., &
Tröster, G. (2003). The Case for Reconfigurable Hardware in Wearable Computing.
Personal and Ubiquitous Computing, 7(5), 299–308. https://doi.org/10.1007/s00779-003-0243-x
bibtex: '@article{Plessl_Enzler_Walder_Beutel_Platzner_Thiele_Tröster_2003, title={The
Case for Reconfigurable Hardware in Wearable Computing}, volume={7}, DOI={10.1007/s00779-003-0243-x},
number={5}, journal={Personal and Ubiquitous Computing}, publisher={Springer},
author={Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan
and Platzner, Marco and Thiele, Lothar and Tröster, Gerhard}, year={2003}, pages={299–308}
}'
chicago: 'Plessl, Christian, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner,
Lothar Thiele, and Gerhard Tröster. “The Case for Reconfigurable Hardware in Wearable
Computing.” Personal and Ubiquitous Computing 7, no. 5 (2003): 299–308.
https://doi.org/10.1007/s00779-003-0243-x.'
ieee: C. Plessl et al., “The Case for Reconfigurable Hardware in Wearable
Computing,” Personal and Ubiquitous Computing, vol. 7, no. 5, pp. 299–308,
2003.
mla: Plessl, Christian, et al. “The Case for Reconfigurable Hardware in Wearable
Computing.” Personal and Ubiquitous Computing, vol. 7, no. 5, Springer,
2003, pp. 299–308, doi:10.1007/s00779-003-0243-x.
short: C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, G. Tröster,
Personal and Ubiquitous Computing 7 (2003) 299–308.
date_created: 2018-04-17T15:04:47Z
date_updated: 2022-01-06T06:56:09Z
department:
- _id: '518'
- _id: '78'
doi: 10.1007/s00779-003-0243-x
extern: '1'
intvolume: ' 7'
issue: '5'
language:
- iso: eng
page: 299-308
publication: Personal and Ubiquitous Computing
publisher: Springer
status: public
title: The Case for Reconfigurable Hardware in Wearable Computing
type: journal_article
user_id: '398'
volume: 7
year: '2003'
...
---
_id: '2420'
abstract:
- lang: eng
text: ' This paper presents the acceleration of minimum-cost covering problems by
instance-specific hardware. First, we formulate the minimum-cost covering problem
and discuss a branch \& bound algorithm to solve it. Then we describe instance-specific
hardware architectures that implement branch \& bound in 3-valued logic and use
reduction techniques similar to those found in software solvers. We further present
prototypical accelerator implementations and a corresponding design tool flow.
Our experiments reveal significant raw speedups up to five orders of magnitude
for a set of smaller unate covering problems. Provided that hardware compilation
times can be reduced, we conclude that instance-specific acceleration of hard
minimum-cost covering problems will lead to substantial overall speedups. '
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering.
Journal of Supercomputing. 2003;26(2):109-129. doi:10.1023/a:1024443416592
apa: Plessl, C., & Platzner, M. (2003). Instance-Specific Accelerators for Minimum
Covering. Journal of Supercomputing, 26(2), 109–129. https://doi.org/10.1023/a:1024443416592
bibtex: '@article{Plessl_Platzner_2003, title={Instance-Specific Accelerators for
Minimum Covering}, volume={26}, DOI={10.1023/a:1024443416592},
number={2}, journal={Journal of Supercomputing}, publisher={Kluwer Academic Publishers},
author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={109–129} }'
chicago: 'Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators
for Minimum Covering.” Journal of Supercomputing 26, no. 2 (2003): 109–29.
https://doi.org/10.1023/a:1024443416592.'
ieee: C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,”
Journal of Supercomputing, vol. 26, no. 2, pp. 109–129, 2003.
mla: Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for
Minimum Covering.” Journal of Supercomputing, vol. 26, no. 2, Kluwer Academic
Publishers, 2003, pp. 109–29, doi:10.1023/a:1024443416592.
short: C. Plessl, M. Platzner, Journal of Supercomputing 26 (2003) 109–129.
date_created: 2018-04-17T15:10:00Z
date_updated: 2022-01-06T06:56:10Z
department:
- _id: '518'
- _id: '78'
doi: 10.1023/a:1024443416592
extern: '1'
intvolume: ' 26'
issue: '2'
keyword:
- reconfigurable computing
- instance-specific acceleration
- minimum covering
language:
- iso: eng
page: 109-129
publication: Journal of Supercomputing
publication_identifier:
issn:
- 0920-8542
publisher: Kluwer Academic Publishers
status: public
title: Instance-Specific Accelerators for Minimum Covering
type: journal_article
user_id: '398'
volume: 26
year: '2003'
...
---
_id: '2421'
abstract:
- lang: eng
text: In contrast to processors, current reconfigurable devices totally lack programming
models that would allow for device independent compilation and forward compatibility.
The key to overcome this limitation is hardware virtualization. In this paper,
we resort to a macro-pipelined execution model to achieve hardware virtualization
for data streaming applications. As a hardware implementation we present a hybrid
multi-context architecture that attaches a coarse-grained reconfigurable array
to a host CPU. A co-simulation framework enables cycle-accurate simulation of
the complete architecture. As a case study we map an FIR filter to our virtualized
hardware model and evaluate different designs. We discuss the impact of the number
of contexts and the feature of context state on the speedup and the CPU load.
author:
- first_name: Rolf
full_name: Enzler, Rolf
last_name: Enzler
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Enzler R, Plessl C, Platzner M. Virtualizing Hardware with Multi-Context Reconfigurable
Arrays. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL).
Vol 2778. Lecture Notes in Computer Science (LNCS). Springer; 2003:151-160. doi:10.1007/b12007'
apa: Enzler, R., Plessl, C., & Platzner, M. (2003). Virtualizing Hardware with
Multi-Context Reconfigurable Arrays. In Proc. Int. Conf. on Field Programmable
Logic and Applications (FPL) (Vol. 2778, pp. 151–160). Springer. https://doi.org/10.1007/b12007
bibtex: '@inproceedings{Enzler_Plessl_Platzner_2003, series={Lecture Notes in Computer
Science (LNCS)}, title={Virtualizing Hardware with Multi-Context Reconfigurable
Arrays}, volume={2778}, DOI={10.1007/b12007},
booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)},
publisher={Springer}, author={Enzler, Rolf and Plessl, Christian and Platzner,
Marco}, year={2003}, pages={151–160}, collection={Lecture Notes in Computer Science
(LNCS)} }'
chicago: Enzler, Rolf, Christian Plessl, and Marco Platzner. “Virtualizing Hardware
with Multi-Context Reconfigurable Arrays.” In Proc. Int. Conf. on Field Programmable
Logic and Applications (FPL), 2778:151–60. Lecture Notes in Computer Science
(LNCS). Springer, 2003. https://doi.org/10.1007/b12007.
ieee: R. Enzler, C. Plessl, and M. Platzner, “Virtualizing Hardware with Multi-Context
Reconfigurable Arrays,” in Proc. Int. Conf. on Field Programmable Logic and
Applications (FPL), 2003, vol. 2778, pp. 151–160.
mla: Enzler, Rolf, et al. “Virtualizing Hardware with Multi-Context Reconfigurable
Arrays.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL),
vol. 2778, Springer, 2003, pp. 151–60, doi:10.1007/b12007.
short: 'R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable
Logic and Applications (FPL), Springer, 2003, pp. 151–160.'
date_created: 2018-04-17T15:11:25Z
date_updated: 2022-01-06T06:56:13Z
department:
- _id: '518'
- _id: '78'
doi: 10.1007/b12007
intvolume: ' 2778'
keyword:
- Zippy
- multi-context
- FPGA
page: 151-160
publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)
publisher: Springer
series_title: Lecture Notes in Computer Science (LNCS)
status: public
title: Virtualizing Hardware with Multi-Context Reconfigurable Arrays
type: conference
user_id: '24135'
volume: 2778
year: '2003'
...
---
_id: '2422'
abstract:
- lang: eng
text: Reconfigurable computing architectures aim to dynamically adapt their hardware
to the application at hand. As research shows, the time it takes to reconfigure
the hardware forms an overhead that can significantly impair the benefits of hardware
customization. Multi-context devices are one promising approach to overcome the
limitations posed by long reconfiguration times. In contrast to more traditional
reconfigurable architectures, multi-context devices hold several configurations
on-chip. On demand, the device can quickly switch to another context. In this
paper we present a co-simulation environment to investigate design trade-offs
for hybrid multi-context architectures. Our architectural model comprises a reconfigurable
unit closely coupled to a CPU core. As a case study, we discuss the implementation
of a FIR filter partitioned into several contexts. We outline the mapping process
and present simulation results for single- and multi-context reconfigurable units
coupled with both embedded and high-end CPUs.
author:
- first_name: Rolf
full_name: Enzler, Rolf
last_name: Enzler
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Enzler R, Plessl C, Platzner M. Co-simulation of a Hybrid Multi-Context Architecture.
In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA). CSREA Press; 2003:174-180.'
apa: Enzler, R., Plessl, C., & Platzner, M. (2003). Co-simulation of a Hybrid
Multi-Context Architecture. In Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA) (pp. 174–180). CSREA Press.
bibtex: '@inproceedings{Enzler_Plessl_Platzner_2003, title={Co-simulation of a Hybrid
Multi-Context Architecture}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Enzler, Rolf
and Plessl, Christian and Platzner, Marco}, year={2003}, pages={174–180} }'
chicago: Enzler, Rolf, Christian Plessl, and Marco Platzner. “Co-Simulation of a
Hybrid Multi-Context Architecture.” In Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), 174–80. CSREA Press, 2003.
ieee: R. Enzler, C. Plessl, and M. Platzner, “Co-simulation of a Hybrid Multi-Context
Architecture,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems
and Algorithms (ERSA), 2003, pp. 174–180.
mla: Enzler, Rolf, et al. “Co-Simulation of a Hybrid Multi-Context Architecture.”
Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
CSREA Press, 2003, pp. 174–80.
short: 'R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of
Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 174–180.'
date_created: 2018-04-17T15:12:56Z
date_updated: 2022-01-06T06:56:13Z
department:
- _id: '518'
- _id: '78'
keyword:
- Zippy
- co-simulation
page: 174-180
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publication_identifier:
isbn:
- 1-932415-05-X
publisher: CSREA Press
status: public
title: Co-simulation of a Hybrid Multi-Context Architecture
type: conference
user_id: '24135'
year: '2003'
...
---
_id: '2423'
abstract:
- lang: eng
text: 'Wearable computers are embedded into the mobile environment of the human
body. A design challenge for wearable systems is to combine the high performance
required for tasks such as video decoding with low energy consumption required
to maximize battery runtimes and the flexibility demanded by the dynamics of the
environment and the applications. In this paper, we demonstrate that reconfigurable
hardware technology is able to answer this challenge. We present the concept and
the prototype implementation of an autonomous wearable unit with reconfigurable
modules (WURM). We discuss two experiments that show the uses of reconfigurable
hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we develop
and evaluate task placement techniques used in the operating system layer of WURM.'
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Rolf
full_name: Enzler, Rolf
last_name: Enzler
- first_name: Herbert
full_name: Walder, Herbert
last_name: Walder
- first_name: Jan
full_name: Beutel, Jan
last_name: Beutel
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Lothar
full_name: Thiele, Lothar
last_name: Thiele
citation:
ama: 'Plessl C, Enzler R, Walder H, Beutel J, Platzner M, Thiele L. Reconfigurable
Hardware in Wearable Computing Nodes. In: Proc. Int. Symp. on Wearable Computers
(ISWC). IEEE Computer Society; 2002:215-222. doi:10.1109/ISWC.2002.1167250'
apa: Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., & Thiele,
L. (2002). Reconfigurable Hardware in Wearable Computing Nodes. In Proc. Int.
Symp. on Wearable Computers (ISWC) (pp. 215–222). IEEE Computer Society. https://doi.org/10.1109/ISWC.2002.1167250
bibtex: '@inproceedings{Plessl_Enzler_Walder_Beutel_Platzner_Thiele_2002, title={Reconfigurable
Hardware in Wearable Computing Nodes}, DOI={10.1109/ISWC.2002.1167250},
booktitle={Proc. Int. Symp. on Wearable Computers (ISWC)}, publisher={IEEE Computer
Society}, author={Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel,
Jan and Platzner, Marco and Thiele, Lothar}, year={2002}, pages={215–222} }'
chicago: Plessl, Christian, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner,
and Lothar Thiele. “Reconfigurable Hardware in Wearable Computing Nodes.” In Proc.
Int. Symp. on Wearable Computers (ISWC), 215–22. IEEE Computer Society, 2002.
https://doi.org/10.1109/ISWC.2002.1167250.
ieee: C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, and L. Thiele, “Reconfigurable
Hardware in Wearable Computing Nodes,” in Proc. Int. Symp. on Wearable Computers
(ISWC), 2002, pp. 215–222.
mla: Plessl, Christian, et al. “Reconfigurable Hardware in Wearable Computing Nodes.”
Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002,
pp. 215–22, doi:10.1109/ISWC.2002.1167250.
short: 'C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, in:
Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp.
215–222.'
date_created: 2018-04-17T15:13:50Z
date_updated: 2022-01-06T06:56:13Z
department:
- _id: '518'
- _id: '78'
doi: 10.1109/ISWC.2002.1167250
keyword:
- wearable computing
page: 215-222
publication: Proc. Int. Symp. on Wearable Computers (ISWC)
publication_identifier:
isbn:
- 0-7695-1816-8
publisher: IEEE Computer Society
status: public
title: Reconfigurable Hardware in Wearable Computing Nodes
type: conference
user_id: '24135'
year: '2002'
...
---
_id: '2424'
abstract:
- lang: eng
text: ' Recent generations of high-density and high-speed FPGAs provide a sufficient
capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid
CPUs that combine standard CPU cores with reconfigurable coprocessors are an important
subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded
on demand while the CPU remains running. However, the lack of high-level design
tools for partial reconfiguration makes practical implementations a challenging
task. In this paper, we introduce a design flow to implement hybrid processors
on Xilinx Virtex. The design flow is based on two techniques, virtual sockets
and feed-through components, and can efficiently generate partial configurations
from industry-quality cores. We discuss the design flow and present a fully operational
audio streaming prototype to demonstrate its feasibility. '
author:
- first_name: Matthias
full_name: Dyer, Matthias
last_name: Dyer
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Dyer M, Plessl C, Platzner M. Partially Reconfigurable Cores for Xilinx Virtex.
In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL).
Vol 2438. Lecture Notes in Computer Science (LNCS). Springer; 2002:292-301. doi:10.1007/3-540-46117-5'
apa: Dyer, M., Plessl, C., & Platzner, M. (2002). Partially Reconfigurable Cores
for Xilinx Virtex. In Proc. Int. Conf. on Field Programmable Logic and Applications
(FPL) (Vol. 2438, pp. 292–301). Springer. https://doi.org/10.1007/3-540-46117-5
bibtex: '@inproceedings{Dyer_Plessl_Platzner_2002, series={Lecture Notes in Computer
Science (LNCS)}, title={Partially Reconfigurable Cores for Xilinx Virtex}, volume={2438},
DOI={10.1007/3-540-46117-5},
booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)},
publisher={Springer}, author={Dyer, Matthias and Plessl, Christian and Platzner,
Marco}, year={2002}, pages={292–301}, collection={Lecture Notes in Computer Science
(LNCS)} }'
chicago: Dyer, Matthias, Christian Plessl, and Marco Platzner. “Partially Reconfigurable
Cores for Xilinx Virtex.” In Proc. Int. Conf. on Field Programmable Logic and
Applications (FPL), 2438:292–301. Lecture Notes in Computer Science (LNCS).
Springer, 2002. https://doi.org/10.1007/3-540-46117-5.
ieee: M. Dyer, C. Plessl, and M. Platzner, “Partially Reconfigurable Cores for Xilinx
Virtex,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL),
2002, vol. 2438, pp. 292–301.
mla: Dyer, Matthias, et al. “Partially Reconfigurable Cores for Xilinx Virtex.”
Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), vol.
2438, Springer, 2002, pp. 292–301, doi:10.1007/3-540-46117-5.
short: 'M. Dyer, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable
Logic and Applications (FPL), Springer, 2002, pp. 292–301.'
date_created: 2018-04-17T15:14:39Z
date_updated: 2022-01-06T06:56:13Z
department:
- _id: '518'
- _id: '78'
doi: 10.1007/3-540-46117-5
intvolume: ' 2438'
keyword:
- partial reconfiguration
page: 292-301
publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)
publisher: Springer
series_title: Lecture Notes in Computer Science (LNCS)
status: public
title: Partially Reconfigurable Cores for Xilinx Virtex
type: conference
user_id: '24135'
volume: 2438
year: '2002'
...
---
_id: '2425'
abstract:
- lang: eng
text: ' We present instance-specific custom computing machines for the set covering
problem. Four accelerator architectures are developed that implement branch \&
bound in 3-valued logic and many of the deduction techniques found in software
solvers. We use set covering benchmarks from two-level logic minimization and
Steiner triple systems to derive and discuss experimental results. The resulting
raw speedups are in the order of four magnitudes on average. Finally, we propose
a hybrid solver architecture that combines the raw speed of instance-specific
reconfigurable hardware with flexible bounding schemes implemented in software. '
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Plessl C, Platzner M. Custom Computing Machines for the Set Covering Problem.
In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM).
IEEE Computer Society; 2002:163-172. doi:10.1109/FPGA.2002.1106671'
apa: Plessl, C., & Platzner, M. (2002). Custom Computing Machines for the Set
Covering Problem. In Proc. Int. Symp. on Field-Programmable Custom Computing
Machines (FCCM) (pp. 163–172). IEEE Computer Society. https://doi.org/10.1109/FPGA.2002.1106671
bibtex: '@inproceedings{Plessl_Platzner_2002, title={Custom Computing Machines for
the Set Covering Problem}, DOI={10.1109/FPGA.2002.1106671},
booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)},
publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco},
year={2002}, pages={163–172} }'
chicago: Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the
Set Covering Problem.” In Proc. Int. Symp. on Field-Programmable Custom Computing
Machines (FCCM), 163–72. IEEE Computer Society, 2002. https://doi.org/10.1109/FPGA.2002.1106671.
ieee: C. Plessl and M. Platzner, “Custom Computing Machines for the Set Covering
Problem,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines
(FCCM), 2002, pp. 163–172.
mla: Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set
Covering Problem.” Proc. Int. Symp. on Field-Programmable Custom Computing
Machines (FCCM), IEEE Computer Society, 2002, pp. 163–72, doi:10.1109/FPGA.2002.1106671.
short: 'C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom
Computing Machines (FCCM), IEEE Computer Society, 2002, pp. 163–172.'
date_created: 2018-04-17T15:15:44Z
date_updated: 2022-01-06T06:56:13Z
department:
- _id: '518'
- _id: '78'
doi: 10.1109/FPGA.2002.1106671
page: 163-172
publication: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)
publisher: IEEE Computer Society
status: public
title: Custom Computing Machines for the Set Covering Problem
type: conference
user_id: '24135'
year: '2002'
...
---
_id: '2428'
abstract:
- lang: eng
text: ' In this paper we present instance-specific accelerators for minimum-cost
covering problems. We first define the covering problem and discuss a branch&bound
algorithm to solve it. Then we describe an instance-specific hardware architecture
that implements branch&bound in 3-valued logic and uses reduction techniques usually
found in software solvers. Results for small unate covering problems reveal significant
raw speedups. '
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering.
In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA). CSREA Press; 2001:85-91.'
apa: Plessl, C., & Platzner, M. (2001). Instance-Specific Accelerators for Minimum
Covering. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and
Algorithms (ERSA) (pp. 85–91). CSREA Press.
bibtex: '@inproceedings{Plessl_Platzner_2001, title={Instance-Specific Accelerators
for Minimum Covering}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian
and Platzner, Marco}, year={2001}, pages={85–91} }'
chicago: Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators
for Minimum Covering.” In Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), 85–91. CSREA Press, 2001.
ieee: C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,”
in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA), 2001, pp. 85–91.
mla: Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for
Minimum Covering.” Proc. Int. Conf. on Engineering of Reconfigurable Systems
and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91.
short: 'C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91.'
date_created: 2018-04-17T15:39:17Z
date_updated: 2022-01-06T06:56:17Z
department:
- _id: '518'
- _id: '78'
keyword:
- minimum covering
- accelerator
- funding-sundance
page: 85-91
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publisher: CSREA Press
status: public
title: Instance-Specific Accelerators for Minimum Covering
type: conference
user_id: '24135'
year: '2001'
...
---
_id: '2429'
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Erik
full_name: Wilde, Erik
last_name: Wilde
citation:
ama: Plessl C, Wilde E. Server-Side-Techniken im Web – ein Überblick. iX.
2001:88-93.
apa: Plessl, C., & Wilde, E. (2001). Server-Side-Techniken im Web – ein Überblick.
IX, 88–93.
bibtex: '@article{Plessl_Wilde_2001, title={Server-Side-Techniken im Web – ein Überblick},
journal={iX}, publisher={Heise Verlag}, author={Plessl, Christian and Wilde, Erik},
year={2001}, pages={88–93} }'
chicago: Plessl, Christian, and Erik Wilde. “Server-Side-Techniken Im Web – Ein
Überblick.” IX, 2001, 88–93.
ieee: C. Plessl and E. Wilde, “Server-Side-Techniken im Web – ein Überblick,” iX,
pp. 88–93, 2001.
mla: Plessl, Christian, and Erik Wilde. “Server-Side-Techniken Im Web – Ein Überblick.”
IX, Heise Verlag, 2001, pp. 88–93.
short: C. Plessl, E. Wilde, IX (2001) 88–93.
date_created: 2018-04-17T15:43:29Z
date_updated: 2022-01-06T06:56:17Z
department:
- _id: '518'
page: 88-93
publication: iX
publisher: Heise Verlag
status: public
title: Server-Side-Techniken im Web – ein Überblick
type: journal_article
user_id: '24135'
year: '2001'
...
---
_id: '2430'
abstract:
- lang: eng
text: In this report the design and implementation of an instance-specific accelerator
for solving minimum covering problems will be presented. After an introduction
to configurable computing in general, the minimum covering problem is defined
and a branch and bound algorithm to solve it in software is presented. The remainder
of the report shows how this branch and bound algorithm can be adopted to hardware.
Specifically it is stressed how the various sophisticated strategies for deducing
conditions for variables used by software solvers can be adopted to hardware and
how a system which uses 3-valued logic to solve this problem can be designed.
In addition to these considerations focusing on the architecture of the system,
some important details of the actual implementation are given. A prototype has
been implemented for showing the feasibility of the concept and for gaining information
about speed and size of the hardware implementation. Cycle-accurate simulations
for a set of benchmark problems have been done for determining the performance
of the accelerator. The speed of the resulting accelerators has been compared
to the time a reference software solver (espresso) needs and the resulting speedups
have been calculated. I have shown that a raw speedup of several orders of maginitude
can be achieved for many problems; for some problems no speedup is achieved yet.
After a discussion of the results, ideas for future work are presented.
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Plessl C. Reconfigurable Accelerators for Minimum Covering. Computer
Engineering and Networks Lab, ETH Zurich, Switzerland; 2001.
apa: Plessl, C. (2001). Reconfigurable Accelerators for Minimum Covering.
Computer Engineering and Networks Lab, ETH Zurich, Switzerland.
bibtex: '@book{Plessl_2001, title={Reconfigurable Accelerators for Minimum Covering},
publisher={Computer Engineering and Networks Lab, ETH Zurich, Switzerland}, author={Plessl,
Christian}, year={2001} }'
chicago: Plessl, Christian. Reconfigurable Accelerators for Minimum Covering.
Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2001.
ieee: C. Plessl, Reconfigurable Accelerators for Minimum Covering. Computer
Engineering and Networks Lab, ETH Zurich, Switzerland, 2001.
mla: Plessl, Christian. Reconfigurable Accelerators for Minimum Covering.
Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2001.
short: C. Plessl, Reconfigurable Accelerators for Minimum Covering, Computer Engineering
and Networks Lab, ETH Zurich, Switzerland, 2001.
date_created: 2018-04-17T15:47:26Z
date_updated: 2022-01-06T06:56:17Z
department:
- _id: '518'
publisher: Computer Engineering and Networks Lab, ETH Zurich, Switzerland
status: public
title: Reconfigurable Accelerators for Minimum Covering
type: mastersthesis
user_id: '24135'
year: '2001'
...
---
_id: '2432'
abstract:
- lang: eng
text: In this paper, we present the analysis of applications from the domain of
handheld and wearable computing. This analysis is the first step to derive and
evaluate design parameters for dynamically reconfigurable processors. We discuss
the selection of representative benchmarks for handhelds and wearables and group
the applications into multimedia, communications, and cryptography programs. We
simulate the applications on a cycle-accurate processor simulator and gather statistical
data such as instruction mix, cache hit rates and memory requirements for an embedded
processor model. A breakdown of the executed cycles into different functions identifies
the most compute-intensive code sections - the kernels. Then, we analyze the applications
and discuss parameters that strongly influence the design of dynamically reconfigurable
processors. Finally, we outline the construction of a parameterizable simulation
model for a reconfigurable unit that is attached to a processor core.
author:
- first_name: Rolf
full_name: Enzler, Rolf
last_name: Enzler
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Lothar
full_name: Thiele, Lothar
last_name: Thiele
- first_name: Gerhard
full_name: Tröster, Gerhard
last_name: Tröster
citation:
ama: 'Enzler R, Platzner M, Plessl C, Thiele L, Tröster G. Reconfigurable Processors
for Handhelds and Wearables: Application Analysis. In: Reconfigurable Technology:
FPGAs and Reconfigurable Processors for Computing and Communications III.
Vol 4525. Proc. SPIE. ; 2001:135-146. doi:10.1117/12.434376'
apa: 'Enzler, R., Platzner, M., Plessl, C., Thiele, L., & Tröster, G. (2001).
Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In
Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing
and Communications III (Vol. 4525, pp. 135–146). https://doi.org/10.1117/12.434376'
bibtex: '@inproceedings{Enzler_Platzner_Plessl_Thiele_Tröster_2001, series={Proc.
SPIE}, title={Reconfigurable Processors for Handhelds and Wearables: Application
Analysis}, volume={4525}, DOI={10.1117/12.434376},
booktitle={Reconfigurable Technology: FPGAs and Reconfigurable Processors for
Computing and Communications III}, author={Enzler, Rolf and Platzner, Marco and
Plessl, Christian and Thiele, Lothar and Tröster, Gerhard}, year={2001}, pages={135–146},
collection={Proc. SPIE} }'
chicago: 'Enzler, Rolf, Marco Platzner, Christian Plessl, Lothar Thiele, and Gerhard
Tröster. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.”
In Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing
and Communications III, 4525:135–46. Proc. SPIE, 2001. https://doi.org/10.1117/12.434376.'
ieee: 'R. Enzler, M. Platzner, C. Plessl, L. Thiele, and G. Tröster, “Reconfigurable
Processors for Handhelds and Wearables: Application Analysis,” in Reconfigurable
Technology: FPGAs and Reconfigurable Processors for Computing and Communications
III, 2001, vol. 4525, pp. 135–146.'
mla: 'Enzler, Rolf, et al. “Reconfigurable Processors for Handhelds and Wearables:
Application Analysis.” Reconfigurable Technology: FPGAs and Reconfigurable
Processors for Computing and Communications III, vol. 4525, 2001, pp. 135–46,
doi:10.1117/12.434376.'
short: 'R. Enzler, M. Platzner, C. Plessl, L. Thiele, G. Tröster, in: Reconfigurable
Technology: FPGAs and Reconfigurable Processors for Computing and Communications
III, 2001, pp. 135–146.'
date_created: 2018-04-17T15:51:39Z
date_updated: 2022-01-06T06:56:17Z
department:
- _id: '518'
- _id: '78'
doi: 10.1117/12.434376
intvolume: ' 4525'
keyword:
- benchmark
page: 135-146
publication: 'Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing
and Communications III'
series_title: Proc. SPIE
status: public
title: 'Reconfigurable Processors for Handhelds and Wearables: Application Analysis'
type: conference
user_id: '24135'
volume: 4525
year: '2001'
...
---
_id: '2433'
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Simon
full_name: Maurer, Simon
last_name: Maurer
citation:
ama: Plessl C, Maurer S. Hardware/Software Codesign in Speech Compression Applications.
Computer Engineering and Networks Lab, ETH Zurich, Switzerland; 2000.
apa: Plessl, C., & Maurer, S. (2000). Hardware/Software Codesign in Speech
Compression Applications. Computer Engineering and Networks Lab, ETH Zurich,
Switzerland.
bibtex: '@book{Plessl_Maurer_2000, title={Hardware/Software Codesign in Speech Compression
Applications}, publisher={Computer Engineering and Networks Lab, ETH Zurich, Switzerland},
author={Plessl, Christian and Maurer, Simon}, year={2000} }'
chicago: Plessl, Christian, and Simon Maurer. Hardware/Software Codesign in Speech
Compression Applications. Computer Engineering and Networks Lab, ETH Zurich,
Switzerland, 2000.
ieee: C. Plessl and S. Maurer, Hardware/Software Codesign in Speech Compression
Applications. Computer Engineering and Networks Lab, ETH Zurich, Switzerland,
2000.
mla: Plessl, Christian, and Simon Maurer. Hardware/Software Codesign in Speech
Compression Applications. Computer Engineering and Networks Lab, ETH Zurich,
Switzerland, 2000.
short: C. Plessl, S. Maurer, Hardware/Software Codesign in Speech Compression Applications,
Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2000.
date_created: 2018-04-17T15:56:00Z
date_updated: 2022-01-06T06:56:17Z
department:
- _id: '518'
keyword:
- co-design
- speech processing
publisher: Computer Engineering and Networks Lab, ETH Zurich, Switzerland
status: public
title: Hardware/Software Codesign in Speech Compression Applications
type: mastersthesis
user_id: '24135'
year: '2000'
...