@inproceedings{24060, abstract = {{In diesem Artikel stellen wir eine Methode zur nicht-invasiven dynamischen Speicher- und IO-Analyse mit QEMU für sicherheitskritische eingebettete Software für die RISC-V Befehlssatzarchitektur vor. Die Implementierung basiert auf einer Erweiterung des Tiny Code Generator (TCG) des quelloffenen CPU-Emulators QEMU um die dynamische Identifikation von Zugriffen auf Datenspeicher sowie auf an die CPU angeschlossene IO-Geräte. Wir demonstrieren die Funktionalität der Methode anhand eines Versuchsaufbaus, bei dem eine Schließsystemkontrolle mittels serieller UART-Schnittstelle an einen RISC-V-Prozessor angebunden ist. Dieses Szenario zeigt, dass ein unberechtigter Zugriff auf die UART-Schnittstelle frühzeitig aufgedeckt und ein Angriff auf eine Zugangskontrolle somit endeckt werden kann. }}, author = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}}, booktitle = {{MBMV 2019-22.Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2019)}}, isbn = {{978-3-8007-4945-4}}, title = {{{Analyse sicherheitskritischer Software für RISC-V Prozessoren}}}, year = {{2019}}, } @inproceedings{24061, author = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph and Driessen, Benedikt}}, booktitle = {{ 2nd International Workshop on Embedded Software for Industrial IoT in conjunction with DATE 2019}}, pages = {{32--34}}, title = {{{QEMU for Dynamic Memory Analysis of Security Sensitive Software}}}, year = {{2019}}, } @article{24063, abstract = {{It its current Version 3.1.0 QEMU supports RISC-V RV32GC and RV64GC software emulation in user and full system mode. We will first give an overview of the current state of the QEMU RISC-V implementation. Thereafter, we will present the DecodeTree tool, which will be available with the next QEMU release. DecodeTree is a code generator included in QEMU that can generate the program logic for extracting and decoding opcodes and operands from a formal instruction list of the target architecture. This enables the structured implementation of just-in-time compilations to guarantee that the QEMU implementation meets the ISA specification. As such, we completely replaced the existing RISC-V RV32GC and RV64GC implementations by DecodeTree generations in the next official QEMU release, which is expected in spring 2019. We will demonstrate the DecodeTree applications by the example of RISC-V ISA subset configurations.}}, author = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}}, journal = {{2nd International Workshop on RISC-V Research Activities}}, title = {{{QEMU Support for RISC-V: Current State and Future Releases}}}, volume = {{(Presentation)}}, year = {{2019}}, } @book{53596, editor = {{Bringmann, Oliver and Ecker, Wolfgang and Müller, Wolfgang and Müller-Gridschneder, Daniel}}, title = {{{Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT}}}, year = {{2019}}, } @article{24194, author = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang}}, journal = {{International Workshop on RISC-V Research Activities}}, location = {{Munich, DE}}, title = {{{Current and Future RISC-V Activities for Virtual Prototyping and Chip Design}}}, volume = {{Presentation}}, year = {{2018}}, } @inproceedings{24196, abstract = {{This paper presents an approach for analog fault effect simulation automation based on random fault selection with a high fault coverage of the circuit under test by means of fault injection and simulation based on advanced sampling techniques. The random fault selection utilizes the likelihood of the fault occurrence of different electrical components in the circuit with a confidence level. Defect models of different devices are analyzed for the calculation of the fault probability. A case study with our implemented tool demonstrates that likelihood calculation and fault simulation provides means for efficient fault effect simulation automation.}}, author = {{Wu, Liang and Hussain, Mohammad Khizer and Abughannam, Saed and Müller, Wolfgang and Scheytt, Christoph and Ecker, Wolfgang}}, booktitle = {{2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)) }}, publisher = {{IEEE}}, title = {{{Analog fault simulation automation at schematic level with random sampling techniques}}}, doi = {{10.1109/DTIS.2018.8368549}}, year = {{2018}}, } @book{53595, editor = {{Bringmann, Oliver and Ecker, Wolfgang and Müller, Wolfgang and Müller-Gridschneder, Daniel}}, title = {{{Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT}}}, year = {{2018}}, } @inproceedings{24220, author = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Mueller-Gritschneder, Daniel and Kleinjohann, Bernd and Scheytt, Christoph}}, booktitle = {{Tagungsband des Wissenschaftsforums Intelligente Technische Systeme}}, isbn = {{978-3-942647-88-5}}, publisher = {{Verlagsschriftenreihe des Heinz Nixdorf Instituts}}, title = {{{Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen}}}, doi = {{10.17619/UNIPB/1-93}}, year = {{2017}}, } @inproceedings{24223, abstract = {{This paper presents the design flow of using sampling technique for fault injection on sche- matic level. The parameters used in the docu- ment to calculate the likelihood could be modi- fied by using more realistic data from the fab. With the help of the fault simulator, the whole design flow of the fault effect simulation can be realized automatically.}}, author = {{Wu, Liang and Abughannam, Saed and Müller, Wolfgang and Scheytt, Christoph and Ecker, Wolfgang}}, booktitle = {{2nd Workshop on Resiliency in Embedded Electronic Systems (REES)}}, pages = {{68}}, title = {{{SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study}}}, year = {{2017}}, } @inproceedings{24224, author = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Kleinjohann, Bernd and Scheytt, Christoph}}, booktitle = {{Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation}}, title = {{{ANALISA - A Tool for Static Instruction Set Analysis}}}, year = {{2017}}, } @inproceedings{24225, author = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Kleinjohann, Bernd and Scheytt, Christoph}}, booktitle = {{2nd Workshop on Resiliency in Embedded Electronic Systems (REES) }}, pages = {{44}}, title = {{{An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries}}}, year = {{2017}}, } @inproceedings{25069, author = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Kleinjohann, Bernd and Scheytt, J. Christoph}}, booktitle = {{Design Automation and Testing in Europe (DATE)}}, location = {{Lausanne, CH, Mrz. 2017}}, title = {{{ANALISA - A Tool for Static Instruction Set Analysis}}}, year = {{2017}}, } @inproceedings{24264, abstract = {{Electronic systems, like they are embedded in road vehicles, have to be compliant to functional safety standards like ISO 26262 [1], which limit the impacts of malfunctions for safety critical systems. ISO 26262, for instance, defines different safety levels for road vehicles, which require different means and measures for a safety compliant system and its development process like risk analysis and fault effect simulation. For fault effect simulation it is important to investigate the impact of physical and hardware related effects to the correct function of a system. This article first studies code and model mutations for fault injection in the context of fault effect simulation through different system abstraction levels. It demonstrates how high level mutations correlate to bit flips of software binaries by examples from the TriCore™ instruction set and finally presents a virtual platform based implementation for automated injection of bit flip based mutations into software binaries. Experimental results demonstrate the efficiency of the implemented approach.}}, author = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Becker, Markus and Kleinjohann, Bernd and Scheytt, Christoph}}, booktitle = {{Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC)}}, issn = {{2324-8440}}, title = {{{Fast Dynamic Fault Injection for Virtual Microcontroller Platforms}}}, doi = {{10.1109/VLSI-SoC.2016.7753545}}, year = {{2016}}, } @inproceedings{24263, abstract = {{The design of safety critical systems requires an efficient methodology for an effective fault effect simulation for analog and digital circuits where analog fault injection and fault effect simulation is currently a field of active research and commercial tools are not available yet. This article begins by discussing fault injection strategies for analog circuits applied on a case study with two topologies of a Voltage Controlled Oscillator (VCO). In the second part it performs on the basis of the example of a Wireless Sensor Network (WSN) node, how far different mixed level implementations with Verilog-A and SPICE can affect the simulation time and points out which component consumes the major part of the simulation time.}}, author = {{Abughannam, Saed and Wu, Liang and Müller, Wolfgang and Scheytt, Christoph and Ecker, Wolfgang and Novello, Christiano}}, booktitle = {{Analog 2016 - VDE}}, isbn = {{978-3-8007-4265-3}}, title = {{{Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study}}}, year = {{2016}}, } @inproceedings{24289, author = {{Müller, Wolfgang and Wu, Liang and Scheytt, Christoph and Becker, Markus and Schoenberg, Sven}}, booktitle = {{Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014)}}, editor = {{Mueller-Gritschneder, Daniel and Müller, Wolfgang and Mitra, Subhasish}}, title = {{{On the Correlation of HW Faults and SW Errors}}}, year = {{2015}}, } @book{53590, editor = {{Müller-Gridschneder, Daniel and Müller, Wolfgang and Mitra, Subhasish}}, title = {{{Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems}}}, year = {{2015}}, } @inproceedings{25145, author = {{Becker, Markus and Kuznik, Christoph and Müller, Wolfgang}}, booktitle = {{17th Euromicro Conference on Digital Systems Design (DSD)}}, title = {{{Virtual Platforms for Model-Based Design of Dependable Cyber-Physical System Software}}}, year = {{2014}}, } @inproceedings{25155, author = {{Becker, Markus and Kuznik, Christoph and Müller, Wolfgang}}, booktitle = {{ACM/IEEE 5th International Conference on Cyber-Physical Systems}}, title = {{{Fault Effect Modeling in a Heterogeneous SystemC Virtual Platform Framework for Cyber-Physical Systems}}}, year = {{2014}}, } @inproceedings{25161, author = {{Koppelmann, Bastian and Becker, Markus and Müller, Wolfgang}}, booktitle = {{17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) }}, title = {{{Portierung der TriCore-Architektur auf QEMU}}}, year = {{2014}}, } @inproceedings{24305, abstract = {{Energy efficiency drives the development of more and more complex low-power designs. Based on dynamic power management techniques, multiple voltage islands as well as a huge amount of power states are specified that have to be tested carefully. In this context, low-power design should start at an early stage using state-of-the-art system-level modeling and simulation techniques. However, there is neither a programming language nor any modeling standard that reflects variable power together with its functional side effects in a well-suited abstract manner. To overcome this limitation, we present a modeling approach on top of SystemC TLM to capture low-power design characteristics at electronic system-level. We demonstrate the usability by means of an existing open-source low-power design. The experimental results show that appropriate TLM instrumentation cause only minimal simulation overhead, but offer sufficient details to identify common low-power design errors.}}, author = {{Mischkalla, Fabian and Müller, Wolfgang}}, booktitle = {{Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)}}, publisher = {{IEEE}}, title = {{{Architectural Low-Power Design Using Transaction-Based System Modeling and Simulation}}}, doi = {{10.1109/SAMOS.2014.6893219}}, year = {{2014}}, }