@inproceedings{24311,
  abstract     = {{Intelligent automotive electronics significantly improved driving safety in the last decades. With the increasing complexity of automotive systems, dependability of the electronic components themselves and of their interaction must be assured to avoid any risk to driving safety due to unexpected failures caused by internal or external faults. Additionally, Virtual Prototypes (VPs) have been accepted in many areas of system development processes in the automotive industry as platforms for SW development, verification, and design space exploration. We believe that VPs will significantly contribute to the analysis of safety conditions for automotive electronics. This paper shows the advantages of such a methodology based on today's industrial needs, presents the current state of the art in this field, and outlines upcoming research challenges that need to be addressed to make this vision a reality.}},
  author       = {{Oetjens, Jan-Hendrik and Becker, Markus and Kuznik, Christoph and Müller, Wolfgang and Bannow, Nico and Brinkmann, Oliver and Burger, Andreas and Chaari, Moomen and Chakraborty, Samarjit and Drechsler, R. and Ecker, Wolfgang and Grüttner, Kim and Kruse, Thomas and Le, Hoang M and Mauderer, M. and Mueller-Gritschneider, Daniel and Poppen, Frank and Post, Hendrik and Reiter, SEbastian and Rosenstiel, Wolfgang and Roth, S.  and Schlichtmann, Ulf and Von Schwerin, Andreas and Tabacaru, Bogdan Andrei and Viehl, Alexander}},
  booktitle    = {{Design Automation Conference (DAC)}},
  title        = {{{Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges}}},
  doi          = {{10.1145/2593069.2602976}},
  year         = {{2014}},
}

@article{25164,
  author       = {{Becker, Markus and Müller, Wolfgang and Stroop, Joachim and Kiffmeier, Ulrich}},
  journal      = {{Design, Automation and Test in Europe DATE, University Booth, Dresden}},
  title        = {{{HeroeS - A Framework for Heterogeneous Software-Intensive System Design with SystemC}}},
  year         = {{2014}},
}

@inproceedings{25120,
  author       = {{Mischkalla, Fabian and Müller, Wolfgang}},
  booktitle    = {{Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)}},
  location     = {{Greece, Sep. 2014, IEEE}},
  publisher    = {{IEEE}},
  title        = {{{Architectural Low-Power Design Using Transaction-Based System Simulation}}},
  year         = {{2014}},
}

@inproceedings{25146,
  author       = {{Joy, M. tech. Mabel Mary and Müller, Wolfgang and Rammig, Franz-Josef}},
  booktitle    = {{12th IEEE International conference on Embedded Computing}},
  title        = {{{Source code annotated memory leak detection for soft real time embedded systems with resource constraints}}},
  year         = {{2014}},
}

@inproceedings{25144,
  author       = {{Mischkalla, Fabian and Müller, Wolfgang}},
  booktitle    = {{PATMOS 2014}},
  title        = {{{Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation}}},
  year         = {{2014}},
}

@inproceedings{36918,
  abstract     = {{This paper presents an advanced eight levels spanning SystemC based virtual platform methodology and framework - referred to as HeroeS 3 - providing smooth application to platform mapping and continuous co-refinement of a virtual prototype with its physical environment model. For heterogeneity support, various SystemC extensions are combined covering continuous/discrete models of computation and different communication abstractions, such as analog mixed-signal models, abstract RTOS/HAL/middleware models, TLM bus models, and QEMU wrappers. We enable dependability assessment by Fault Effect Modeling (FEM) at the virtual prototype in order to avoid risking physical injury or damage. Also, simulation results are deterministic and can be evaluated interactively or offline. We apply FEM to both the physical environment model and the different abstractions of the virtual prototype. Currently, we focus on sensor failures and application control flow errors.}},
  author       = {{Becker, Markus and Kuznik, Christoph and Müller, Wolfgang}},
  keywords     = {{Computational modeling, Finite element analysis, Prototypes, Abstracts, Software, Fault tolerance, Fault tolerant systems}},
  location     = {{Berlin}},
  publisher    = {{IEEE}},
  title        = {{{Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems}}},
  doi          = {{10.1109/ICCPS.2014.6843726}},
  year         = {{2014}},
}

@inproceedings{36917,
  abstract     = {{The ever-increasing complexity of heterogeneous electronic systems demand for intensified abstraction and automation efforts to improve design, verification and validation productivity, especially in earlier phases of system engineering. Within the verification activity various metrics can be applied to determine functional correctness or the overall progress. Here, a supporting verification methodology defining high-level verification planning down to the actual metric code development is essential. Moreover, an advanced assistance for the designer, such as a tooling infrastructure to automatize and accelerate the metric code implementation, is needed to minimize the influence of errorprone manual coding. In this article we present a single-source verification metric code-generation methodology for improved coverage automation. We determine (i) a suitable metric model for model-based capture of verification metrics as well as (ii) an assisted model-based processing and generation flow of the verification environment and metric skeletons. We apply our method to a SystemC case-study, in doing so, targeting metric code implementation productivity and consistency enhancement.}},
  author       = {{Kuznik, Christoph and Müller, Wolfgang and Defo, Gilles Bertrand}},
  keywords     = {{System Design, Verification}},
  title        = {{{An Assisted Single Source Verification Metric Model Code Generation Methodology}}},
  year         = {{2014}},
}

@inproceedings{25166,
  abstract     = {{Zur Sicherstellung hoher Zuverlässigkeits- und Fehlertoleranzwerte von Schaltungen und ganzen Systemen finden vermehrt Test- und Verifikationsmethoden Anwendung die einen virtuellen Prototypen (VP) des Systems bereits frühzeitig im Entwurfsablauf einem Stresstest unterziehen. Hierbei werden speziell für die Domäne relevante Fehlerinjektoren verwendet (Digital, Mixed-Signal, Mechanik) die anhand von Fehlermodellen geeignete Testfälle erzeugen und in das System über Stimuli bzw. direkt injizieren. Jede effektive Anwendung einer Methode bedingt jedoch auch das Vorhandensein einer zugrundeliegenden Methodik. In diesem Beitrag wird die System Verification Methodology (SVM) vorgestellt werden, eine universell einsetzbare und erweiterbare Infrastruktur zur Beschreibung von Testumgebungen auf Basis der SystemC Sprache und Simulationskernels.}},
  author       = {{Kuznik, Christoph and Müller, Wolfgang}},
  booktitle    = {{26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen}},
  title        = {{{Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM}}},
  year         = {{2014}},
}

@inproceedings{25163,
  author       = {{Kuznik, Christoph and Defo, Bertrand Gilles and Müller, Wolfgang}},
  booktitle    = {{17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) }},
  title        = {{{Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung}}},
  year         = {{2014}},
}

@article{25151,
  author       = {{Kuznik, Christoph and Defo, Bertrand Gilles and Müller, Wolfgang}},
  journal      = {{Electronic System Level Synthesis Conference (ESLSyn)}},
  title        = {{{An Assisted Single Source Verification Metric Model Code Generation Methodology}}},
  year         = {{2014}},
}

@inproceedings{34585,
  abstract     = {{In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation.}},
  author       = {{Koppelmann, Bastian and Messidat, Bernd and Becker, Markus and Müller, Wolfgang and Scheytt, J. Christoph}},
  booktitle    = {{Proceedings of the Design and Verification Conference Europe (DVCON Europe)}},
  keywords     = {{System Design, Verification}},
  title        = {{{Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}}},
  year         = {{2014}},
}

@inproceedings{34583,
  abstract     = {{In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation.}},
  author       = {{Koppelmann, Bastian and Messidat, Bernd and Kuznik, Christoph and Müller, Wolfgang and Becker, Markus and Scheytt, J. Christoph}},
  booktitle    = {{Proceedings of the Design and Verification Conference Europe (DVCON Europe)}},
  keywords     = {{System Design, Verification}},
  title        = {{{Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}}},
  year         = {{2014}},
}

@inproceedings{34580,
  abstract     = {{In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation.}},
  author       = {{Becker, Markus and Kuznik, Christoph and Müller, Wolfgang and Koppelmann, Bastian and Messidat, Bernd}},
  booktitle    = {{Proceedings of the Design and Verification Conference Europe }},
  title        = {{{Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}}},
  year         = {{2014}},
}

@article{25117,
  author       = {{Koppelmann, Bastian and Messidat, Bernd and Becker, Markus and Kuznik, Christoph and Müller, Wolfgang and Scheytt, J. Christoph}},
  journal      = {{Design and Verification Conference (DVCON EUROPE)}},
  title        = {{{Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}}},
  year         = {{2014}},
}

@article{25162,
  author       = {{Kuznik, Christoph and Müller, Wolfgang}},
  journal      = {{Design, Automation and Test in Europe DATE, University Booth, Dresden }},
  title        = {{{Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure}}},
  year         = {{2014}},
}

@inproceedings{25169,
  author       = {{Oetjens, Jan-Hendrik and Becker, Markus and Kuznik, Christoph and Müller, Wolfgang}},
  booktitle    = {{Design Automation Conference (DAC)}},
  title        = {{{Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges}}},
  year         = {{2014}},
}

@inproceedings{25270,
  author       = {{Joy, M. tech. Mabel Mary and Müller, Wolfgang and Rammig, Franz-Josef}},
  booktitle    = {{Proceedings of AVICPS 2013, Dez. 2013 IEEE Computer Society,}},
  publisher    = {{Linköping University Electronic Press}},
  title        = {{{Early Phase Memory Leak Detection in Embedded Software Designs with Virtual Memory Management Model}}},
  year         = {{2013}},
}

@inproceedings{25271,
  author       = {{He, Da and Müller, Wolfgang}},
  booktitle    = {{Proceedings of International Conference on Applied Computing (AC)}},
  title        = {{{AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL- TIME SYSTEM ON MULTI-CORE PROCESSORS}}},
  year         = {{2013}},
}

@inproceedings{25284,
  author       = {{Mischkalla, Fabian and Müller, Wolfgang}},
  booktitle    = {{ 23rd International Workshop on Power And Timing Modeling, Optimization and Simulation, Sep. 2013}},
  title        = {{{ Efficient Power Intent Validation Using Loosely-Timed Simulation Models}}},
  year         = {{2013}},
}

@inproceedings{25291,
  author       = {{Becker, Markus and Kiffmeier, Ulrich and Müller, Wolfgang}},
  booktitle    = {{16th IEEE Computer Society Symposium on Object/Component/Service-oriented Real-time Distributed Computing}},
  title        = {{{HeroeS: Virtual Platform Driven Integration of Heterogeneous Software Components for Multi-Core Real-Time Architectures}}},
  year         = {{2013}},
}