@inproceedings{34585,
  abstract     = {{In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation.}},
  author       = {{Koppelmann, Bastian and Messidat, Bernd and Becker, Markus and Müller, Wolfgang and Scheytt, J. Christoph}},
  booktitle    = {{Proceedings of the Design and Verification Conference Europe (DVCON Europe)}},
  keywords     = {{System Design, Verification}},
  title        = {{{Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}}},
  year         = {{2014}},
}

@inproceedings{34583,
  abstract     = {{In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation.}},
  author       = {{Koppelmann, Bastian and Messidat, Bernd and Kuznik, Christoph and Müller, Wolfgang and Becker, Markus and Scheytt, J. Christoph}},
  booktitle    = {{Proceedings of the Design and Verification Conference Europe (DVCON Europe)}},
  keywords     = {{System Design, Verification}},
  title        = {{{Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}}},
  year         = {{2014}},
}

@inproceedings{34580,
  abstract     = {{In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation.}},
  author       = {{Becker, Markus and Kuznik, Christoph and Müller, Wolfgang and Koppelmann, Bastian and Messidat, Bernd}},
  booktitle    = {{Proceedings of the Design and Verification Conference Europe }},
  title        = {{{Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}}},
  year         = {{2014}},
}

@article{25117,
  author       = {{Koppelmann, Bastian and Messidat, Bernd and Becker, Markus and Kuznik, Christoph and Müller, Wolfgang and Scheytt, J. Christoph}},
  journal      = {{Design and Verification Conference (DVCON EUROPE)}},
  title        = {{{Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}}},
  year         = {{2014}},
}

@article{25162,
  author       = {{Kuznik, Christoph and Müller, Wolfgang}},
  journal      = {{Design, Automation and Test in Europe DATE, University Booth, Dresden }},
  title        = {{{Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure}}},
  year         = {{2014}},
}

@inproceedings{25169,
  author       = {{Oetjens, Jan-Hendrik and Becker, Markus and Kuznik, Christoph and Müller, Wolfgang}},
  booktitle    = {{Design Automation Conference (DAC)}},
  title        = {{{Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges}}},
  year         = {{2014}},
}

@inproceedings{25270,
  author       = {{Joy, M. tech. Mabel Mary and Müller, Wolfgang and Rammig, Franz-Josef}},
  booktitle    = {{Proceedings of AVICPS 2013, Dez. 2013 IEEE Computer Society,}},
  publisher    = {{Linköping University Electronic Press}},
  title        = {{{Early Phase Memory Leak Detection in Embedded Software Designs with Virtual Memory Management Model}}},
  year         = {{2013}},
}

@inproceedings{25271,
  author       = {{He, Da and Müller, Wolfgang}},
  booktitle    = {{Proceedings of International Conference on Applied Computing (AC)}},
  title        = {{{AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL- TIME SYSTEM ON MULTI-CORE PROCESSORS}}},
  year         = {{2013}},
}

@inproceedings{25284,
  author       = {{Mischkalla, Fabian and Müller, Wolfgang}},
  booktitle    = {{ 23rd International Workshop on Power And Timing Modeling, Optimization and Simulation, Sep. 2013}},
  title        = {{{ Efficient Power Intent Validation Using Loosely-Timed Simulation Models}}},
  year         = {{2013}},
}

@inproceedings{25291,
  author       = {{Becker, Markus and Kiffmeier, Ulrich and Müller, Wolfgang}},
  booktitle    = {{16th IEEE Computer Society Symposium on Object/Component/Service-oriented Real-time Distributed Computing}},
  title        = {{{HeroeS: Virtual Platform Driven Integration of Heterogeneous Software Components for Multi-Core Real-Time Architectures}}},
  year         = {{2013}},
}

@inproceedings{25606,
  author       = {{Kuznik, Christoph and F. S. Oliveira, Marcio and Müller, Wolfgang}},
  booktitle    = {{edaWorkshop 13}},
  location     = {{Mrz. 2013 - Poster}},
  title        = {{{SystemC Verification Components - An enhanced OVM/UVM for SystemC}}},
  year         = {{2013}},
}

@inproceedings{25612,
  author       = {{Mischkalla, Fabian and Müller, Wolfgang}},
  booktitle    = {{Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)}},
  title        = {{{Funktionale Verifikation von Low-Power Designs unter Verwendung Virtueller Prototypen}}},
  year         = {{2013}},
}

@inproceedings{25614,
  author       = {{Kuznik, Christoph and F. S. Oliveira, Marcio and Müller, Wolfgang}},
  booktitle    = {{Open SANITAS SystemC Verification Workshop}},
  title        = {{{SC OVM: An Advanced SystemC Library for OVM-based Verification}}},
  year         = {{2013}},
}

@misc{25615,
  author       = {{Engels, Gregor and Gerth, Christian and Kleinjohann, Lisa and Kleinjohann, Bernd and Müller, Wolfgang}},
  booktitle    = {{ForschungsForum Paderborn }},
  title        = {{{ Informationstechnik spart Ressourcen}}},
  year         = {{2013}},
}

@inproceedings{25620,
  author       = {{Kuznik, Christoph and Oliveira, Marcio F. and Defo, Bertrand and Müller, Wolfgang}},
  booktitle    = {{Proceedings of DVCON}},
  title        = {{{Systematic Application of UCIS to Improve the Automation on Verification Closure}}},
  year         = {{2013}},
}

@inproceedings{25632,
  author       = {{Klobedanz, Kay and Jatzkowski, Jan and Rettberg, Achim and Müller, Wolfgang}},
  booktitle    = {{International Embedded Systems Symposium (IESS) 2013}},
  publisher    = {{Springer}},
  title        = {{{Fault-Tolerant Deployment of Real-Time Software in AUTOSAR ECU Networks}}},
  year         = {{2013}},
}

@article{25740,
  author       = {{He, Da and Müller, Wolfgang}},
  journal      = {{Microprocessors and Microsystems - Embedded Hardware Design 37(6-7)}},
  pages        = {{845--857}},
  title        = {{{ A heuristic energy-aware approach for hard real-time systems on multi-core platforms}}},
  year         = {{2013}},
}

@inbook{25743,
  author       = {{Anacker, Harald and Dellnitz, Michael and Flaßkamp, Kathrin and Grösbrink, Stefan and Hartmann, Philip and Heinzemann, Christian and Horenkamp, Christian and Kleinjohann, Lisa and Kleinjohann, Bernd and Korf, Sebastian and Krüger, Martin and Müller, Wolfgang and Ober-Blöbaum, Sina and Oberthür, Simon and Porrmann, Mario and Priesterjahn, Claudia and Radkowski, W. and Rasche, Christoph and Rieke, Jan and Ringkamp, Maik and Stahl, Katharina and Steenken, Dominik and Stöcklein, Jörg and Timmermann, Robert and Trächtler, Ansgar and Witting, Katrin and Xie, Tao and Ziegert, Steffen}},
  booktitle    = {{Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future}},
  pages        = {{187--356}},
  publisher    = {{Springer-Verlag}},
  title        = {{{Methods for the Design and Development}}},
  year         = {{2013}},
}

@inproceedings{36919,
  abstract     = {{Faced with increasing demands on energy efficiency, current electronic systems operate according to complex power management schemes including more and more fine-grained voltage frequency scaling and power shutdown scenarios. Consequently, validation of the power design intent should begin as early as possible at electronic system-level (ESL) together with first executable system specifications for integrity tests. However, today's system-level design methodologies usually focus on the abstraction of digital logic and time, so that typical low-power aspects cannot be considered so far. In this paper, we present a high-level modeling approach on top of the SystemC/TLM standard to simulate power distribution and voltage based implications in a "loosely-timed" functional execution context. The approach reuses legacy TLM models and prevents the need for detailed lock-step process synchronization in contrast to existing methods. A case study derived from an open source low-power design demonstrates the efficiency of our approach in terms of simulation performance and testability.}},
  author       = {{Mischkalla, Fabian and Müller, Wolfgang}},
  keywords     = {{Time-varying systems, Time-domain analysis, Synchronization, Context modeling, Clocks, Semantics, Standards}},
  publisher    = {{IEEE}},
  title        = {{{Efficient Power-Intent Validation Using "Loosely-Timed" Simulation Models: A Non-Invasive Approach}}},
  doi          = {{10.1109/PATMOS.2013.6662171}},
  year         = {{2013}},
}

@inproceedings{36920,
  abstract     = {{In the electronic system development, energy consumption is clearly becoming one of the most important design concerns. From the system level point of view, Dynamic Power Management (DPM) and Dynamic Voltage and Frequency Scaling (DVFS) are two mostly applied techniques to adjust the tradeoff between the performance and power dissipation at runtime. In this paper, we study the problem of combined application of both techniques with regard to hard real-time systems running on cluster-based multi-core processors. To optimize the processor energy consumption, a heuristic based on simulated annealing with efficient termination criterion is proposed. The experiment results show that the proposed algorithm outperforms the existing approaches in terms of the energy reduction. }},
  author       = {{He, Da and Müller, Wolfgang}},
  booktitle    = {{Proceedings of the International Conference on Applied Computing (AC)}},
  editor       = {{Weghorn, Hans}},
  isbn         = {{978-989-8533-20-3 }},
  keywords     = {{Dynamic Power Management, Dynamic Voltage and Frequency Scaling, Hard Real-Time, Multi-core Processor}},
  title        = {{{An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors}}},
  year         = {{2013}},
}