@inproceedings{25744,
  author       = {{Joy, M. tech. Mabel Mary and Becker, Markus and Mathews, Emi and Müller, Wolfgang}},
  booktitle    = {{ In Proceedings of Advanced Computing and Communications Conference 2012 (ADCOM 2012)}},
  location     = {{ Bangalore, 14. - 16. Dez. 2012, IEEE}},
  publisher    = {{IEEE}},
  title        = {{{Automated Source Code Annotation for Timing Analysis of Embedded Software}}},
  year         = {{2012}},
}

@inproceedings{25758,
  author       = {{Becker, Markus and Baldin, Daniel and Kuznik, Christoph and Joy, M. tech. Mabel Mary and Xie, Tao and Müller, Wolfgang}},
  booktitle    = {{EMSOFT'12: Teenth ACM International Conference on Embedded Software 2012 Proceedings }},
  title        = {{{XEMU: An Efficient QEMU Based Binary Mutation Testing Framework for Embedded Software}}},
  year         = {{2012}},
}

@inproceedings{25761,
  author       = {{Oliveira, Marcio F. and Kuznik, Christoph and Le, Hoang M. and Große, Daniel and Haedicke, Finn and Müller, Wolfgang and Drechsler, Rolf and Ecker, Wolfgang and Esen, Volkan}},
  booktitle    = {{CODES/ISSS '12: Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Proceedings}},
  title        = {{{The System Verification Methodology for Advanced TLM Verification}}},
  year         = {{2012}},
}

@inproceedings{25767,
  author       = {{He, Da and Müller, Wolfgang}},
  booktitle    = {{15th Euromicro Conference on Digital System Design (DSD)}},
  publisher    = {{IEEE Xplore}},
  title        = {{{A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms}}},
  year         = {{2012}},
}

@inproceedings{26022,
  author       = {{Becker, Markus and Kuznik, Christoph and Joy, M. tech. Mabel Mary and Xie, Tao and Müller, Wolfgang}},
  booktitle    = {{ 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)}},
  title        = {{{Binary Mutation Testing Through Dynamic Translation}}},
  year         = {{2012}},
}

@inproceedings{26023,
  author       = {{He, Da and Müller, Wolfgang}},
  booktitle    = {{Third International Symposium on Advances in Embedded Systems and Applications (ESA-2012)}},
  publisher    = {{IEEE Xplore}},
  title        = {{{Enhanced Schedulability Analysis of Hard Real-Time Systems on Power Manageable Multi-Core Platforms}}},
  year         = {{2012}},
}

@inproceedings{26024,
  author       = {{Radke, Stephan and Rülke, Steffen and Oliveira, Marcio F. and Kuznik, Christoph and Müller, Wolfgang and Ecker, Wolfgang and Esen, Volkan and Hufnagel, Simon and Bannow, Nico and Oetjens, Jan-Hendrik and Brazdrum, Helmut and Janssen, Peter and Le, Hoang M. and Große, Daniel and Haedicke, Finn and Drechsler, Rolf and Koch, Gernot and Burger, Andreas and Bringmann, Oliver and Rosenstiel, Wolfgang and Görgen, Ralph}},
  booktitle    = {{edaWorkshop 12}},
  title        = {{{Compilation of Methodologies to Speed up the Verification Process at System Level}}},
  year         = {{2012}},
}

@inproceedings{26031,
  author       = {{He, Da and Müller, Wolfgang}},
  booktitle    = {{2012 IEEE 15th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC)}},
  publisher    = {{IEEE Xplore}},
  title        = {{{Online Energy-Efficient Hard Real-Time Scheduling for Component Oriented Systems}}},
  year         = {{2012}},
}

@inproceedings{26036,
  author       = {{Oliveira, Marcio F. and Kuznik, Christoph and Müller, Wolfgang and Ecker, Wolfgang and Esen, Volkan}},
  booktitle    = {{Proceeding of Design and Verification Conference (DVCON)}},
  title        = {{{A SystemC Library for Advanced TLM Verification}}},
  year         = {{2012}},
}

@inproceedings{26079,
  author       = {{Becker, Markus and Gnokam Defo, Gilles Bertrand and Müller, Wolfgang and Fummi, F. and Pravadelli, G. and Vinco, Sara}},
  booktitle    = {{Design, Automation and Test in Europe (DATE 2012)}},
  title        = {{{MOUSSE: scaling MOdelling and verification to complex heterogeneoUS embedded Systems Evolution}}},
  year         = {{2012}},
}

@inproceedings{26080,
  author       = {{Becker, Markus and Kuznik, Christoph and Joy, M. tech. Mabel and Xie, Tao and Müller, Wolfgang}},
  booktitle    = {{Design, Automation and Test in Europe DATE}},
  title        = {{{XEMU: A QEMU Based Binary Mutation Testing Framework}}},
  year         = {{2012}},
}

@inproceedings{26092,
  author       = {{Müller, Wolfgang and Becker, Markus and Zabel, Henning and Elfeky, Ahmed and DiPasquale, Anthony}},
  booktitle    = {{In Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012}},
  title        = {{{Virtual Prototyping of Cyber-Physical Systems}}},
  year         = {{2012}},
}

@inbook{26695,
  abstract     = {{The Unified Modeling Language (UML) is now widely accepted by the software community. More recently, UML has attracted attention as a unification language for systems description combining both hardware and software components. First, it has been recognized that electronic systems design can no longer be seen as an isolated hardware design activity. In addition, recent advances in tools supporting high level hardware synthesis from electronic system level languages, which are predominantly based on C/C++, open new perspectives for automatic code generation from UML models and opportunities to enhance the link between a high level specification and a concrete hardware/software implementation. Finally, UML has become a general purpose language which can be customized for specific purposes, such as the modelization of electronic systems. This chapter presents recent advances of the UML language applied to System-on-Chip (SoC) and hardware-related embedded systems design. In particular, several examples of specific UML customizations (UML profiles) relevant for SoC design are summarized. Various approaches associating UML with existing hardware/software design languages are presented. The question of tool support and association with well-known simulation environments, such as MATLAB/Simulink, is addressed as well. A concrete example of a UML profile for hardware/software co-modeling and code generation for hardware/software co-simulation is presented in more details for illustration purposes.}},
  author       = {{Vanderperren, Yves and Müller, Wolfgang and He, Da and Mischkalla, Fabian and Dahaene, Wim}},
  booktitle    = {{Design Technology for Heterogeneous Embedded Systems}},
  editor       = {{Nicolescu, Gabriela and O'Connor, Ian and Piguet, Christian}},
  isbn         = {{978-94-007-1125-9}},
  pages        = {{13--39}},
  publisher    = {{Springer Verlag}},
  title        = {{{Extending UML for Electronic Systems Design: A Code Generation Perspective}}},
  year         = {{2012}},
}

@article{26038,
  abstract     = {{We present an enhanced UVM for SystemC library which incorporates verification best practices from OVM-ML and UVM as well as project partner implementations. Moreover, we extended functionality and implemented missing features, such as domain specific components, stimuli sequence generation and management, call-back facilities, response to request routing, transaction recording and many more. Apart from that, we added crucial verification components, such as functional coverage.}},
  author       = {{Kuznik, Christoph and Oliveira, Marcio F. and Müller, Wolfgang}},
  journal      = {{Design, Automation and Test in Europe DATE}},
  location     = {{ University Booth, Dresden , Mrz. 2012}},
  title        = {{{SYSTEMC UVM VERIFICATION COMPONENTS}}},
  year         = {{2012}},
}

@book{53593,
  editor       = {{Müller, Wolfgang and Ecker, Wolfgang}},
  title        = {{{Proceedings of the 1st Workshop on Metamodelling and Code Generation for Embedded Systems - MeCoEs }}},
  year         = {{2012}},
}

@inproceedings{36922,
  abstract     = {{In this paper we present an approach for the self reconfiguration of distributed micro-controllers for increased fault tolerance. Based on a modified distributed system topology utilizing a time division multiple access (TDMA) protocol, i.e., Flex Ray, we present a self-organized distributed coordinator concept which performs the self-reconfiguration in the case of node failures. We introduce a distributed coordinator, which utilizes redundant slots in the Flex Ray communication schedule and combines messages in configured protocol frames and slots to avoid a complete bus restart. As such, the self-reconfiguration is realized by means of predetermined information about resulting changes in the communication dependencies and (re-)assignments determined in the design phase. To retrieve the necessary information, we present an analytical approach, which determines a combined solution for the initial configuration and all possible reconfigurations for the remaining nodes of the Flex Ray network in case of node failures. Hence, through this method we can design self-reconfiguring network-based systems enabling the handling of node failures for an increased fault tolerance.}},
  author       = {{Klobedanz, Kay and Müller, Wolfgang and Rettberg, Achim}},
  keywords     = {{Real time systems, Fault tolerant systems, Schedules, Protocols, Redundancy, Delay}},
  publisher    = {{IEEE}},
  title        = {{{An Approach for Self-Reconfiguring and Fault-Tolerant Distributed Real-Time Systems}}},
  doi          = {{10.1109/ISORCW.2012.41}},
  year         = {{2012}},
}

@inproceedings{36921,
  author       = {{Oliveira, M. F. and Kuznik, Christoph and Müller, Wolfgang and Esen, V. and Ecker, W.}},
  booktitle    = {{Proceedings of the Design & Verification Conference (DVCon)}},
  title        = {{{Towards an Enhanced UVM for SystemC}}},
  year         = {{2012}},
}

@inproceedings{36994,
  abstract     = {{This paper proposes a quality driven, simulation based approach to functional design verification, which applies mainly to IP-level HDL designs with well specified test instruction format and is evaluated on a soft microprocessor core MB-LITE [5]. The approach utilizes mutation analysis as the quality metric to steer an automated simulation data generation process. It leads to a simulation flow with two phases towards an enhanced mutation analysis result. First in a random simulation phase, an in-loop heuristics is deployed and adjusts dynamically the test probability distribution so as to improve the coverage efficiency. Next, for each remaining hard-to-kill mutant, a search heuristics on test input space is developed to iteratively locate a target test, using a specific objective cost function for the goal of killing HDL mutant. The effectiveness of this integrated two-phase simulation flow is demonstrated by the results with the MB-LITE microprocessor IP.}},
  author       = {{Xie, Tao  and Müller, Wolfgang and Letombe, Florian}},
  booktitle    = {{Proceedings of SOCC2012}},
  keywords     = {{Analytical models, Hardware design languages, Microprocessors, Cost function, Data models, Search problems, IP networks}},
  publisher    = {{IEEE}},
  title        = {{{Mutation-Analysis Driven Functional Verification of a Soft Microprocessor}}},
  doi          = {{10.1109/SOCC.2012.6398362}},
  year         = {{2012}},
}

@inproceedings{36997,
  author       = {{Xie, Tao and Müller, Wolfgang}},
  booktitle    = {{Proceedings of the MeCoES’12}},
  title        = {{{An IP-XACT-TO-SystemC Model Generator for Mutation Analysis}}},
  year         = {{2012}},
}

@inproceedings{26667,
  author       = {{Kuznik, Christoph and Müller, Wolfgang}},
  booktitle    = {{Proc. of the 8th International SoC Design Conference 2011 (ISOCC 2011)}},
  title        = {{{Aspect enhanced functional coverage driven verification in the SystemC HDVL}}},
  year         = {{2011}},
}