@inproceedings{26080, author = {{Becker, Markus and Kuznik, Christoph and Joy, M. tech. Mabel and Xie, Tao and Müller, Wolfgang}}, booktitle = {{Design, Automation and Test in Europe DATE}}, title = {{{XEMU: A QEMU Based Binary Mutation Testing Framework}}}, year = {{2012}}, } @inproceedings{26092, author = {{Müller, Wolfgang and Becker, Markus and Zabel, Henning and Elfeky, Ahmed and DiPasquale, Anthony}}, booktitle = {{In Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012}}, title = {{{Virtual Prototyping of Cyber-Physical Systems}}}, year = {{2012}}, } @inbook{26695, abstract = {{The Unified Modeling Language (UML) is now widely accepted by the software community. More recently, UML has attracted attention as a unification language for systems description combining both hardware and software components. First, it has been recognized that electronic systems design can no longer be seen as an isolated hardware design activity. In addition, recent advances in tools supporting high level hardware synthesis from electronic system level languages, which are predominantly based on C/C++, open new perspectives for automatic code generation from UML models and opportunities to enhance the link between a high level specification and a concrete hardware/software implementation. Finally, UML has become a general purpose language which can be customized for specific purposes, such as the modelization of electronic systems. This chapter presents recent advances of the UML language applied to System-on-Chip (SoC) and hardware-related embedded systems design. In particular, several examples of specific UML customizations (UML profiles) relevant for SoC design are summarized. Various approaches associating UML with existing hardware/software design languages are presented. The question of tool support and association with well-known simulation environments, such as MATLAB/Simulink, is addressed as well. A concrete example of a UML profile for hardware/software co-modeling and code generation for hardware/software co-simulation is presented in more details for illustration purposes.}}, author = {{Vanderperren, Yves and Müller, Wolfgang and He, Da and Mischkalla, Fabian and Dahaene, Wim}}, booktitle = {{Design Technology for Heterogeneous Embedded Systems}}, editor = {{Nicolescu, Gabriela and O'Connor, Ian and Piguet, Christian}}, isbn = {{978-94-007-1125-9}}, pages = {{13--39}}, publisher = {{Springer Verlag}}, title = {{{Extending UML for Electronic Systems Design: A Code Generation Perspective}}}, year = {{2012}}, } @article{26038, abstract = {{We present an enhanced UVM for SystemC library which incorporates verification best practices from OVM-ML and UVM as well as project partner implementations. Moreover, we extended functionality and implemented missing features, such as domain specific components, stimuli sequence generation and management, call-back facilities, response to request routing, transaction recording and many more. Apart from that, we added crucial verification components, such as functional coverage.}}, author = {{Kuznik, Christoph and Oliveira, Marcio F. and Müller, Wolfgang}}, journal = {{Design, Automation and Test in Europe DATE}}, location = {{ University Booth, Dresden , Mrz. 2012}}, title = {{{SYSTEMC UVM VERIFICATION COMPONENTS}}}, year = {{2012}}, } @book{53593, editor = {{Müller, Wolfgang and Ecker, Wolfgang}}, title = {{{Proceedings of the 1st Workshop on Metamodelling and Code Generation for Embedded Systems - MeCoEs }}}, year = {{2012}}, } @inproceedings{36922, abstract = {{In this paper we present an approach for the self reconfiguration of distributed micro-controllers for increased fault tolerance. Based on a modified distributed system topology utilizing a time division multiple access (TDMA) protocol, i.e., Flex Ray, we present a self-organized distributed coordinator concept which performs the self-reconfiguration in the case of node failures. We introduce a distributed coordinator, which utilizes redundant slots in the Flex Ray communication schedule and combines messages in configured protocol frames and slots to avoid a complete bus restart. As such, the self-reconfiguration is realized by means of predetermined information about resulting changes in the communication dependencies and (re-)assignments determined in the design phase. To retrieve the necessary information, we present an analytical approach, which determines a combined solution for the initial configuration and all possible reconfigurations for the remaining nodes of the Flex Ray network in case of node failures. Hence, through this method we can design self-reconfiguring network-based systems enabling the handling of node failures for an increased fault tolerance.}}, author = {{Klobedanz, Kay and Müller, Wolfgang and Rettberg, Achim}}, keywords = {{Real time systems, Fault tolerant systems, Schedules, Protocols, Redundancy, Delay}}, publisher = {{IEEE}}, title = {{{An Approach for Self-Reconfiguring and Fault-Tolerant Distributed Real-Time Systems}}}, doi = {{10.1109/ISORCW.2012.41}}, year = {{2012}}, } @inproceedings{36921, author = {{Oliveira, M. F. and Kuznik, Christoph and Müller, Wolfgang and Esen, V. and Ecker, W.}}, booktitle = {{Proceedings of the Design & Verification Conference (DVCon)}}, title = {{{Towards an Enhanced UVM for SystemC}}}, year = {{2012}}, } @inproceedings{36994, abstract = {{This paper proposes a quality driven, simulation based approach to functional design verification, which applies mainly to IP-level HDL designs with well specified test instruction format and is evaluated on a soft microprocessor core MB-LITE [5]. The approach utilizes mutation analysis as the quality metric to steer an automated simulation data generation process. It leads to a simulation flow with two phases towards an enhanced mutation analysis result. First in a random simulation phase, an in-loop heuristics is deployed and adjusts dynamically the test probability distribution so as to improve the coverage efficiency. Next, for each remaining hard-to-kill mutant, a search heuristics on test input space is developed to iteratively locate a target test, using a specific objective cost function for the goal of killing HDL mutant. The effectiveness of this integrated two-phase simulation flow is demonstrated by the results with the MB-LITE microprocessor IP.}}, author = {{Xie, Tao and Müller, Wolfgang and Letombe, Florian}}, booktitle = {{Proceedings of SOCC2012}}, keywords = {{Analytical models, Hardware design languages, Microprocessors, Cost function, Data models, Search problems, IP networks}}, publisher = {{IEEE}}, title = {{{Mutation-Analysis Driven Functional Verification of a Soft Microprocessor}}}, doi = {{10.1109/SOCC.2012.6398362}}, year = {{2012}}, } @inproceedings{36997, author = {{Xie, Tao and Müller, Wolfgang}}, booktitle = {{Proceedings of the MeCoES’12}}, title = {{{An IP-XACT-TO-SystemC Model Generator for Mutation Analysis}}}, year = {{2012}}, } @inproceedings{26667, author = {{Kuznik, Christoph and Müller, Wolfgang}}, booktitle = {{Proc. of the 8th International SoC Design Conference 2011 (ISOCC 2011)}}, title = {{{Aspect enhanced functional coverage driven verification in the SystemC HDVL}}}, year = {{2011}}, } @inproceedings{26669, author = {{Xie, Tao and Müller, Wolfgang}}, booktitle = {{Proceedings of the 16th IEEE International High Level Design Validation and Test Workshop (HLDVT)}}, title = {{{IP-XACT based System Level Mutation Testing}}}, year = {{2011}}, } @inproceedings{26698, author = {{Xie, Tao and Müller, Wolfgang}}, booktitle = {{Proceedings of the 14th Euromicro Conference on Digital System Design (DSD)}}, title = {{{HDL-Mutation Based Simulation Data Generation by Propagation Guided Search}}}, year = {{2011}}, } @article{26705, abstract = {{In the area of dynamic verification of virtual prototypes, functional coverage is a valuable tool for answering the "Are we done?" question and achieving verification closure. Recent verification methodologies such as OVM and UVM contain multi-language support that provides a basic SystemC version. However, due to language shortcoming they cannot be utilized for the same amount of verification tasks in the SystemC ecosystem as in other supported hardware design and verification languages. In this presentation, we propose to boost the verification capabilities of SystemC by implementing functional coverage collection and evaluation according to the same metric as defined in the widely accepted IEEE-1800 SystemVerilog cover group feature. We implement a functional coverage library to enable coverage-driven verification of SystemC designs on multiple levels of abstraction enabling value, transition, and expression coverage. To our knowledge, the overall functionalities are not available in the IEEE-1666 SystemC standard or the SCV add-on library, nor are they complete compared to the aforementioned in any publicly available SystemC library. }}, author = {{Kuznik, Christoph and Müller, Wolfgang}}, journal = {{North American SystemC User Group Meeting (16th)}}, title = {{{Verification Closure of SystemC Designs with Functional Coverage}}}, year = {{2011}}, } @inproceedings{26710, author = {{Becker, Markus and Zabel, Henning and Müller, Wolfgang and Elfeky, Ahmed and DiPasquale, Anthony}}, booktitle = {{8. Paderborner Workshop Entwurf mechatronischer Systeme, Band 294}}, pages = {{315--327}}, publisher = {{Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}}, title = {{{Virtual Prototyping softwareintensiver mechatronischer Systeme – Eine Fallstudie}}}, volume = {{294}}, year = {{2011}}, } @inproceedings{26713, author = {{Klobedanz, Kay and König, A. and Müller, Wolfgang}}, booktitle = {{Proceedings of Design, Automation, Test Europe - DATE2011}}, location = {{14. - 18. Mrz. 2011}}, publisher = {{IEEE Computer Society Press}}, title = {{{A Reconfiguration Approach for Fault-Tolerant FlexRay Networks}}}, year = {{2011}}, } @inproceedings{26714, author = {{Klobedanz, Kay and König, A. and Müller, Wolfgang and Rettberg, Achim}}, booktitle = {{Second IEEE Workshop on Self-Organizing Real-Time Systems - SORT 2011}}, publisher = {{IEEE Computer Society Press}}, title = {{{Self-Reconfiguration for Fault-Tolerant FlexRay Networks}}}, year = {{2011}}, } @inproceedings{26715, abstract = {{SystemC is a versatile C++ based design and verification language, offering various mechanisms and constructs required for embedded systems modeling. Using the add-on SystemC Verification Library (SCV) elemental constrained-random stimuli techniques may be used for verification. However, SCV has several drawbacks such as lack of a functional coverage facility supporting coverage collection on RTL and TLM models. In this article we present a functional coverage library which implements parts of the IEEE 1800-2005 SystemVerilog standard capturing functional coverage throughout the design and verification process, and allows to facilitate coverage-driven verification in SystemC.}}, author = {{Kuznik, Christoph and Müller, Wolfgang}}, booktitle = {{Proceedings of DVCON }}, title = {{{Functional Coverage-driven Verification with SystemC on Multiple Level of Abstraction}}}, year = {{2011}}, } @inproceedings{26716, abstract = {{UML profiles like SysML and MARTE have been a major research topic in electronic system design, but are mainly applied for specification and analysis in early design phases. High-Level Synthesis (HLS), however, addresses the physical implementation aspect of electronic systems, and thus leads to different requirements on the accuracy of models. For this, modular interfaces are a novel object-oriented synthesizable technique to overcome the conflict between a higher degree of abstraction and necessary details for further synthesis. In this paper, we present our approach to use SysML as an adequate modeling language for modular interfaces and C/C++/SystemC-based HLS. We extended SysML with annotations for synthesizable SystemC and high-level synthesis constraints and implemented a code generation scheme to achieve design flow automation. Based on the SysML editor Artisan Studio and an industrial case study, we demonstrate the applicability of SysML as a retargetable front-end for HLS design flows.}}, author = {{Mischkalla, Fabian and He, Da and Müller, Wolfgang}}, booktitle = {{Proceedings of 2nd Workshop on Model Based Engineering for Embedded Systems Design (M-BED)}}, title = {{{A Retargetable SysML-based Front-End for High-Level Synthesis}}}, year = {{2011}}, } @inproceedings{26717, author = {{He, Da and Mischkalla, Fabian and Müller, Wolfgang}}, booktitle = {{Proceedings of 1st international QEMU Users Forum}}, title = {{{A SysML-based Framework with QEMU-SystemC Code Generation}}}, year = {{2011}}, } @inproceedings{26784, author = {{Gnokam Defo, Gilles Bertrand and Müller, Wolfgang}}, booktitle = {{Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)}}, title = {{{Synchronisation eines SystemC Restbus-Simulators mit einem Hardware-In-the-Loop FlexRay Netzwerk}}}, year = {{2011}}, }