@inproceedings{26714, author = {{Klobedanz, Kay and König, A. and Müller, Wolfgang and Rettberg, Achim}}, booktitle = {{Second IEEE Workshop on Self-Organizing Real-Time Systems - SORT 2011}}, publisher = {{IEEE Computer Society Press}}, title = {{{Self-Reconfiguration for Fault-Tolerant FlexRay Networks}}}, year = {{2011}}, } @inproceedings{26715, abstract = {{SystemC is a versatile C++ based design and verification language, offering various mechanisms and constructs required for embedded systems modeling. Using the add-on SystemC Verification Library (SCV) elemental constrained-random stimuli techniques may be used for verification. However, SCV has several drawbacks such as lack of a functional coverage facility supporting coverage collection on RTL and TLM models. In this article we present a functional coverage library which implements parts of the IEEE 1800-2005 SystemVerilog standard capturing functional coverage throughout the design and verification process, and allows to facilitate coverage-driven verification in SystemC.}}, author = {{Kuznik, Christoph and Müller, Wolfgang}}, booktitle = {{Proceedings of DVCON }}, title = {{{Functional Coverage-driven Verification with SystemC on Multiple Level of Abstraction}}}, year = {{2011}}, } @inproceedings{26716, abstract = {{UML profiles like SysML and MARTE have been a major research topic in electronic system design, but are mainly applied for specification and analysis in early design phases. High-Level Synthesis (HLS), however, addresses the physical implementation aspect of electronic systems, and thus leads to different requirements on the accuracy of models. For this, modular interfaces are a novel object-oriented synthesizable technique to overcome the conflict between a higher degree of abstraction and necessary details for further synthesis. In this paper, we present our approach to use SysML as an adequate modeling language for modular interfaces and C/C++/SystemC-based HLS. We extended SysML with annotations for synthesizable SystemC and high-level synthesis constraints and implemented a code generation scheme to achieve design flow automation. Based on the SysML editor Artisan Studio and an industrial case study, we demonstrate the applicability of SysML as a retargetable front-end for HLS design flows.}}, author = {{Mischkalla, Fabian and He, Da and Müller, Wolfgang}}, booktitle = {{Proceedings of 2nd Workshop on Model Based Engineering for Embedded Systems Design (M-BED)}}, title = {{{A Retargetable SysML-based Front-End for High-Level Synthesis}}}, year = {{2011}}, } @inproceedings{26717, author = {{He, Da and Mischkalla, Fabian and Müller, Wolfgang}}, booktitle = {{Proceedings of 1st international QEMU Users Forum}}, title = {{{A SysML-based Framework with QEMU-SystemC Code Generation}}}, year = {{2011}}, } @inproceedings{26784, author = {{Gnokam Defo, Gilles Bertrand and Müller, Wolfgang}}, booktitle = {{Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)}}, title = {{{Synchronisation eines SystemC Restbus-Simulators mit einem Hardware-In-the-Loop FlexRay Netzwerk}}}, year = {{2011}}, } @inproceedings{26789, abstract = {{Mutation analysis is a powerful tool for white-box testing of the verification environment in order to produce dependable and higher quality software products. However, due to high computational costs and the focus on high-level software languages such as Java mutation analysis is not yet widely used in commercial design flows targeting embedded (software) systems. Here the industry is modeling both hardware and related software parts at higher levels of abstraction, called virtual prototypes, to accelerate parallel development and shorten time-to-market. In this paper we propose a mutation testing verification flow for SystemC based virtual prototypes that may not rely on source code only but on annotated basic blocks and enables mutant creation at assembler level to heavily reduce execution costs and equivalence mutants likelihood.}}, author = {{Kuznik, Christoph and Müller, Wolfgang}}, booktitle = {{Proceedings of the 17th IEEE Pacific Rim International Symposium on Dependable Computing}}, title = {{{Native binary mutation analysis for embedded software and virtual prototypes in SystemC}}}, year = {{2011}}, } @book{53580, editor = {{Müller, Wolfgang and Petrot, Frederic}}, location = {{Grenoble, France}}, title = {{{Proceedings of the 1st International QEMU Users' Forum}}}, year = {{2011}}, } @inproceedings{37001, author = {{Becker, Markus and Zabel, Henning and Müller, Wolfgang and Elfeky, Ahmed}}, title = {{{Virtual Prototyping software-intensiver mechatronischer Systeme - Eine Fallstudie}}}, year = {{2011}}, } @inproceedings{37005, author = {{Kuznik, Christoph and Müller, Wolfgang}}, location = {{San Jose, CA}}, title = {{{A SystemC Based Library for Functional Coverage}}}, year = {{2011}}, } @inproceedings{37006, abstract = {{In this paper we present an approach for the configuration and reconfiguration of FlexRay networks to increase their fault tolerance. To guarantee a correct and deterministic system behavior, the FlexRay specification does not allow a reconfiguration of the schedapproachule during run time. To avoid the necessity of a complete bus restart in case of a node failure, we propose a reconfiguration using redundant slots in the schedule and/or combine messages in existing frames and slots, to compensate node failures and increase robustness. Our approach supports the developer to increase the fault tolerance of the system during the design phase. It is a heuristic, which, additionally to a determined initial configuration, calculates possible reconfigurations for the remaining nodes of the FlexRay network in case of a node failure, to keep the system working properly. An evaluation by means of realistic safety-critical automotive real-time systems revealed that it determines valid reconfigurations for up to 80% of possible individual node failures. In summary, our approach offers major support for the developer of FlexRay networks since the results provide helpful feedback about reconfiguration capabilities. In an iterative design process these information can be used to determine and optimize valid reconfigurations.}}, author = {{Klobedanz, Kay and König, Andreas and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE'11}}, keywords = {{Schedules, Fault tolerant systems, Redundancy, Protocols, Automotive engineering, Genetic algorithms}}, location = {{Grenoble, France}}, publisher = {{IEEE}}, title = {{{A Reconfiguration Approach for Faul-Tolerant FlexRay Networks}}}, doi = {{10.1109/DATE.2011.5763022}}, year = {{2011}}, } @inproceedings{37002, abstract = {{HDL-mutation based fault injection and analysis is considered as an important coverage metric for measuring the quality of design simulation processes [20, 3, 1, 2]. In this work, we try to solve the problem of automatic simulation data generation targeting HDL mutation faults. We follow a search based approach and eliminate the need for symbolic execution and mathematical constraint solving from existing work. An objective cost function is defined on the test input space and serves the guidance of search for fault-detecting test data. This is done by first mapping the simulation traces under a test onto a control and data flow graph structure which is extracted from the design. Then the progress of fault detection can be measured quantitatively on this graph to be the cost value. By minimizing this cost we approach the target test data. The effectiveness of the cost function is investigated under an example neighborhood search scheme. Case study with a floating point arithmetic IP design has shown that the cost function is able to guide effectively the search procedure towards a fault-detecting test. The cost calculation time as the search overhead was also observed to be minor compared to the actual design simulation time.}}, author = {{Xie, Tao and Müller, Wolfgang and Letombe, Florian}}, booktitle = {{Proceedings of Euromicro DSD 2011}}, isbn = {{978-1-4577-1048-3}}, keywords = {{Hardware design languages, Cost function, Computational modeling, Fault detection, Data models, Analytical models, Testing}}, publisher = {{IEEE}}, title = {{{HDL-Mutation Based Simulation Data Generation by Propagation Guided Search}}}, doi = {{10.1109/DSD.2011.83}}, year = {{2011}}, } @inproceedings{36999, author = {{Becker, Markus and Zabel, Henning and Müller, Wolfgang and Elfeky, Ahmed}}, title = {{{Virtual Prototyping software-intensiver mechatronischer Systeme - Eine Fallstudie}}}, year = {{2011}}, } @book{53582, editor = {{Gerard, Sebatian and Müller, Wolfgang and Rioux, L. and Selic, Brand}}, title = {{{Proceedings of the 1st Workshop on Model Based Engineering for Embedded Systems Design}}}, year = {{2010}}, } @inproceedings{37007, abstract = {{UML is widely applied for the specification and modeling of software and some studies have demonstrated that it is applicable for HW/SW codesign. However, in this area there is still a big gap from UML modeling to SystemC-based verification and synthesis environments. This paper presents an efficient approach to bridge this gap in the context of Systems-on-a-Chip (SoC) design. We propose a framework for the seamless integration of a customized SysML entry with code generation for HW/SW cosimulation and high-level FPGA synthesis. For this, we extended the SysML UML profile by SystemC and synthesis capabilities. Two case studies demonstrate the applicability of our approach.}}, author = {{Mischkalla, Fabian and He, Da and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{Unified modeling language, Field programmable gate arrays, Bridges, Helium, Real time systems, Operating systems, Documentation, Application software, XML, Space exploration}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems}}}, doi = {{10.1109/DATE.2010.5456990}}, year = {{2010}}, } @inproceedings{37009, abstract = {{Today, mobile and embedded real time systems have to cope with the migration and allocation of multiple software tasks running on top of a real time operating system (RTOS) residing on one or several processors. For scaling of each task set and processor configuration, instruction set simulation and worst case timing analysis are typically applied. This paper presents a complementary approach for the verification of RTOS properties based on an abstract RTOS-Model in SystemC. We apply IEEE P1850 PSL for which we present an approach and first experiences for the assertion-based verification of RTOS properties.}}, author = {{Oliveira, Marcio F. S. and Zabel, Henning and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{Operating systems, Real time systems, Timing, Hardware, Analytical models, Embedded software, Software systems, Processor scheduling, Software performance, Performance analysis}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{Assertion-Based Verification of RTOS Properties}}}, doi = {{10.1109/DATE.2010.5457130}}, year = {{2010}}, } @inproceedings{37011, abstract = {{Safety-critical automotive systems must fulfill hard real-time constraints for reliability and safety. This paper presents a case study for the application of an AUTOSAR-based language for timing modeling and analysis. We present and apply the Timing Augmented Description Language (TADL) and demonstrate a methodology for the development of a speed-adaptive steer-by-wire system. We examine the impact of TADL and the methodology on the development process and the suitability and interoperability of the applied tools with respect to the AUTOSAR-based tool chain in the context of our case study.}}, author = {{Klobedanz, Kay and Kuznik, Christoph and Thuy, Andre and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE’10, Dresden}}, keywords = {{Timing, Programming, Automotive engineering, Application software, Hardware, Computer architecture, Communication system software, Software architecture, Delay, Software standards}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study}}}, doi = {{10.1109/DATE.2010.5457125}}, year = {{2010}}, } @inproceedings{37037, abstract = {{Today we can identify a big gap between requirement specification and the generation of test environments. This article extends the Classification Tree Method for Embedded Systems (CTM/ES) to fill this gap by new concepts for the precise specification of stimuli for operational ranges of continuous control systems. It introduces novel means for continuous acceptance criteria definition and for functional coverage definition.}}, author = {{Krupp, Alexander and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{System testing, Automatic testing, Object oriented modeling, Classification tree analysis, Automotive engineering, Mathematical model, Embedded system, Control systems, Electronic equipment testing, Software testing}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{A Systematic Approach to Combined HW/SW System Test}}}, doi = {{10.1109/DATE.2010.5457186}}, year = {{2010}}, } @inproceedings{37040, abstract = {{Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms.}}, author = {{Becker, Markus and Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli, Graziano and Xie, Tao}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{Timing, Hardware, Operating systems, Process design, Accuracy, Standards development, Context modeling, Real time systems, Communication channels, Microprogramming}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{RTOS-Aware Refinement for TLM2.0-based HW/SW Design}}}, doi = {{10.1109/DATE.2010.5456965}}, year = {{2010}}, } @inproceedings{37046, abstract = {{In this article, we present a flexible simulation environment for embedded real-time software refinement by a mixed level cosimulation. For this, we combine the native speed of an abstract real-time operating system (RTOS) model in SystemC with dynamic binary translation for fast Instruction Set Simulation (ISS) by QEMU. In order to support stepwise RTOS software refinement from system level to the target software, each task can be separately migrated between the native execution and the ISS. By adapting the dynamic binary translation approach to an efficient but yet very accurate synchronization scheme the overhead of QEMU user mode execution is only factor two compared to native SystemC. Furthermore, the simulation speed increases almost linearly according to the utilization of the task set abstracted by the native execution. Hereby, the simulation time can be considerably reduced by cosimulating just a subset of tasks on QEMU.}}, author = {{Becker, Markus and Zabel, Henning and Müller, Wolfgang}}, editor = {{Kleinjohann, L. and Kleinjohann, B.}}, isbn = {{978-3-642-15233-7}}, keywords = {{Application Programming Interface User Mode Kernel Space System Level Design Mixed Level}}, publisher = {{Springer Verlag}}, title = {{{A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement}}}, doi = {{10.1007/978-3-642-15234-4_15}}, year = {{2010}}, } @inproceedings{37044, abstract = {{In this paper we present new concepts to resolve ECU (Electronic Control Unit) failures in FlexRay networks. Our approach extends the FlexRay bus schedule by redundant slots with modifications in the communication and slot assignment. We introduce additional backup nodes to replace faulty nodes. To reduce the required memory resources of the backup nodes, we distribute redundant tasks over different nodes and propose the migration of tasks to the backup node at runtime. We investigate different solutions to migrate the redundant tasks to the backup node by time-triggered and event-triggered transmissions.}}, author = {{Klobedanz, Kay and Defo, Gilles B. and Zabel, Henning and Müller, Wolfgang and Zhi, Yuan}}, editor = {{Kleinjohann, L. and Kleinjohann, B.}}, isbn = {{978-3-642-15233-7}}, keywords = {{Faulty Node Static Segment Slot Assignment Task Migration Communication Controller}}, publisher = {{Springer Verlag}}, title = {{{Task Migration for Fault-Tolerant FlexRay Networks}}}, doi = {{10.1007/978-3-642-15234-4_7}}, year = {{2010}}, }