[{"language":[{"iso":"eng"}],"department":[{"_id":"58"}],"user_id":"16243","_id":"58861","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"status":"public","publication":"OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits","type":"conference","title":"Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells","author":[{"last_name":"Luchterhandt","full_name":"Luchterhandt, Lars","first_name":"Lars"},{"last_name":"Govindasamy","full_name":"Govindasamy, Vivek","first_name":"Vivek"},{"first_name":"Yutong","last_name":"Wang","full_name":"Wang, Yutong"},{"full_name":"Dömer, Rainer","last_name":"Dömer","first_name":"Rainer"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"orcid":"0000-0002-5950-6618 ","last_name":"Scheytt","id":"37144","full_name":"Scheytt, J. Christoph","first_name":"J. Christoph"}],"date_created":"2025-02-26T14:40:23Z","date_updated":"2025-11-06T10:08:09Z","citation":{"apa":"Luchterhandt, L., Govindasamy, V., Wang, Y., Dömer, R., Müller, W., &#38; Scheytt, J. C. (2025). Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells. <i>OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits</i>.","short":"L. Luchterhandt, V. Govindasamy, Y. Wang, R. Dömer, W. Müller, J.C. Scheytt, in: OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits, Lyon, France, 2025.","mla":"Luchterhandt, Lars, et al. “Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells.” <i>OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits</i>, 2025.","bibtex":"@inproceedings{Luchterhandt_Govindasamy_Wang_Dömer_Müller_Scheytt_2025, place={Lyon, France}, title={Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells}, booktitle={OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits}, author={Luchterhandt, Lars and Govindasamy, Vivek and Wang, Yutong and Dömer, Rainer and Müller, Wolfgang and Scheytt, J. Christoph}, year={2025} }","chicago":"Luchterhandt, Lars, Vivek Govindasamy, Yutong Wang, Rainer Dömer, Wolfgang Müller, and J. Christoph Scheytt. “Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells.” In <i>OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits</i>. Lyon, France, 2025.","ieee":"L. Luchterhandt, V. Govindasamy, Y. Wang, R. Dömer, W. Müller, and J. C. Scheytt, “Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells,” 2025.","ama":"Luchterhandt L, Govindasamy V, Wang Y, Dömer R, Müller W, Scheytt JC. Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells. In: <i>OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits</i>. ; 2025."},"place":"Lyon, France","year":"2025"},{"publication_identifier":{"issn":["1063-8210"]},"publication_status":"published","year":"2025","citation":{"chicago":"Sadiye, Babak, Mohammed Iftekhar, Wolfgang Müller, and J. Christoph Scheytt. “60-Gb/s 1:4 Demultiplexer in 22-Nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design.” <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>, 2025. <a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">https://doi.org/10.1109/TVLSI.2025.3625787</a>.","ieee":"B. Sadiye, M. Iftekhar, W. Müller, and J. C. Scheytt, “60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design,” <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>, 2025, doi: <a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">10.1109/TVLSI.2025.3625787</a>.","ama":"Sadiye B, Iftekhar M, Müller W, Scheytt JC. 60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design. <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>. Published online 2025. doi:<a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">10.1109/TVLSI.2025.3625787</a>","bibtex":"@article{Sadiye_Iftekhar_Müller_Scheytt_2025, title={60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design}, DOI={<a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">10.1109/TVLSI.2025.3625787</a>}, journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, publisher={IEEE}, author={Sadiye, Babak and Iftekhar, Mohammed and Müller, Wolfgang and Scheytt, J. Christoph}, year={2025} }","short":"B. Sadiye, M. Iftekhar, W. Müller, J.C. Scheytt, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2025).","mla":"Sadiye, Babak, et al. “60-Gb/s 1:4 Demultiplexer in 22-Nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design.” <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>, IEEE, 2025, doi:<a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">10.1109/TVLSI.2025.3625787</a>.","apa":"Sadiye, B., Iftekhar, M., Müller, W., &#38; Scheytt, J. C. (2025). 60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design. <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>. <a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">https://doi.org/10.1109/TVLSI.2025.3625787</a>"},"date_updated":"2025-11-10T08:38:07Z","publisher":"IEEE","author":[{"first_name":"Babak","full_name":"Sadiye, Babak","id":"93634","last_name":"Sadiye"},{"first_name":"Mohammed","last_name":"Iftekhar","id":"47944","full_name":"Iftekhar, Mohammed"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"orcid":"0000-0002-5950-6618 ","last_name":"Scheytt","id":"37144","full_name":"Scheytt, J. Christoph","first_name":"J. Christoph"}],"date_created":"2025-11-10T08:31:47Z","title":"60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design","doi":"10.1109/TVLSI.2025.3625787","publication":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","type":"journal_article","status":"public","_id":"62148","project":[{"_id":"325","name":"Scale4Edge: Skalierbare Infrastruktur für Edge-Computing"}],"department":[{"_id":"58"}],"user_id":"93634","language":[{"iso":"eng"}]},{"citation":{"apa":"Iftekhar, M., Sadiye, B., Müller, W., &#38; Scheytt, J. C. (2025). A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology. <i>IEEE Nordic Circuits and Systems Conference (NORCAS)</i>. IEEE Nordic Circuits and Systems Conference (NORCAS), Riga, Latvia. <a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">https://doi.org/10.1109/NorCAS66540.2025.11231203</a>","short":"M. Iftekhar, B. Sadiye, W. Müller, J.C. Scheytt, in: IEEE Nordic Circuits and Systems Conference (NORCAS), 2025.","mla":"Iftekhar, Mohammed, et al. “A 50 Gbps Reference-Less NRZ Full-Rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 Nm SiGe:C BiCMOS Technology.” <i>IEEE Nordic Circuits and Systems Conference (NORCAS)</i>, 2025, doi:<a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">10.1109/NorCAS66540.2025.11231203</a>.","bibtex":"@inproceedings{Iftekhar_Sadiye_Müller_Scheytt_2025, title={A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology}, DOI={<a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">10.1109/NorCAS66540.2025.11231203</a>}, booktitle={IEEE Nordic Circuits and Systems Conference (NORCAS)}, author={Iftekhar, Mohammed and Sadiye, Babak and Müller, Wolfgang and Scheytt, J. Christoph}, year={2025} }","ama":"Iftekhar M, Sadiye B, Müller W, Scheytt JC. A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology. In: <i>IEEE Nordic Circuits and Systems Conference (NORCAS)</i>. ; 2025. doi:<a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">10.1109/NorCAS66540.2025.11231203</a>","chicago":"Iftekhar, Mohammed, Babak Sadiye, Wolfgang Müller, and J. Christoph Scheytt. “A 50 Gbps Reference-Less NRZ Full-Rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 Nm SiGe:C BiCMOS Technology.” In <i>IEEE Nordic Circuits and Systems Conference (NORCAS)</i>, 2025. <a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">https://doi.org/10.1109/NorCAS66540.2025.11231203</a>.","ieee":"M. Iftekhar, B. Sadiye, W. Müller, and J. C. Scheytt, “A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology,” presented at the IEEE Nordic Circuits and Systems Conference (NORCAS), Riga, Latvia, 2025, doi: <a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">10.1109/NorCAS66540.2025.11231203</a>."},"year":"2025","author":[{"full_name":"Iftekhar, Mohammed","id":"47944","last_name":"Iftekhar","first_name":"Mohammed"},{"full_name":"Sadiye, Babak","id":"93634","last_name":"Sadiye","first_name":"Babak"},{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"},{"orcid":"0000-0002-5950-6618 ","last_name":"Scheytt","id":"37144","full_name":"Scheytt, J. Christoph","first_name":"J. Christoph"}],"date_created":"2025-11-07T10:41:45Z","date_updated":"2025-11-20T10:34:13Z","conference":{"end_date":"2025-10-29","location":"Riga, Latvia","name":"IEEE Nordic Circuits and Systems Conference (NORCAS)","start_date":"2025-10-28"},"doi":"10.1109/NorCAS66540.2025.11231203","title":"A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology","type":"conference","publication":"IEEE Nordic Circuits and Systems Conference (NORCAS)","status":"public","user_id":"47944","department":[{"_id":"58"}],"project":[{"name":"Scale4Edge: Skalierbare Infrastruktur für Edge-Computing","_id":"325"}],"_id":"62126","language":[{"iso":"eng"}]},{"status":"public","publication":"MBMV 2025 - 28. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen","type":"conference","language":[{"iso":"eng"}],"_id":"58856","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"department":[{"_id":"58"}],"user_id":"16243","place":"Warnemünde","year":"2025","citation":{"mla":"Hannemann, Kai Arne, et al. “Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study.” <i>MBMV 2025 - 28. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen</i>, VDE Verlag, 2025.","bibtex":"@inproceedings{Hannemann_Bütün_Müller_Scheytt_2025, place={Warnemünde}, title={Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study}, booktitle={MBMV 2025 - 28. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen}, publisher={VDE Verlag}, author={Hannemann, Kai Arne and Bütün, Hüseyin Berke and Müller, Wolfgang and Scheytt, J. Christoph}, year={2025} }","short":"K.A. Hannemann, H.B. Bütün, W. Müller, J.C. Scheytt, in: MBMV 2025 - 28. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen, VDE Verlag, Warnemünde, 2025.","apa":"Hannemann, K. A., Bütün, H. B., Müller, W., &#38; Scheytt, J. C. (2025). Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study. <i>MBMV 2025 - 28. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen</i>.","ieee":"K. A. Hannemann, H. B. Bütün, W. Müller, and J. C. Scheytt, “Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study,” 2025.","chicago":"Hannemann, Kai Arne, Hüseyin Berke Bütün, Wolfgang Müller, and J. Christoph Scheytt. “Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study.” In <i>MBMV 2025 - 28. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen</i>. Warnemünde: VDE Verlag, 2025.","ama":"Hannemann KA, Bütün HB, Müller W, Scheytt JC. Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study. In: <i>MBMV 2025 - 28. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen</i>. VDE Verlag; 2025."},"publication_identifier":{"isbn":["978-3-8007-6515-7"]},"title":"Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study","date_updated":"2025-11-20T12:46:44Z","publisher":"VDE Verlag","author":[{"first_name":"Kai Arne","last_name":"Hannemann","full_name":"Hannemann, Kai Arne","id":"63972"},{"last_name":"Bütün","full_name":"Bütün, Hüseyin Berke","first_name":"Hüseyin Berke"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"},{"first_name":"J. Christoph","full_name":"Scheytt, J. Christoph","id":"37144","last_name":"Scheytt","orcid":"0000-0002-5950-6618 "}],"date_created":"2025-02-26T14:33:18Z"},{"department":[{"_id":"58"}],"user_id":"16243","_id":"53579","language":[{"iso":"eng"}],"publication":"DATE 24 - Design Automation and Test in Europe","type":"conference","status":"public","date_created":"2024-04-18T20:25:23Z","author":[{"first_name":"Paul","last_name":"Palomero Bernardo","full_name":"Palomero Bernardo, Paul"},{"first_name":"Patrick","full_name":"Schmid, Patrick","last_name":"Schmid"},{"first_name":"Oliver","last_name":"Bringmann","full_name":"Bringmann, Oliver"},{"last_name":"Iftekhar","id":"47944","full_name":"Iftekhar, Mohammed","first_name":"Mohammed"},{"first_name":"Babak","id":"93634","full_name":"Sadiye, Babak","last_name":"Sadiye"},{"last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243","first_name":"Wolfgang"},{"last_name":"Koch","full_name":"Koch, Andreas","first_name":"Andreas"},{"last_name":"Jentsch","full_name":"Jentsch, Eyck","first_name":"Eyck"},{"first_name":"Axel","full_name":"Sauer, Axel","last_name":"Sauer"},{"full_name":"Feldner, Ingo","last_name":"Feldner","first_name":"Ingo"},{"last_name":"Ecker","full_name":"Ecker, Wolfgang","first_name":"Wolfgang"}],"date_updated":"2024-04-18T20:25:29Z","conference":{"location":"Valencia, Spain"},"title":"A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing","citation":{"chicago":"Palomero Bernardo, Paul, Patrick Schmid, Oliver Bringmann, Mohammed Iftekhar, Babak Sadiye, Wolfgang Müller, Andreas Koch, et al. “A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing.” In <i>DATE 24 - Design Automation and Test in Europe</i>, 2024.","ieee":"P. Palomero Bernardo <i>et al.</i>, “A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing,” Valencia, Spain, 2024.","ama":"Palomero Bernardo P, Schmid P, Bringmann O, et al. A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing. In: <i>DATE 24 - Design Automation and Test in Europe</i>. ; 2024.","apa":"Palomero Bernardo, P., Schmid, P., Bringmann, O., Iftekhar, M., Sadiye, B., Müller, W., Koch, A., Jentsch, E., Sauer, A., Feldner, I., &#38; Ecker, W. (2024). A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing. <i>DATE 24 - Design Automation and Test in Europe</i>.","short":"P. Palomero Bernardo, P. Schmid, O. Bringmann, M. Iftekhar, B. Sadiye, W. Müller, A. Koch, E. Jentsch, A. Sauer, I. Feldner, W. Ecker, in: DATE 24 - Design Automation and Test in Europe, 2024.","mla":"Palomero Bernardo, Paul, et al. “A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing.” <i>DATE 24 - Design Automation and Test in Europe</i>, 2024.","bibtex":"@inproceedings{Palomero Bernardo_Schmid_Bringmann_Iftekhar_Sadiye_Müller_Koch_Jentsch_Sauer_Feldner_et al._2024, title={A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing}, booktitle={DATE 24 - Design Automation and Test in Europe}, author={Palomero Bernardo, Paul and Schmid, Patrick and Bringmann, Oliver and Iftekhar, Mohammed and Sadiye, Babak and Müller, Wolfgang and Koch, Andreas and Jentsch, Eyck and Sauer, Axel and Feldner, Ingo and et al.}, year={2024} }"},"year":"2024"},{"publication":"MBMV 2024 - 27. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“","type":"conference","abstract":[{"lang":"eng","text":"RISC-V has received worldwide acceptance in the industry and by the academic community. As of today, multiple\r\nRISC-V applications and variants are under investigation for embedded IoT systems, from resource-limited single-core\r\nprocessors up to multi-core systems for High-Performance Computing (HPC). Recently, the Grid of Processing Cells\r\n(GPC) platform has been proposed as a scalable parallel grid-oriented network of processor cores with local memories.\r\nThis paper describes a prototype design of the GPC platform for hardware implementation at Register-Transfer Level\r\n(RTL) based on modified RISC-V Rocket processors with scratchpad memories. It introduces a scalable Chisel-based\r\nimplementation of the modified Rocket cores with RTL generation and a functional test using Verilator simulation. This\r\nwork also includes the adaptation of the Chipyard software toolchain to extend the compiler to multi-core grids with\r\ndifferent local address spaces."}],"status":"public","_id":"45778","department":[{"_id":"58"}],"user_id":"16243","language":[{"iso":"eng"}],"year":"2024","citation":{"mla":"Luchterhandt, Lars, et al. “Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells.” <i>MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“</i>, VDE Verlag, 2024.","bibtex":"@inproceedings{Luchterhandt_Nellius_Beck_Dömer_Kneuper_Müller_Sadiye_2024, title={Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells}, booktitle={MBMV 2024 - 27. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“}, publisher={VDE Verlag}, author={Luchterhandt, Lars and Nellius, Tom and Beck, Robert and Dömer, Rainer and Kneuper, Pascal and Müller, Wolfgang and Sadiye, Babak}, year={2024} }","short":"L. Luchterhandt, T. Nellius, R. Beck, R. Dömer, P. Kneuper, W. Müller, B. Sadiye, in: MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, VDE Verlag, 2024.","apa":"Luchterhandt, L., Nellius, T., Beck, R., Dömer, R., Kneuper, P., Müller, W., &#38; Sadiye, B. (2024). Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells. <i>MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“</i>. MBMV 2023 - 26. Workshop, Freiburg, , Germany,  Freiburg.","chicago":"Luchterhandt, Lars, Tom Nellius, Robert Beck, Rainer Dömer, Pascal Kneuper, Wolfgang Müller, and Babak Sadiye. “Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells.” In <i>MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“</i>. VDE Verlag, 2024.","ieee":"L. Luchterhandt <i>et al.</i>, “Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells,” presented at the MBMV 2023 - 26. Workshop, Freiburg, , Germany,  Freiburg, 2024.","ama":"Luchterhandt L, Nellius T, Beck R, et al. Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells. In: <i>MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“</i>. VDE Verlag; 2024."},"date_updated":"2025-02-24T10:40:29Z","publisher":"VDE Verlag","author":[{"last_name":"Luchterhandt","full_name":"Luchterhandt, Lars","first_name":"Lars"},{"last_name":"Nellius","full_name":"Nellius, Tom","first_name":"Tom"},{"first_name":"Robert","full_name":"Beck, Robert","last_name":"Beck"},{"full_name":"Dömer, Rainer","last_name":"Dömer","first_name":"Rainer"},{"first_name":"Pascal","id":"47367","full_name":"Kneuper, Pascal","last_name":"Kneuper"},{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"},{"id":"93634","full_name":"Sadiye, Babak","last_name":"Sadiye","first_name":"Babak"}],"date_created":"2023-06-26T12:32:07Z","title":"Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells","conference":{"start_date":"2023.03.23","name":"MBMV 2023 - 26. Workshop, Freiburg, ","location":"Germany,  Freiburg","end_date":"2023.03.24"}},{"status":"public","publication":"RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.","type":"conference","language":[{"iso":"eng"}],"department":[{"_id":"58"}],"user_id":"16243","_id":"45776","citation":{"short":"W. Ecker, M. Krstic, M. Ulbricht, A. Mauderer, E. Jentzsch, A. Koch, B. Koppelmann, W. Müller, B. Sadiye, N. Bruns, R. Drechsler, D. Müller-Gritschneder, J. Schlamelcher, K. Grüttner, J. Bormann, W. Kunz, R. Heckmann, G. Angst, R. Wimmer, B. Becker, T. Faller, P. Palomero Bernardo, O. Brinkmann, J. Partzsch, C. Mayr, in: RISC-V Summit Europe 2023, Barcelona, Spain, June 2023., 2023.","bibtex":"@inproceedings{Ecker_Krstic_Ulbricht_Mauderer_Jentzsch_Koch_Koppelmann_Müller_Sadiye_Bruns_et al._2023, title={Scale4Edge – Scaling RISC-V for Edge Applications}, booktitle={RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.}, author={Ecker, Wolfgang and Krstic, Milos and Ulbricht, Markus and Mauderer, Andreas and Jentzsch, Eyck and Koch, Andreas and Koppelmann, Bastian and Müller, Wolfgang and Sadiye, Babak and Bruns, Niklas and et al.}, year={2023} }","mla":"Ecker, Wolfgang, et al. “Scale4Edge – Scaling RISC-V for Edge Applications.” <i>RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.</i>, 2023.","apa":"Ecker, W., Krstic, M., Ulbricht, M., Mauderer, A., Jentzsch, E., Koch, A., Koppelmann, B., Müller, W., Sadiye, B., Bruns, N., Drechsler, R., Müller-Gritschneder, D., Schlamelcher, J., Grüttner, K., Bormann, J., Kunz, W., Heckmann, R., Angst, G., Wimmer, R., … Mayr, C. (2023). Scale4Edge – Scaling RISC-V for Edge Applications. <i>RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.</i> RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.,  Barcelona, Spain,.","ama":"Ecker W, Krstic M, Ulbricht M, et al. Scale4Edge – Scaling RISC-V for Edge Applications. In: <i>RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.</i> ; 2023.","chicago":"Ecker, Wolfgang, Milos Krstic, Markus Ulbricht, Andreas Mauderer, Eyck Jentzsch, Andreas Koch, Bastian Koppelmann, et al. “Scale4Edge – Scaling RISC-V for Edge Applications.” In <i>RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.</i>, 2023.","ieee":"W. Ecker <i>et al.</i>, “Scale4Edge – Scaling RISC-V for Edge Applications,” presented at the RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.,  Barcelona, Spain, 2023."},"year":"2023","related_material":{"link":[{"url":"https://riscv-europe.org/media/proceedings/posters/2023-06-06-Wolfgang-ECKER-abstract.pdf","relation":"slides"},{"relation":"other","url":"https://riscv-europe.org/"}]},"conference":{"start_date":"2023.06.05","name":"RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.","location":" Barcelona, Spain,","end_date":"2023.06.09"},"title":"Scale4Edge – Scaling RISC-V for Edge Applications","date_created":"2023-06-26T12:16:36Z","author":[{"first_name":"Wolfgang","full_name":"Ecker, Wolfgang","last_name":"Ecker"},{"first_name":"Milos","full_name":"Krstic, Milos","last_name":"Krstic"},{"first_name":"Markus","full_name":"Ulbricht, Markus","last_name":"Ulbricht"},{"first_name":"Andreas","last_name":"Mauderer","full_name":"Mauderer, Andreas"},{"last_name":"Jentzsch","full_name":"Jentzsch, Eyck","first_name":"Eyck"},{"first_name":"Andreas","last_name":"Koch","full_name":"Koch, Andreas"},{"last_name":"Koppelmann","full_name":"Koppelmann, Bastian","id":"25260","first_name":"Bastian"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"},{"first_name":"Babak","last_name":"Sadiye","full_name":"Sadiye, Babak","id":"93634"},{"last_name":"Bruns","full_name":"Bruns, Niklas","first_name":"Niklas"},{"last_name":"Drechsler","full_name":"Drechsler, Rolf","first_name":"Rolf"},{"first_name":"Daniel","last_name":"Müller-Gritschneder","full_name":"Müller-Gritschneder, Daniel"},{"last_name":"Schlamelcher","full_name":"Schlamelcher, Jan","first_name":"Jan"},{"first_name":"Kim","last_name":"Grüttner","full_name":"Grüttner, Kim"},{"full_name":"Bormann, Jörg","last_name":"Bormann","first_name":"Jörg"},{"full_name":"Kunz, Wolfgang","last_name":"Kunz","first_name":"Wolfgang"},{"first_name":"Reinhold","last_name":"Heckmann","full_name":"Heckmann, Reinhold"},{"first_name":"Gerhard","last_name":"Angst","full_name":"Angst, Gerhard"},{"last_name":"Wimmer","full_name":"Wimmer, Ralf","first_name":"Ralf"},{"full_name":"Becker, Bernd","last_name":"Becker","first_name":"Bernd"},{"first_name":"Tobias","last_name":"Faller","full_name":"Faller, Tobias"},{"first_name":"Paul","full_name":"Palomero Bernardo, Paul","last_name":"Palomero Bernardo"},{"last_name":"Brinkmann","full_name":"Brinkmann, Oliver","first_name":"Oliver"},{"first_name":"Johannes","last_name":"Partzsch","full_name":"Partzsch, Johannes"},{"first_name":"Christian","last_name":"Mayr","full_name":"Mayr, Christian"}],"date_updated":"2024-04-18T20:07:44Z"},{"_id":"48530","user_id":"16243","department":[{"_id":"58"}],"language":[{"iso":"eng"}],"type":"conference","publication":"5. ITG / GMM / GI -Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen ","status":"public","date_updated":"2024-04-18T20:08:22Z","author":[{"last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243","first_name":"Wolfgang"},{"first_name":"Markus","full_name":"Ulbricht, Markus","last_name":"Ulbricht"},{"first_name":"Lu","full_name":"Li, Lu","last_name":"Li"},{"last_name":"Krstic","full_name":"Krstic, Milos","first_name":"Milos"}],"date_created":"2023-10-27T13:26:53Z","title":"Der TETRISC SoC - Ein resilientes Quad-Core System auf Pulpissimo-Basis","conference":{"name":"5. ITG / GMM / GI -Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen ","location":"Erfurt. Germany"},"year":"2023","citation":{"short":"W. Müller, M. Ulbricht, L. Li, M. Krstic, in: 5. ITG / GMM / GI -Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen , 2023.","mla":"Müller, Wolfgang, et al. “Der TETRISC SoC - Ein Resilientes Quad-Core System Auf Pulpissimo-Basis.” <i>5. ITG / GMM / GI -Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen </i>, 2023.","bibtex":"@inproceedings{Müller_Ulbricht_Li_Krstic_2023, title={Der TETRISC SoC - Ein resilientes Quad-Core System auf Pulpissimo-Basis}, booktitle={5. ITG / GMM / GI -Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen }, author={Müller, Wolfgang and Ulbricht, Markus and Li, Lu and Krstic, Milos}, year={2023} }","apa":"Müller, W., Ulbricht, M., Li, L., &#38; Krstic, M. (2023). Der TETRISC SoC - Ein resilientes Quad-Core System auf Pulpissimo-Basis. <i>5. ITG / GMM / GI -Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen </i>. 5. ITG / GMM / GI -Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen , Erfurt. Germany.","chicago":"Müller, Wolfgang, Markus Ulbricht, Lu Li, and Milos Krstic. “Der TETRISC SoC - Ein Resilientes Quad-Core System Auf Pulpissimo-Basis.” In <i>5. ITG / GMM / GI -Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen </i>, 2023.","ieee":"W. Müller, M. Ulbricht, L. Li, and M. Krstic, “Der TETRISC SoC - Ein resilientes Quad-Core System auf Pulpissimo-Basis,” presented at the 5. ITG / GMM / GI -Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen , Erfurt. Germany, 2023.","ama":"Müller W, Ulbricht M, Li L, Krstic M. Der TETRISC SoC - Ein resilientes Quad-Core System auf Pulpissimo-Basis. In: <i>5. ITG / GMM / GI -Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen </i>. ; 2023."}},{"_id":"48961","user_id":"15931","department":[{"_id":"58"}],"language":[{"iso":"eng"}],"type":"conference_abstract","publication":"2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","status":"public","date_updated":"2024-04-19T11:43:21Z","date_created":"2023-11-16T11:04:41Z","author":[{"last_name":"Iftekhar","full_name":"Iftekhar, Mohammed","id":"47944","first_name":"Mohammed"},{"first_name":"Harshan","full_name":"Gowda, Harshan","last_name":"Gowda"},{"first_name":"Pascal","id":"47367","full_name":"Kneuper, Pascal","last_name":"Kneuper"},{"id":"93634","full_name":"Sadiye, Babak","last_name":"Sadiye","first_name":"Babak"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"full_name":"Scheytt, Christoph","id":"37144","last_name":"Scheytt","orcid":"0000-0002-5950-6618 ","first_name":"Christoph"}],"title":"A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology","conference":{"location":"Monterey, CA, USA","end_date":"2023-10-18","start_date":"2023-10-16","name":"2023 IEEE BiCMOS und Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)"},"doi":"10.1109/BCICTS54660.2023.10310954","publication_identifier":{"eisbn":["979-8-3503-0764-1"]},"related_material":{"link":[{"url":"https://ieeexplore.ieee.org/document/10310954","relation":"confirmation"}]},"year":"2023","citation":{"chicago":"Iftekhar, Mohammed, Harshan Gowda, Pascal Kneuper, Babak Sadiye, Wolfgang Müller, and Christoph Scheytt. “A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 Nm FD-SOI CMOS Technology.” In <i>2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)</i>, 2023. <a href=\"https://doi.org/10.1109/BCICTS54660.2023.10310954\">https://doi.org/10.1109/BCICTS54660.2023.10310954</a>.","ieee":"M. Iftekhar, H. Gowda, P. Kneuper, B. Sadiye, W. Müller, and C. Scheytt, “A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology,” presented at the 2023 IEEE BiCMOS und Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), Monterey, CA, USA, 2023, doi: <a href=\"https://doi.org/10.1109/BCICTS54660.2023.10310954\">10.1109/BCICTS54660.2023.10310954</a>.","ama":"Iftekhar M, Gowda H, Kneuper P, Sadiye B, Müller W, Scheytt C. A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology. In: <i>2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)</i>. ; 2023. doi:<a href=\"https://doi.org/10.1109/BCICTS54660.2023.10310954\">10.1109/BCICTS54660.2023.10310954</a>","apa":"Iftekhar, M., Gowda, H., Kneuper, P., Sadiye, B., Müller, W., &#38; Scheytt, C. (2023). A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology. <i>2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)</i>. 2023 IEEE BiCMOS und Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), Monterey, CA, USA. <a href=\"https://doi.org/10.1109/BCICTS54660.2023.10310954\">https://doi.org/10.1109/BCICTS54660.2023.10310954</a>","mla":"Iftekhar, Mohammed, et al. “A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 Nm FD-SOI CMOS Technology.” <i>2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)</i>, 2023, doi:<a href=\"https://doi.org/10.1109/BCICTS54660.2023.10310954\">10.1109/BCICTS54660.2023.10310954</a>.","short":"M. Iftekhar, H. Gowda, P. Kneuper, B. Sadiye, W. Müller, C. Scheytt, in: 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2023.","bibtex":"@inproceedings{Iftekhar_Gowda_Kneuper_Sadiye_Müller_Scheytt_2023, title={A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology}, DOI={<a href=\"https://doi.org/10.1109/BCICTS54660.2023.10310954\">10.1109/BCICTS54660.2023.10310954</a>}, booktitle={2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)}, author={Iftekhar, Mohammed and Gowda, Harshan and Kneuper, Pascal and Sadiye, Babak and Müller, Wolfgang and Scheytt, Christoph}, year={2023} }"}},{"conference":{"name":"MBMV 2023, Freiburg","start_date":"2023.03.23","end_date":"2023.03.24","location":"Freiburg"},"title":"Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture","author":[{"last_name":"Luchterhandt","full_name":"Luchterhandt, Lars","first_name":"Lars"},{"full_name":"Nellius, Tom","last_name":"Nellius","first_name":"Tom"},{"first_name":"Robert","full_name":"Beck, Robert","last_name":"Beck"},{"first_name":"Rainer","last_name":"Dömer","full_name":"Dömer, Rainer"},{"last_name":"Kneuper","id":"47367","full_name":"Kneuper, Pascal","first_name":"Pascal"},{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"},{"full_name":"Sadiye, Babak","id":"93634","last_name":"Sadiye","first_name":"Babak"}],"date_created":"2023-06-26T11:47:42Z","date_updated":"2025-02-24T10:41:01Z","publisher":"VDE Verlag","citation":{"apa":"Luchterhandt, L., Nellius, T., Beck, R., Dömer, R., Kneuper, P., Müller, W., &#38; Sadiye, B. (2023). Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture. <i>MBMV 2023 - 26. Workshop \"Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg</i>. MBMV 2023, Freiburg, Freiburg.","short":"L. Luchterhandt, T. Nellius, R. Beck, R. Dömer, P. Kneuper, W. Müller, B. Sadiye, in: MBMV 2023 - 26. Workshop \"Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg, VDE Verlag, 2023.","mla":"Luchterhandt, Lars, et al. “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture.” <i>MBMV 2023 - 26. Workshop \"Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg</i>, VDE Verlag, 2023.","bibtex":"@inproceedings{Luchterhandt_Nellius_Beck_Dömer_Kneuper_Müller_Sadiye_2023, title={Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture}, booktitle={MBMV 2023 - 26. Workshop \"Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“, MBMV 2023, Freiburg}, publisher={VDE Verlag}, author={Luchterhandt, Lars and Nellius, Tom and Beck, Robert and Dömer, Rainer and Kneuper, Pascal and Müller, Wolfgang and Sadiye, Babak}, year={2023} }","ama":"Luchterhandt L, Nellius T, Beck R, et al. Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture. In: <i>MBMV 2023 - 26. Workshop \"Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg</i>. VDE Verlag; 2023.","chicago":"Luchterhandt, Lars, Tom Nellius, Robert Beck, Rainer Dömer, Pascal Kneuper, Wolfgang Müller, and Babak Sadiye. “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture.” In <i>MBMV 2023 - 26. Workshop \"Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg</i>. VDE Verlag, 2023.","ieee":"L. Luchterhandt <i>et al.</i>, “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture,” presented at the MBMV 2023, Freiburg, Freiburg, 2023."},"year":"2023","language":[{"iso":"eng"}],"user_id":"16243","_id":"45775","status":"public","abstract":[{"text":"RISC-V has received worldwide acceptance in the industry and by the academic community. As of today, multiple\r\nRISC-V applications and variants are under investigation for embedded IoT systems, from resource-limited single-core\r\nprocessors up to multi-core systems for High-Performance Computing (HPC). Recently, the Grid of Processing Cells\r\n(GPC) platform has been proposed as a scalable parallel grid-oriented network of processor cores with local memories.\r\nThis paper describes a prototype design of the GPC platform for hardware implementation at Register-Transfer Level\r\n(RTL) based on modified RISC-V Rocket processors with scratchpad memories. It introduces a scalable Chisel-based\r\nimplementation of the modified Rocket cores with RTL generation and a functional test using Verilator simulation. This\r\nwork also includes the adaptation of the Chipyard software toolchain to extend the compiler to multi-core grids with\r\ndifferent local address spaces.","lang":"eng"}],"publication":"MBMV 2023 - 26. Workshop \"Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“, MBMV 2023, Freiburg","type":"conference"},{"title":"A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology ","conference":{"start_date":"2023-10-15","location":"MONTEREY, CALIFORNIA, USA","end_date":"2023-10-18"},"date_updated":"2025-02-26T14:41:53Z","date_created":"2023-09-14T11:30:36Z","author":[{"full_name":"Iftekhar, Mohammed","id":"47944","last_name":"Iftekhar","first_name":"Mohammed"},{"full_name":"Nagaraju, Harshan","last_name":"Nagaraju","first_name":"Harshan"},{"first_name":"Pascal","full_name":"Kneuper, Pascal","id":"47367","last_name":"Kneuper"},{"full_name":"Sadiye, Babak","id":"93634","last_name":"Sadiye","first_name":"Babak"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"},{"full_name":"Scheytt, J. Christoph","id":"37144","orcid":"0000-0002-5950-6618 ","last_name":"Scheytt","first_name":"J. Christoph"}],"year":"2023","citation":{"mla":"Iftekhar, Mohammed, et al. “A 28-Gb/s 27.2 MW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 Nm FD-SOI CMOS Technology .” <i>BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium</i>, 2023.","bibtex":"@inproceedings{Iftekhar_Nagaraju_Kneuper_Sadiye_Müller_Scheytt_2023, title={A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology }, booktitle={BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium}, author={Iftekhar, Mohammed and Nagaraju, Harshan and Kneuper, Pascal and Sadiye, Babak and Müller, Wolfgang and Scheytt, J. Christoph}, year={2023} }","short":"M. Iftekhar, H. Nagaraju, P. Kneuper, B. Sadiye, W. Müller, J.C. Scheytt, in: BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2023.","apa":"Iftekhar, M., Nagaraju, H., Kneuper, P., Sadiye, B., Müller, W., &#38; Scheytt, J. C. (2023). A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology . <i>BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium</i>.","ama":"Iftekhar M, Nagaraju H, Kneuper P, Sadiye B, Müller W, Scheytt JC. A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology . In: <i>BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium</i>. ; 2023.","ieee":"M. Iftekhar, H. Nagaraju, P. Kneuper, B. Sadiye, W. Müller, and J. C. Scheytt, “A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology ,” MONTEREY, CALIFORNIA, USA, 2023.","chicago":"Iftekhar, Mohammed, Harshan Nagaraju, Pascal Kneuper, Babak Sadiye, Wolfgang Müller, and J. Christoph Scheytt. “A 28-Gb/s 27.2 MW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 Nm FD-SOI CMOS Technology .” In <i>BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium</i>, 2023."},"related_material":{"link":[{"url":"https://bcicts.org/","relation":"contains"}]},"language":[{"iso":"eng"}],"_id":"47064","user_id":"15931","department":[{"_id":"58"}],"status":"public","type":"conference_abstract","publication":"BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium"},{"department":[{"_id":"58"}],"user_id":"15931","_id":"29302","language":[{"iso":"eng"}],"publication":"In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022)","type":"conference","status":"public","abstract":[{"lang":"eng","text":"This paper introduces the project Scale4Edge. The project is focused on enabling an effective RISC-V ecosystem for optimization of edge applications. We describe the basic components of this ecosystem and introduce the envisioned\r\ndemonstrators, which will be used in their evaluation."}],"date_created":"2022-01-13T07:27:46Z","author":[{"first_name":"Wolfgang","last_name":"Ecker","full_name":"Ecker, Wolfgang"},{"id":"5603","full_name":"Adelt, Peer","last_name":"Adelt","first_name":"Peer"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"},{"first_name":"Reinhold","last_name":"Heckmann","full_name":"Heckmann, Reinhold"},{"full_name":"Krstic, Milos","last_name":"Krstic","first_name":"Milos"},{"full_name":"Herdt, Vladimir","last_name":"Herdt","first_name":"Vladimir"},{"last_name":"Drechsler","full_name":"Drechsler, Rolf","first_name":"Rolf"},{"full_name":"Angst, Gerhard","last_name":"Angst","first_name":"Gerhard"},{"first_name":"Ralf","last_name":"Wimmer","full_name":"Wimmer, Ralf"},{"full_name":"Mauderer, Andreas","last_name":"Mauderer","first_name":"Andreas"},{"last_name":"Stahl","full_name":"Stahl, Rafael","first_name":"Rafael"},{"last_name":"Emrich","full_name":"Emrich, Karsten","first_name":"Karsten"},{"full_name":"Mueller-Gritschneder, Daniel","last_name":"Mueller-Gritschneder","first_name":"Daniel"},{"first_name":"Bernd","last_name":"Becker","full_name":"Becker, Bernd"},{"first_name":"Philipp","last_name":"Scholl","full_name":"Scholl, Philipp"},{"first_name":"Eyck","last_name":"Jentzsch","full_name":"Jentzsch, Eyck"},{"first_name":"Jan","last_name":"Schlamelcher","full_name":"Schlamelcher, Jan"},{"full_name":"Grüttner, Kim","last_name":"Grüttner","first_name":"Kim"},{"first_name":"Paul Palomero","full_name":"Bernardo, Paul Palomero","last_name":"Bernardo"},{"last_name":"Brinkmann","full_name":"Brinkmann, Oliver","first_name":"Oliver"},{"full_name":"Damian, Mihaela","last_name":"Damian","first_name":"Mihaela"},{"first_name":"Julian","full_name":"Oppermann, Julian","last_name":"Oppermann"},{"first_name":"Andreas","full_name":"Koch, Andreas","last_name":"Koch"},{"full_name":"Bormann, Jörg","last_name":"Bormann","first_name":"Jörg"},{"first_name":"Johannes","last_name":"Partzsch","full_name":"Partzsch, Johannes"},{"first_name":"Christian","full_name":"Mayr, Christian","last_name":"Mayr"},{"first_name":"Wolfgang","full_name":"Kunz, Wolfgang","last_name":"Kunz"}],"date_updated":"2022-01-13T07:30:38Z","conference":{"start_date":"14.03.2022","end_date":"15.03.2022"},"title":"The Scale4Edge RISC-V Ecosystem","citation":{"chicago":"Ecker, Wolfgang, Peer Adelt, Wolfgang Müller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, et al. “The Scale4Edge RISC-V Ecosystem.” In <i>In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022)</i>, 2022.","ieee":"W. Ecker <i>et al.</i>, “The Scale4Edge RISC-V Ecosystem,” 2022.","ama":"Ecker W, Adelt P, Müller W, et al. The Scale4Edge RISC-V Ecosystem. In: <i>In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022)</i>. ; 2022.","apa":"Ecker, W., Adelt, P., Müller, W., Heckmann, R., Krstic, M., Herdt, V., Drechsler, R., Angst, G., Wimmer, R., Mauderer, A., Stahl, R., Emrich, K., Mueller-Gritschneder, D., Becker, B., Scholl, P., Jentzsch, E., Schlamelcher, J., Grüttner, K., Bernardo, P. P., … Kunz, W. (2022). The Scale4Edge RISC-V Ecosystem. <i>In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022)</i>.","bibtex":"@inproceedings{Ecker_Adelt_Müller_Heckmann_Krstic_Herdt_Drechsler_Angst_Wimmer_Mauderer_et al._2022, title={The Scale4Edge RISC-V Ecosystem}, booktitle={In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022)}, author={Ecker, Wolfgang and Adelt, Peer and Müller, Wolfgang and Heckmann, Reinhold and Krstic, Milos and Herdt, Vladimir and Drechsler, Rolf and Angst, Gerhard and Wimmer, Ralf and Mauderer, Andreas and et al.}, year={2022} }","short":"W. Ecker, P. Adelt, W. Müller, R. Heckmann, M. Krstic, V. Herdt, R. Drechsler, G. Angst, R. Wimmer, A. Mauderer, R. Stahl, K. Emrich, D. Mueller-Gritschneder, B. Becker, P. Scholl, E. Jentzsch, J. Schlamelcher, K. Grüttner, P.P. Bernardo, O. Brinkmann, M. Damian, J. Oppermann, A. Koch, J. Bormann, J. Partzsch, C. Mayr, W. Kunz, in: In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022), 2022.","mla":"Ecker, Wolfgang, et al. “The Scale4Edge RISC-V Ecosystem.” <i>In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022)</i>, 2022."},"year":"2022"},{"language":[{"iso":"eng"}],"_id":"32125","user_id":"5603","department":[{"_id":"58"}],"abstract":[{"lang":"eng","text":"Fault coverage analysis and fault simulation are well-established methods for the qualification of test vectors in hardware design. However, their role in virtual prototyping and the correlation to later steps in the design process need further investigation. We introduce a metric for RISC-V instruction and register coverage for binary software. The metric measures if RISC-V instruction types are executed and if GPRs, CSRs, and FPRs are accessed. The analysis is applied by the means of a virtual prototype which is based on an abstract instruction and register model with direct correspondence to their bit level representation. In this context, we analyzed three different openly available test suites: the RISC-V architectural testing framework, the RISC-V unit tests, and programs which are automatically generated by the RISC-V Torture test generator. We discuss their tradeoffs and show that by combining them to a unified test suite we can arrive at a 100% GPR and FPR register coverage and a 98.7% instruction type coverage."}],"status":"public","type":"conference","publication":"MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop","title":"Register and Instruction Coverage Analysis for Different RISC-V ISA Modules","conference":{"end_date":"2021-03-19","start_date":"2021-03-18"},"date_updated":"2022-06-23T11:54:16Z","publisher":"VDE","author":[{"first_name":"Peer","full_name":"Adelt, Peer","id":"5603","last_name":"Adelt"},{"full_name":"Koppelmann, Bastian","id":"25260","last_name":"Koppelmann","first_name":"Bastian"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"first_name":"Christoph","id":"37144","full_name":"Scheytt, Christoph","last_name":"Scheytt"}],"date_created":"2022-06-23T11:52:50Z","year":"2021","place":"Munich, DE","citation":{"apa":"Adelt, P., Koppelmann, B., Müller, W., &#38; Scheytt, C. (2021). Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>.","short":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, Munich, DE, 2021.","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Scheytt_2021, place={Munich, DE}, title={Register and Instruction Coverage Analysis for Different RISC-V ISA Modules}, booktitle={MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop}, publisher={VDE}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2021} }","mla":"Adelt, Peer, et al. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>, VDE, 2021.","ieee":"P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules,” 2021.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” In <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>. Munich, DE: VDE, 2021.","ama":"Adelt P, Koppelmann B, Müller W, Scheytt C. Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. In: <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>. VDE; 2021."},"publication_status":"published","publication_identifier":{"isbn":["978-3-8007-5500-4"]},"related_material":{"link":[{"url":"https://ieeexplore.ieee.org/document/9399723","relation":"confirmation"}]}},{"user_id":"5603","department":[{"_id":"58"}],"_id":"32132","language":[{"iso":"ger"}],"keyword":["QEMU","aiT","Zeitannotation","WCET"],"type":"conference","publication":"MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop","status":"public","abstract":[{"lang":"ger","text":"Die Werkzeugdemonstration des QEMU Timing Analyzers (QTA) stellt eine Erweiterung des quelloffenen CPU Emulators QEMU zur Simulation von Softwareprogrammen und deren Worst-Case Zeitverhaltens vor, das durch eine statische Zeitanalyse vorher aus dem Softwareprogramm extrahiert wurde. Der Ablauf der Analyse gliedert sich in mehrere Schritte: Zunächst wird für das zu simulierende Binärprogramm eine WCET-Analyse mit aiT durchgeführt. Im Preprocessing des aiT-Reports wird daraufhin ein WCET-annotierter Kontrollflussgraph erzeugt. Dabei entsprechen die Knoten im Kontrollflussgraph den aiT-Blöcken und die Kanten dem jeweiligen Worst-Case-Zeitverbrauch, um das Programm im aktuellen Ausführungskontext vom Quell- bis zum Zielblock laufen zu lassen. Nach dem Preprocessing werden Binärprogramm und der zuvor erzeugte, zeitannotierte Kontrollflussgraph von QEMU geladen und gemeinsam simuliert.\r\n\r\nDie Implementierung des QTA basiert auf der Standard TGI Plugin API (Tiny Code Generator Plugin API), die seit Ende 2019 mit QEMU V4.2 verfügbar ist. Dieses API erlaubt die Entwicklung von versionsunabhängigen QEMU-Erweiterungen. Die QEMU-QTA-Erweiterung wird zum Zeitpunkt der Werkzeugdemonstration inklusive des ait2qta-Preprozessors unter github.com im Quellcode frei verfügbar sein.\r\n\r\nDie Demonstration geht von einer existierenden aiT-Analyse eines für TriCore© kompilierten binären Softwareprograms aus, erläutert das Kontrollflusszwischenformat und zeigt die zeitannotierte Simulation der Software."}],"date_created":"2022-06-23T12:07:10Z","author":[{"id":"5603","full_name":"Adelt, Peer","last_name":"Adelt","first_name":"Peer"},{"last_name":"Koppelmann","full_name":"Koppelmann, Bastian","id":"25260","first_name":"Bastian"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"full_name":"Scheytt, Christoph","id":"37144","orcid":"https://orcid.org/0000-0002-5950-6618","last_name":"Scheytt","first_name":"Christoph"}],"publisher":"VDE","date_updated":"2022-12-06T13:24:44Z","conference":{"start_date":"2021-03-18","end_date":"2021-03-19"},"title":"QEMU zur Simulation von Worst-Case-Ausführungszeiten","publication_status":"published","citation":{"chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “QEMU zur Simulation von Worst-Case-Ausführungszeiten.” In <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>. Munich, DE: VDE, 2021.","ieee":"P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “QEMU zur Simulation von Worst-Case-Ausführungszeiten,” 2021.","ama":"Adelt P, Koppelmann B, Müller W, Scheytt C. QEMU zur Simulation von Worst-Case-Ausführungszeiten. In: <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>. VDE; 2021.","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Scheytt_2021, place={Munich, DE}, title={QEMU zur Simulation von Worst-Case-Ausführungszeiten}, booktitle={MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop}, publisher={VDE}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2021} }","mla":"Adelt, Peer, et al. “QEMU zur Simulation von Worst-Case-Ausführungszeiten.” <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>, VDE, 2021.","short":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, Munich, DE, 2021.","apa":"Adelt, P., Koppelmann, B., Müller, W., &#38; Scheytt, C. (2021). QEMU zur Simulation von Worst-Case-Ausführungszeiten. <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>."},"year":"2021","place":"Munich, DE"},{"language":[{"iso":"eng"}],"title":"Register and Instruction Coverage Analysis for Different RISC-V ISA Modules","date_created":"2021-09-09T08:30:03Z","user_id":"15931","author":[{"last_name":"Adelt","full_name":"Adelt, Peer","id":"5603","first_name":"Peer"},{"last_name":"Koppelmann","full_name":"Koppelmann, Bastian","id":"25260","first_name":"Bastian"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"},{"first_name":"Christoph","id":"37144","full_name":"Scheytt, Christoph","last_name":"Scheytt","orcid":"https://orcid.org/0000-0002-5950-6618"}],"department":[{"_id":"58"}],"date_updated":"2023-01-31T13:25:48Z","_id":"23992","citation":{"ama":"Adelt P, Koppelmann B, Müller W, Scheytt C. Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. In: <i>Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021)</i>. ; 2021.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” In <i>Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021)</i>, 2021.","ieee":"P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules,” 2021.","apa":"Adelt, P., Koppelmann, B., Müller, W., &#38; Scheytt, C. (2021). Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. <i>Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021)</i>.","short":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021), 2021.","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Scheytt_2021, title={Register and Instruction Coverage Analysis for Different RISC-V ISA Modules}, booktitle={Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2021)}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2021} }","mla":"Adelt, Peer, et al. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” <i>Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021)</i>, 2021."},"status":"public","year":"2021","type":"conference","publication":"Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2021)"},{"language":[{"iso":"eng"}],"_id":"24027","department":[{"_id":"58"}],"user_id":"15931","abstract":[{"lang":"eng","text":"Fault effect simulation is a well-established technique for the qualification of robust embedded software and hardware as required by different safety standards. Our article introduces a Virtual Prototype based approach for the fault analysis and fast simulation of a set of automatically generated and target compiled software programs. The approach scales to different RISC-V ISA standard subset configurations and is based on an instruction and hardware register coverage for automatic fault injections of permanent and transient bitflips. The analysis of each software binary evaluates its opcode type and register access coverage including the addressed memory space. Based on this information dedicated sets of fault injected hardware models, i.e., mutants, are generated. The simulation of all mutants conducted with the different binaries finally identifies the cases with a normal termination though executed on a faulty hardware model. They are identified as a subject for further investigations and improvements by the implementation of additional hardware or software safety countermeasures. Our final evaluation results with automatic C code generation, compilation, analysis, and simulation show that QEMU provides an adequate efficient platform, which also scales to more complex scenarios."}],"status":"public","publication":"MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop","type":"conference","title":"A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures","date_updated":"2022-01-06T06:56:06Z","date_created":"2021-09-09T11:50:19Z","author":[{"last_name":"Adelt","full_name":"Adelt, Peer","id":"5603","first_name":"Peer"},{"last_name":"Koppelmann","id":"25260","full_name":"Koppelmann, Bastian","first_name":"Bastian"},{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"},{"last_name":"Scheytt","id":"37144","full_name":"Scheytt, Christoph","first_name":"Christoph"}],"place":"Stuttgart, DE","year":"2020","citation":{"bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Scheytt_2020, place={Stuttgart, DE}, title={A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures}, booktitle={MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2020} }","short":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, Stuttgart, DE, 2020.","mla":"Adelt, Peer, et al. “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures.” <i>MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>, 2020.","apa":"Adelt, P., Koppelmann, B., Müller, W., &#38; Scheytt, C. (2020). A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures. <i>MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures.” In <i>MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>. Stuttgart, DE, 2020.","ieee":"P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures,” 2020.","ama":"Adelt P, Koppelmann B, Müller W, Scheytt C. A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures. In: <i>MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>. ; 2020."},"related_material":{"link":[{"relation":"confirmation","url":"https://ieeexplore.ieee.org/document/9094540"}]}},{"_id":"24058","department":[{"_id":"58"}],"user_id":"15931","language":[{"iso":"eng"}],"publication":"29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","type":"conference","abstract":[{"lang":"eng","text":"Embedded systems require a high energy efficiency in combination with an optimized performance. As such, Bit Manipulation Instructions (BMIs) were introduced for x86 and ARMv8 to improve the runtime efficiency and power dissipation of the compiled software for various applications. Though the RISC-V platform is meanwhile widely accepted for embedded systems application, its instruction set architecture (ISA) currently still supports only two basic BMIs.We introduce ten advanced BMIs for the RISC-V ISA and implemented them on Berkeley's Rocket CPU [1], which we synthesized for the Artix-7 FPGA and the TSMC 65nm cell library. Our RISC-V BMI definitions are based on an analysis and combination of existing x86 and ARMv8 BMIs. Our Rocket CPU hardware extensions show that RISC-V BMI extensions have no negative impact on the critical path of the execution pipeline. Our software evaluations show that we can, for example, expect a significant impact for time and power consuming cryptographic applications."}],"status":"public","date_updated":"2022-01-06T06:56:06Z","author":[{"first_name":"Bastian","last_name":"Koppelmann","full_name":"Koppelmann, Bastian","id":"25260"},{"first_name":"Peer","id":"5603","full_name":"Adelt, Peer","last_name":"Adelt"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"},{"first_name":"Christoph","id":"37144","full_name":"Scheytt, Christoph","last_name":"Scheytt"}],"date_created":"2021-09-09T12:26:14Z","title":"RISC-V Extensions for Bit Manipulation Instructions","conference":{"end_date":"2019.07.03","start_date":"2019.07.01"},"doi":"10.1109/PATMOS.2019.8862170","related_material":{"link":[{"url":"https://ieeexplore.ieee.org/document/8862170","relation":"confirmation"}]},"year":"2019","place":"Rhodos, Griechenland","citation":{"apa":"Koppelmann, B., Adelt, P., Müller, W., &#38; Scheytt, C. (2019). RISC-V Extensions for Bit Manipulation Instructions. <i>29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)</i>. <a href=\"https://doi.org/10.1109/PATMOS.2019.8862170\">https://doi.org/10.1109/PATMOS.2019.8862170</a>","short":"B. Koppelmann, P. Adelt, W. Müller, C. Scheytt, in: 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Rhodos, Griechenland, 2019.","mla":"Koppelmann, Bastian, et al. “RISC-V Extensions for Bit Manipulation Instructions.” <i>29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)</i>, 2019, doi:<a href=\"https://doi.org/10.1109/PATMOS.2019.8862170\">10.1109/PATMOS.2019.8862170</a>.","bibtex":"@inproceedings{Koppelmann_Adelt_Müller_Scheytt_2019, place={Rhodos, Griechenland}, title={RISC-V Extensions for Bit Manipulation Instructions}, DOI={<a href=\"https://doi.org/10.1109/PATMOS.2019.8862170\">10.1109/PATMOS.2019.8862170</a>}, booktitle={29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)}, author={Koppelmann, Bastian and Adelt, Peer and Müller, Wolfgang and Scheytt, Christoph}, year={2019} }","ama":"Koppelmann B, Adelt P, Müller W, Scheytt C. RISC-V Extensions for Bit Manipulation Instructions. In: <i>29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)</i>. ; 2019. doi:<a href=\"https://doi.org/10.1109/PATMOS.2019.8862170\">10.1109/PATMOS.2019.8862170</a>","chicago":"Koppelmann, Bastian, Peer Adelt, Wolfgang Müller, and Christoph Scheytt. “RISC-V Extensions for Bit Manipulation Instructions.” In <i>29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)</i>. Rhodos, Griechenland, 2019. <a href=\"https://doi.org/10.1109/PATMOS.2019.8862170\">https://doi.org/10.1109/PATMOS.2019.8862170</a>.","ieee":"B. Koppelmann, P. Adelt, W. Müller, and C. Scheytt, “RISC-V Extensions for Bit Manipulation Instructions,” 2019, doi: <a href=\"https://doi.org/10.1109/PATMOS.2019.8862170\">10.1109/PATMOS.2019.8862170</a>."}},{"citation":{"ama":"Adelt P, Koppelmann B, Müller W, Scheytt C. Analyse sicherheitskritischer Software für RISC-V Prozessoren. In: <i>MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019)</i>. ; 2019.","ieee":"P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Analyse sicherheitskritischer Software für RISC-V Prozessoren,” 2019.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “Analyse Sicherheitskritischer Software Für RISC-V Prozessoren.” In <i>MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019)</i>. Kaiserslautern, DE, 2019.","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Scheytt_2019, place={Kaiserslautern, DE}, title={Analyse sicherheitskritischer Software für RISC-V Prozessoren}, booktitle={MBMV 2019-22.Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2019)}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2019} }","mla":"Adelt, Peer, et al. “Analyse Sicherheitskritischer Software Für RISC-V Prozessoren.” <i>MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019)</i>, 2019.","short":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019), Kaiserslautern, DE, 2019.","apa":"Adelt, P., Koppelmann, B., Müller, W., &#38; Scheytt, C. (2019). Analyse sicherheitskritischer Software für RISC-V Prozessoren. <i>MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019)</i>."},"year":"2019","place":"Kaiserslautern, DE","related_material":{"link":[{"url":"https://www.vde-verlag.de/proceedings-de/454945007.html","relation":"confirmation"}]},"publication_identifier":{"isbn":["978-3-8007-4945-4"]},"conference":{"end_date":"2019.04.08","start_date":"2019.04.08"},"title":"Analyse sicherheitskritischer Software für RISC-V Prozessoren","author":[{"first_name":"Peer","last_name":"Adelt","id":"5603","full_name":"Adelt, Peer"},{"last_name":"Koppelmann","full_name":"Koppelmann, Bastian","id":"25260","first_name":"Bastian"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"},{"first_name":"Christoph","full_name":"Scheytt, Christoph","id":"37144","last_name":"Scheytt"}],"date_created":"2021-09-09T12:26:16Z","date_updated":"2022-01-06T06:56:06Z","status":"public","abstract":[{"lang":"ger","text":"In diesem Artikel stellen wir eine Methode zur nicht-invasiven dynamischen Speicher- und IO-Analyse mit QEMU für sicherheitskritische eingebettete Software für die RISC-V Befehlssatzarchitektur vor. Die Implementierung basiert auf einer Erweiterung des Tiny Code Generator (TCG) des quelloffenen CPU-Emulators QEMU um die dynamische Identifikation von Zugriffen auf Datenspeicher sowie auf an die CPU angeschlossene IO-Geräte. Wir demonstrieren die Funktionalität der Methode anhand eines Versuchsaufbaus, bei dem eine Schließsystemkontrolle mittels serieller UART-Schnittstelle an einen RISC-V-Prozessor angebunden ist. Dieses Szenario zeigt, dass ein unberechtigter Zugriff auf die UART-Schnittstelle frühzeitig aufgedeckt und ein Angriff auf eine Zugangskontrolle somit endeckt werden kann. "}],"type":"conference","publication":"MBMV 2019-22.Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2019)","language":[{"iso":"eng"}],"user_id":"15931","department":[{"_id":"58"}],"_id":"24060"},{"related_material":{"link":[{"url":"https://www.researchgate.net/publication/334258953_QEMU_for_Dynamic_Memory_Analysis_of_Security_Sensitive_Software","relation":"confirmation"}]},"citation":{"apa":"Adelt, P., Koppelmann, B., Müller, W., Scheytt, C., &#38; Driessen, B. (2019). QEMU for Dynamic Memory Analysis of Security Sensitive Software. <i> 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019</i>, 32–34.","short":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, B. Driessen, in:  2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019, Florence, Italy, 2019, pp. 32–34.","mla":"Adelt, Peer, et al. “QEMU for Dynamic Memory Analysis of Security Sensitive Software.” <i> 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019</i>, 2019, pp. 32–34.","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Scheytt_Driessen_2019, place={Florence, Italy}, title={QEMU for Dynamic Memory Analysis of Security Sensitive Software}, booktitle={ 2nd International Workshop on Embedded Software for Industrial IoT in conjunction with DATE 2019}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph and Driessen, Benedikt}, year={2019}, pages={32–34} }","ama":"Adelt P, Koppelmann B, Müller W, Scheytt C, Driessen B. QEMU for Dynamic Memory Analysis of Security Sensitive Software. In: <i> 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019</i>. ; 2019:32-34.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Christoph Scheytt, and Benedikt Driessen. “QEMU for Dynamic Memory Analysis of Security Sensitive Software.” In <i> 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019</i>, 32–34. Florence, Italy, 2019.","ieee":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, and B. Driessen, “QEMU for Dynamic Memory Analysis of Security Sensitive Software,” in <i> 2nd International Workshop on Embedded Software for Industrial IoT in conjunction with DATE 2019</i>, 2019, pp. 32–34."},"page":"32-34","year":"2019","place":"Florence, Italy","author":[{"first_name":"Peer","full_name":"Adelt, Peer","id":"5603","last_name":"Adelt"},{"last_name":"Koppelmann","id":"25260","full_name":"Koppelmann, Bastian","first_name":"Bastian"},{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"},{"first_name":"Christoph","last_name":"Scheytt","full_name":"Scheytt, Christoph","id":"37144"},{"last_name":"Driessen","full_name":"Driessen, Benedikt","first_name":"Benedikt"}],"date_created":"2021-09-09T12:26:18Z","date_updated":"2022-01-06T06:56:06Z","title":"QEMU for Dynamic Memory Analysis of Security Sensitive Software","type":"conference","publication":" 2nd International Workshop on Embedded Software for Industrial IoT in conjunction with DATE 2019","status":"public","user_id":"15931","department":[{"_id":"58"}],"_id":"24061","language":[{"iso":"eng"}]},{"related_material":{"link":[{"relation":"confirmation","url":"https://www.edacentrum.de/veranstaltungen/risc-v/2019/programm"}]},"citation":{"short":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, 2nd International Workshop on RISC-V Research Activities (Presentation) (2019).","mla":"Adelt, Peer, et al. “QEMU Support for RISC-V: Current State and Future Releases.” <i>2nd International Workshop on RISC-V Research Activities</i>, vol. (Presentation), 2019.","bibtex":"@article{Adelt_Koppelmann_Müller_Scheytt_2019, title={QEMU Support for RISC-V: Current State and Future Releases}, volume={(Presentation)}, journal={2nd International Workshop on RISC-V Research Activities}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2019} }","apa":"Adelt, P., Koppelmann, B., Müller, W., &#38; Scheytt, C. (2019). QEMU Support for RISC-V: Current State and Future Releases. <i>2nd International Workshop on RISC-V Research Activities</i>, <i>(Presentation)</i>.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “QEMU Support for RISC-V: Current State and Future Releases.” <i>2nd International Workshop on RISC-V Research Activities</i> (Presentation) (2019).","ieee":"P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “QEMU Support for RISC-V: Current State and Future Releases,” <i>2nd International Workshop on RISC-V Research Activities</i>, vol. (Presentation), 2019.","ama":"Adelt P, Koppelmann B, Müller W, Scheytt C. QEMU Support for RISC-V: Current State and Future Releases. <i>2nd International Workshop on RISC-V Research Activities</i>. 2019;(Presentation)."},"year":"2019","author":[{"full_name":"Adelt, Peer","id":"5603","last_name":"Adelt","first_name":"Peer"},{"first_name":"Bastian","id":"25260","full_name":"Koppelmann, Bastian","last_name":"Koppelmann"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"},{"last_name":"Scheytt","id":"37144","full_name":"Scheytt, Christoph","first_name":"Christoph"}],"date_created":"2021-09-09T12:26:20Z","volume":"(Presentation)","date_updated":"2022-01-06T06:56:06Z","title":"QEMU Support for RISC-V: Current State and Future Releases","type":"journal_article","publication":"2nd International Workshop on RISC-V Research Activities","status":"public","abstract":[{"lang":"eng","text":"It its current Version 3.1.0 QEMU supports RISC-V RV32GC and RV64GC software emulation in user and full system mode. We will first give an overview of the current state of the QEMU RISC-V implementation. Thereafter, we will present the DecodeTree tool, which will be available with the next QEMU release. DecodeTree is a code generator included in QEMU that can generate the program logic for extracting and decoding opcodes and operands from a formal instruction list of the target architecture. This enables the structured implementation of just-in-time compilations to guarantee that the QEMU implementation meets the ISA specification. As such, we completely replaced the existing RISC-V RV32GC and RV64GC implementations by DecodeTree generations in the next official QEMU release, which is expected in spring 2019. We will demonstrate the DecodeTree applications by the example of RISC-V ISA subset configurations."}],"user_id":"15931","department":[{"_id":"58"}],"_id":"24063","language":[{"iso":"eng"}]}]