[{"title":"A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology ","conference":{"start_date":"2023-10-15","end_date":"2023-10-18","location":"MONTEREY, CALIFORNIA, USA"},"date_updated":"2025-02-26T14:41:53Z","author":[{"first_name":"Mohammed","full_name":"Iftekhar, Mohammed","id":"47944","last_name":"Iftekhar"},{"full_name":"Nagaraju, Harshan","last_name":"Nagaraju","first_name":"Harshan"},{"first_name":"Pascal","last_name":"Kneuper","full_name":"Kneuper, Pascal","id":"47367"},{"first_name":"Babak","full_name":"Sadiye, Babak","id":"93634","last_name":"Sadiye"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"},{"first_name":"J. Christoph","full_name":"Scheytt, J. Christoph","id":"37144","orcid":"0000-0002-5950-6618 ","last_name":"Scheytt"}],"date_created":"2023-09-14T11:30:36Z","year":"2023","citation":{"short":"M. Iftekhar, H. Nagaraju, P. Kneuper, B. Sadiye, W. Müller, J.C. Scheytt, in: BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2023.","bibtex":"@inproceedings{Iftekhar_Nagaraju_Kneuper_Sadiye_Müller_Scheytt_2023, title={A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology }, booktitle={BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium}, author={Iftekhar, Mohammed and Nagaraju, Harshan and Kneuper, Pascal and Sadiye, Babak and Müller, Wolfgang and Scheytt, J. Christoph}, year={2023} }","mla":"Iftekhar, Mohammed, et al. “A 28-Gb/s 27.2 MW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 Nm FD-SOI CMOS Technology .” <i>BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium</i>, 2023.","apa":"Iftekhar, M., Nagaraju, H., Kneuper, P., Sadiye, B., Müller, W., &#38; Scheytt, J. C. (2023). A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology . <i>BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium</i>.","ama":"Iftekhar M, Nagaraju H, Kneuper P, Sadiye B, Müller W, Scheytt JC. A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology . In: <i>BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium</i>. ; 2023.","chicago":"Iftekhar, Mohammed, Harshan Nagaraju, Pascal Kneuper, Babak Sadiye, Wolfgang Müller, and J. Christoph Scheytt. “A 28-Gb/s 27.2 MW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 Nm FD-SOI CMOS Technology .” In <i>BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium</i>, 2023.","ieee":"M. Iftekhar, H. Nagaraju, P. Kneuper, B. Sadiye, W. Müller, and J. C. Scheytt, “A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology ,” MONTEREY, CALIFORNIA, USA, 2023."},"related_material":{"link":[{"relation":"contains","url":"https://bcicts.org/"}]},"language":[{"iso":"eng"}],"_id":"47064","department":[{"_id":"58"}],"user_id":"15931","status":"public","publication":"BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium","type":"conference_abstract"},{"year":"2022","citation":{"mla":"Ecker, Wolfgang, et al. “The Scale4Edge RISC-V Ecosystem.” <i>In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022)</i>, 2022.","bibtex":"@inproceedings{Ecker_Adelt_Müller_Heckmann_Krstic_Herdt_Drechsler_Angst_Wimmer_Mauderer_et al._2022, title={The Scale4Edge RISC-V Ecosystem}, booktitle={In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022)}, author={Ecker, Wolfgang and Adelt, Peer and Müller, Wolfgang and Heckmann, Reinhold and Krstic, Milos and Herdt, Vladimir and Drechsler, Rolf and Angst, Gerhard and Wimmer, Ralf and Mauderer, Andreas and et al.}, year={2022} }","short":"W. Ecker, P. Adelt, W. Müller, R. Heckmann, M. Krstic, V. Herdt, R. Drechsler, G. Angst, R. Wimmer, A. Mauderer, R. Stahl, K. Emrich, D. Mueller-Gritschneder, B. Becker, P. Scholl, E. Jentzsch, J. Schlamelcher, K. Grüttner, P.P. Bernardo, O. Brinkmann, M. Damian, J. Oppermann, A. Koch, J. Bormann, J. Partzsch, C. Mayr, W. Kunz, in: In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022), 2022.","apa":"Ecker, W., Adelt, P., Müller, W., Heckmann, R., Krstic, M., Herdt, V., Drechsler, R., Angst, G., Wimmer, R., Mauderer, A., Stahl, R., Emrich, K., Mueller-Gritschneder, D., Becker, B., Scholl, P., Jentzsch, E., Schlamelcher, J., Grüttner, K., Bernardo, P. P., … Kunz, W. (2022). The Scale4Edge RISC-V Ecosystem. <i>In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022)</i>.","chicago":"Ecker, Wolfgang, Peer Adelt, Wolfgang Müller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, et al. “The Scale4Edge RISC-V Ecosystem.” In <i>In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022)</i>, 2022.","ieee":"W. Ecker <i>et al.</i>, “The Scale4Edge RISC-V Ecosystem,” 2022.","ama":"Ecker W, Adelt P, Müller W, et al. The Scale4Edge RISC-V Ecosystem. In: <i>In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022)</i>. ; 2022."},"title":"The Scale4Edge RISC-V Ecosystem","conference":{"end_date":"15.03.2022","start_date":"14.03.2022"},"date_updated":"2022-01-13T07:30:38Z","date_created":"2022-01-13T07:27:46Z","author":[{"first_name":"Wolfgang","full_name":"Ecker, Wolfgang","last_name":"Ecker"},{"first_name":"Peer","id":"5603","full_name":"Adelt, Peer","last_name":"Adelt"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"},{"full_name":"Heckmann, Reinhold","last_name":"Heckmann","first_name":"Reinhold"},{"first_name":"Milos","last_name":"Krstic","full_name":"Krstic, Milos"},{"first_name":"Vladimir","full_name":"Herdt, Vladimir","last_name":"Herdt"},{"first_name":"Rolf","full_name":"Drechsler, Rolf","last_name":"Drechsler"},{"first_name":"Gerhard","last_name":"Angst","full_name":"Angst, Gerhard"},{"first_name":"Ralf","full_name":"Wimmer, Ralf","last_name":"Wimmer"},{"first_name":"Andreas","full_name":"Mauderer, Andreas","last_name":"Mauderer"},{"last_name":"Stahl","full_name":"Stahl, Rafael","first_name":"Rafael"},{"first_name":"Karsten","full_name":"Emrich, Karsten","last_name":"Emrich"},{"first_name":"Daniel","full_name":"Mueller-Gritschneder, Daniel","last_name":"Mueller-Gritschneder"},{"first_name":"Bernd","full_name":"Becker, Bernd","last_name":"Becker"},{"first_name":"Philipp","full_name":"Scholl, Philipp","last_name":"Scholl"},{"first_name":"Eyck","last_name":"Jentzsch","full_name":"Jentzsch, Eyck"},{"full_name":"Schlamelcher, Jan","last_name":"Schlamelcher","first_name":"Jan"},{"first_name":"Kim","full_name":"Grüttner, Kim","last_name":"Grüttner"},{"last_name":"Bernardo","full_name":"Bernardo, Paul Palomero","first_name":"Paul Palomero"},{"first_name":"Oliver","last_name":"Brinkmann","full_name":"Brinkmann, Oliver"},{"first_name":"Mihaela","last_name":"Damian","full_name":"Damian, Mihaela"},{"first_name":"Julian","full_name":"Oppermann, Julian","last_name":"Oppermann"},{"first_name":"Andreas","last_name":"Koch","full_name":"Koch, Andreas"},{"first_name":"Jörg","last_name":"Bormann","full_name":"Bormann, Jörg"},{"last_name":"Partzsch","full_name":"Partzsch, Johannes","first_name":"Johannes"},{"first_name":"Christian","full_name":"Mayr, Christian","last_name":"Mayr"},{"full_name":"Kunz, Wolfgang","last_name":"Kunz","first_name":"Wolfgang"}],"abstract":[{"text":"This paper introduces the project Scale4Edge. The project is focused on enabling an effective RISC-V ecosystem for optimization of edge applications. We describe the basic components of this ecosystem and introduce the envisioned\r\ndemonstrators, which will be used in their evaluation.","lang":"eng"}],"status":"public","publication":"In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022)","type":"conference","language":[{"iso":"eng"}],"_id":"29302","department":[{"_id":"58"}],"user_id":"15931"},{"publisher":"VDE","date_updated":"2022-06-23T11:54:16Z","date_created":"2022-06-23T11:52:50Z","author":[{"last_name":"Adelt","id":"5603","full_name":"Adelt, Peer","first_name":"Peer"},{"first_name":"Bastian","last_name":"Koppelmann","full_name":"Koppelmann, Bastian","id":"25260"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"full_name":"Scheytt, Christoph","id":"37144","last_name":"Scheytt","first_name":"Christoph"}],"title":"Register and Instruction Coverage Analysis for Different RISC-V ISA Modules","conference":{"start_date":"2021-03-18","end_date":"2021-03-19"},"publication_status":"published","publication_identifier":{"isbn":["978-3-8007-5500-4"]},"related_material":{"link":[{"url":"https://ieeexplore.ieee.org/document/9399723","relation":"confirmation"}]},"year":"2021","place":"Munich, DE","citation":{"apa":"Adelt, P., Koppelmann, B., Müller, W., &#38; Scheytt, C. (2021). Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>.","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Scheytt_2021, place={Munich, DE}, title={Register and Instruction Coverage Analysis for Different RISC-V ISA Modules}, booktitle={MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop}, publisher={VDE}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2021} }","mla":"Adelt, Peer, et al. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>, VDE, 2021.","short":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, Munich, DE, 2021.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” In <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>. Munich, DE: VDE, 2021.","ieee":"P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules,” 2021.","ama":"Adelt P, Koppelmann B, Müller W, Scheytt C. Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. In: <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>. VDE; 2021."},"_id":"32125","user_id":"5603","department":[{"_id":"58"}],"language":[{"iso":"eng"}],"type":"conference","publication":"MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop","abstract":[{"lang":"eng","text":"Fault coverage analysis and fault simulation are well-established methods for the qualification of test vectors in hardware design. However, their role in virtual prototyping and the correlation to later steps in the design process need further investigation. We introduce a metric for RISC-V instruction and register coverage for binary software. The metric measures if RISC-V instruction types are executed and if GPRs, CSRs, and FPRs are accessed. The analysis is applied by the means of a virtual prototype which is based on an abstract instruction and register model with direct correspondence to their bit level representation. In this context, we analyzed three different openly available test suites: the RISC-V architectural testing framework, the RISC-V unit tests, and programs which are automatically generated by the RISC-V Torture test generator. We discuss their tradeoffs and show that by combining them to a unified test suite we can arrive at a 100% GPR and FPR register coverage and a 98.7% instruction type coverage."}],"status":"public"},{"publication":"MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop","type":"conference","status":"public","abstract":[{"text":"Die Werkzeugdemonstration des QEMU Timing Analyzers (QTA) stellt eine Erweiterung des quelloffenen CPU Emulators QEMU zur Simulation von Softwareprogrammen und deren Worst-Case Zeitverhaltens vor, das durch eine statische Zeitanalyse vorher aus dem Softwareprogramm extrahiert wurde. Der Ablauf der Analyse gliedert sich in mehrere Schritte: Zunächst wird für das zu simulierende Binärprogramm eine WCET-Analyse mit aiT durchgeführt. Im Preprocessing des aiT-Reports wird daraufhin ein WCET-annotierter Kontrollflussgraph erzeugt. Dabei entsprechen die Knoten im Kontrollflussgraph den aiT-Blöcken und die Kanten dem jeweiligen Worst-Case-Zeitverbrauch, um das Programm im aktuellen Ausführungskontext vom Quell- bis zum Zielblock laufen zu lassen. Nach dem Preprocessing werden Binärprogramm und der zuvor erzeugte, zeitannotierte Kontrollflussgraph von QEMU geladen und gemeinsam simuliert.\r\n\r\nDie Implementierung des QTA basiert auf der Standard TGI Plugin API (Tiny Code Generator Plugin API), die seit Ende 2019 mit QEMU V4.2 verfügbar ist. Dieses API erlaubt die Entwicklung von versionsunabhängigen QEMU-Erweiterungen. Die QEMU-QTA-Erweiterung wird zum Zeitpunkt der Werkzeugdemonstration inklusive des ait2qta-Preprozessors unter github.com im Quellcode frei verfügbar sein.\r\n\r\nDie Demonstration geht von einer existierenden aiT-Analyse eines für TriCore© kompilierten binären Softwareprograms aus, erläutert das Kontrollflusszwischenformat und zeigt die zeitannotierte Simulation der Software.","lang":"ger"}],"department":[{"_id":"58"}],"user_id":"5603","_id":"32132","language":[{"iso":"ger"}],"keyword":["QEMU","aiT","Zeitannotation","WCET"],"publication_status":"published","citation":{"ieee":"P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “QEMU zur Simulation von Worst-Case-Ausführungszeiten,” 2021.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “QEMU zur Simulation von Worst-Case-Ausführungszeiten.” In <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>. Munich, DE: VDE, 2021.","ama":"Adelt P, Koppelmann B, Müller W, Scheytt C. QEMU zur Simulation von Worst-Case-Ausführungszeiten. In: <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>. VDE; 2021.","apa":"Adelt, P., Koppelmann, B., Müller, W., &#38; Scheytt, C. (2021). QEMU zur Simulation von Worst-Case-Ausführungszeiten. <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>.","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Scheytt_2021, place={Munich, DE}, title={QEMU zur Simulation von Worst-Case-Ausführungszeiten}, booktitle={MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop}, publisher={VDE}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2021} }","short":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, Munich, DE, 2021.","mla":"Adelt, Peer, et al. “QEMU zur Simulation von Worst-Case-Ausführungszeiten.” <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>, VDE, 2021."},"place":"Munich, DE","year":"2021","author":[{"last_name":"Adelt","id":"5603","full_name":"Adelt, Peer","first_name":"Peer"},{"full_name":"Koppelmann, Bastian","id":"25260","last_name":"Koppelmann","first_name":"Bastian"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"},{"orcid":"https://orcid.org/0000-0002-5950-6618","last_name":"Scheytt","full_name":"Scheytt, Christoph","id":"37144","first_name":"Christoph"}],"date_created":"2022-06-23T12:07:10Z","date_updated":"2022-12-06T13:24:44Z","publisher":"VDE","conference":{"start_date":"2021-03-18","end_date":"2021-03-19"},"title":"QEMU zur Simulation von Worst-Case-Ausführungszeiten"},{"date_created":"2021-09-09T08:30:03Z","user_id":"15931","author":[{"first_name":"Peer","id":"5603","full_name":"Adelt, Peer","last_name":"Adelt"},{"last_name":"Koppelmann","full_name":"Koppelmann, Bastian","id":"25260","first_name":"Bastian"},{"last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243","first_name":"Wolfgang"},{"first_name":"Christoph","orcid":"https://orcid.org/0000-0002-5950-6618","last_name":"Scheytt","id":"37144","full_name":"Scheytt, Christoph"}],"department":[{"_id":"58"}],"date_updated":"2023-01-31T13:25:48Z","_id":"23992","language":[{"iso":"eng"}],"title":"Register and Instruction Coverage Analysis for Different RISC-V ISA Modules","type":"conference","publication":"Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2021)","citation":{"chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” In <i>Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021)</i>, 2021.","ieee":"P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules,” 2021.","ama":"Adelt P, Koppelmann B, Müller W, Scheytt C. Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. In: <i>Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021)</i>. ; 2021.","mla":"Adelt, Peer, et al. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” <i>Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021)</i>, 2021.","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Scheytt_2021, title={Register and Instruction Coverage Analysis for Different RISC-V ISA Modules}, booktitle={Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2021)}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2021} }","short":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021), 2021.","apa":"Adelt, P., Koppelmann, B., Müller, W., &#38; Scheytt, C. (2021). Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. <i>Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021)</i>."},"status":"public","year":"2021"},{"publication":"MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop","type":"conference","abstract":[{"lang":"eng","text":"Fault effect simulation is a well-established technique for the qualification of robust embedded software and hardware as required by different safety standards. Our article introduces a Virtual Prototype based approach for the fault analysis and fast simulation of a set of automatically generated and target compiled software programs. The approach scales to different RISC-V ISA standard subset configurations and is based on an instruction and hardware register coverage for automatic fault injections of permanent and transient bitflips. The analysis of each software binary evaluates its opcode type and register access coverage including the addressed memory space. Based on this information dedicated sets of fault injected hardware models, i.e., mutants, are generated. The simulation of all mutants conducted with the different binaries finally identifies the cases with a normal termination though executed on a faulty hardware model. They are identified as a subject for further investigations and improvements by the implementation of additional hardware or software safety countermeasures. Our final evaluation results with automatic C code generation, compilation, analysis, and simulation show that QEMU provides an adequate efficient platform, which also scales to more complex scenarios."}],"status":"public","_id":"24027","department":[{"_id":"58"}],"user_id":"15931","language":[{"iso":"eng"}],"related_material":{"link":[{"relation":"confirmation","url":"https://ieeexplore.ieee.org/document/9094540"}]},"year":"2020","place":"Stuttgart, DE","citation":{"apa":"Adelt, P., Koppelmann, B., Müller, W., &#38; Scheytt, C. (2020). A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures. <i>MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>.","mla":"Adelt, Peer, et al. “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures.” <i>MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>, 2020.","short":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, Stuttgart, DE, 2020.","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Scheytt_2020, place={Stuttgart, DE}, title={A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures}, booktitle={MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2020} }","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures.” In <i>MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>. Stuttgart, DE, 2020.","ieee":"P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures,” 2020.","ama":"Adelt P, Koppelmann B, Müller W, Scheytt C. A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures. In: <i>MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>. ; 2020."},"date_updated":"2022-01-06T06:56:06Z","author":[{"last_name":"Adelt","id":"5603","full_name":"Adelt, Peer","first_name":"Peer"},{"full_name":"Koppelmann, Bastian","id":"25260","last_name":"Koppelmann","first_name":"Bastian"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"last_name":"Scheytt","full_name":"Scheytt, Christoph","id":"37144","first_name":"Christoph"}],"date_created":"2021-09-09T11:50:19Z","title":"A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures"},{"status":"public","abstract":[{"lang":"eng","text":"Embedded systems require a high energy efficiency in combination with an optimized performance. As such, Bit Manipulation Instructions (BMIs) were introduced for x86 and ARMv8 to improve the runtime efficiency and power dissipation of the compiled software for various applications. Though the RISC-V platform is meanwhile widely accepted for embedded systems application, its instruction set architecture (ISA) currently still supports only two basic BMIs.We introduce ten advanced BMIs for the RISC-V ISA and implemented them on Berkeley's Rocket CPU [1], which we synthesized for the Artix-7 FPGA and the TSMC 65nm cell library. Our RISC-V BMI definitions are based on an analysis and combination of existing x86 and ARMv8 BMIs. Our Rocket CPU hardware extensions show that RISC-V BMI extensions have no negative impact on the critical path of the execution pipeline. Our software evaluations show that we can, for example, expect a significant impact for time and power consuming cryptographic applications."}],"type":"conference","publication":"29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","language":[{"iso":"eng"}],"user_id":"15931","department":[{"_id":"58"}],"_id":"24058","citation":{"ieee":"B. Koppelmann, P. Adelt, W. Müller, and C. Scheytt, “RISC-V Extensions for Bit Manipulation Instructions,” 2019, doi: <a href=\"https://doi.org/10.1109/PATMOS.2019.8862170\">10.1109/PATMOS.2019.8862170</a>.","chicago":"Koppelmann, Bastian, Peer Adelt, Wolfgang Müller, and Christoph Scheytt. “RISC-V Extensions for Bit Manipulation Instructions.” In <i>29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)</i>. Rhodos, Griechenland, 2019. <a href=\"https://doi.org/10.1109/PATMOS.2019.8862170\">https://doi.org/10.1109/PATMOS.2019.8862170</a>.","ama":"Koppelmann B, Adelt P, Müller W, Scheytt C. RISC-V Extensions for Bit Manipulation Instructions. In: <i>29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)</i>. ; 2019. doi:<a href=\"https://doi.org/10.1109/PATMOS.2019.8862170\">10.1109/PATMOS.2019.8862170</a>","apa":"Koppelmann, B., Adelt, P., Müller, W., &#38; Scheytt, C. (2019). RISC-V Extensions for Bit Manipulation Instructions. <i>29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)</i>. <a href=\"https://doi.org/10.1109/PATMOS.2019.8862170\">https://doi.org/10.1109/PATMOS.2019.8862170</a>","short":"B. Koppelmann, P. Adelt, W. Müller, C. Scheytt, in: 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Rhodos, Griechenland, 2019.","bibtex":"@inproceedings{Koppelmann_Adelt_Müller_Scheytt_2019, place={Rhodos, Griechenland}, title={RISC-V Extensions for Bit Manipulation Instructions}, DOI={<a href=\"https://doi.org/10.1109/PATMOS.2019.8862170\">10.1109/PATMOS.2019.8862170</a>}, booktitle={29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)}, author={Koppelmann, Bastian and Adelt, Peer and Müller, Wolfgang and Scheytt, Christoph}, year={2019} }","mla":"Koppelmann, Bastian, et al. “RISC-V Extensions for Bit Manipulation Instructions.” <i>29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)</i>, 2019, doi:<a href=\"https://doi.org/10.1109/PATMOS.2019.8862170\">10.1109/PATMOS.2019.8862170</a>."},"year":"2019","place":"Rhodos, Griechenland","related_material":{"link":[{"relation":"confirmation","url":"https://ieeexplore.ieee.org/document/8862170"}]},"conference":{"end_date":"2019.07.03","start_date":"2019.07.01"},"doi":"10.1109/PATMOS.2019.8862170","title":"RISC-V Extensions for Bit Manipulation Instructions","date_created":"2021-09-09T12:26:14Z","author":[{"id":"25260","full_name":"Koppelmann, Bastian","last_name":"Koppelmann","first_name":"Bastian"},{"last_name":"Adelt","full_name":"Adelt, Peer","id":"5603","first_name":"Peer"},{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"},{"full_name":"Scheytt, Christoph","id":"37144","last_name":"Scheytt","first_name":"Christoph"}],"date_updated":"2022-01-06T06:56:06Z"},{"status":"public","abstract":[{"lang":"ger","text":"In diesem Artikel stellen wir eine Methode zur nicht-invasiven dynamischen Speicher- und IO-Analyse mit QEMU für sicherheitskritische eingebettete Software für die RISC-V Befehlssatzarchitektur vor. Die Implementierung basiert auf einer Erweiterung des Tiny Code Generator (TCG) des quelloffenen CPU-Emulators QEMU um die dynamische Identifikation von Zugriffen auf Datenspeicher sowie auf an die CPU angeschlossene IO-Geräte. Wir demonstrieren die Funktionalität der Methode anhand eines Versuchsaufbaus, bei dem eine Schließsystemkontrolle mittels serieller UART-Schnittstelle an einen RISC-V-Prozessor angebunden ist. Dieses Szenario zeigt, dass ein unberechtigter Zugriff auf die UART-Schnittstelle frühzeitig aufgedeckt und ein Angriff auf eine Zugangskontrolle somit endeckt werden kann. "}],"type":"conference","publication":"MBMV 2019-22.Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2019)","language":[{"iso":"eng"}],"user_id":"15931","department":[{"_id":"58"}],"_id":"24060","citation":{"ieee":"P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Analyse sicherheitskritischer Software für RISC-V Prozessoren,” 2019.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “Analyse Sicherheitskritischer Software Für RISC-V Prozessoren.” In <i>MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019)</i>. Kaiserslautern, DE, 2019.","ama":"Adelt P, Koppelmann B, Müller W, Scheytt C. Analyse sicherheitskritischer Software für RISC-V Prozessoren. In: <i>MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019)</i>. ; 2019.","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Scheytt_2019, place={Kaiserslautern, DE}, title={Analyse sicherheitskritischer Software für RISC-V Prozessoren}, booktitle={MBMV 2019-22.Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2019)}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2019} }","mla":"Adelt, Peer, et al. “Analyse Sicherheitskritischer Software Für RISC-V Prozessoren.” <i>MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019)</i>, 2019.","short":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019), Kaiserslautern, DE, 2019.","apa":"Adelt, P., Koppelmann, B., Müller, W., &#38; Scheytt, C. (2019). Analyse sicherheitskritischer Software für RISC-V Prozessoren. <i>MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019)</i>."},"place":"Kaiserslautern, DE","year":"2019","related_material":{"link":[{"url":"https://www.vde-verlag.de/proceedings-de/454945007.html","relation":"confirmation"}]},"publication_identifier":{"isbn":["978-3-8007-4945-4"]},"conference":{"end_date":"2019.04.08","start_date":"2019.04.08"},"title":"Analyse sicherheitskritischer Software für RISC-V Prozessoren","author":[{"last_name":"Adelt","full_name":"Adelt, Peer","id":"5603","first_name":"Peer"},{"last_name":"Koppelmann","id":"25260","full_name":"Koppelmann, Bastian","first_name":"Bastian"},{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"},{"full_name":"Scheytt, Christoph","id":"37144","last_name":"Scheytt","first_name":"Christoph"}],"date_created":"2021-09-09T12:26:16Z","date_updated":"2022-01-06T06:56:06Z"},{"language":[{"iso":"eng"}],"_id":"24061","user_id":"15931","department":[{"_id":"58"}],"status":"public","type":"conference","publication":" 2nd International Workshop on Embedded Software for Industrial IoT in conjunction with DATE 2019","title":"QEMU for Dynamic Memory Analysis of Security Sensitive Software","date_updated":"2022-01-06T06:56:06Z","date_created":"2021-09-09T12:26:18Z","author":[{"full_name":"Adelt, Peer","id":"5603","last_name":"Adelt","first_name":"Peer"},{"first_name":"Bastian","last_name":"Koppelmann","id":"25260","full_name":"Koppelmann, Bastian"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"first_name":"Christoph","last_name":"Scheytt","id":"37144","full_name":"Scheytt, Christoph"},{"last_name":"Driessen","full_name":"Driessen, Benedikt","first_name":"Benedikt"}],"year":"2019","place":"Florence, Italy","citation":{"chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Christoph Scheytt, and Benedikt Driessen. “QEMU for Dynamic Memory Analysis of Security Sensitive Software.” In <i> 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019</i>, 32–34. Florence, Italy, 2019.","ieee":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, and B. Driessen, “QEMU for Dynamic Memory Analysis of Security Sensitive Software,” in <i> 2nd International Workshop on Embedded Software for Industrial IoT in conjunction with DATE 2019</i>, 2019, pp. 32–34.","ama":"Adelt P, Koppelmann B, Müller W, Scheytt C, Driessen B. QEMU for Dynamic Memory Analysis of Security Sensitive Software. In: <i> 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019</i>. ; 2019:32-34.","apa":"Adelt, P., Koppelmann, B., Müller, W., Scheytt, C., &#38; Driessen, B. (2019). QEMU for Dynamic Memory Analysis of Security Sensitive Software. <i> 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019</i>, 32–34.","short":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, B. Driessen, in:  2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019, Florence, Italy, 2019, pp. 32–34.","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Scheytt_Driessen_2019, place={Florence, Italy}, title={QEMU for Dynamic Memory Analysis of Security Sensitive Software}, booktitle={ 2nd International Workshop on Embedded Software for Industrial IoT in conjunction with DATE 2019}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph and Driessen, Benedikt}, year={2019}, pages={32–34} }","mla":"Adelt, Peer, et al. “QEMU for Dynamic Memory Analysis of Security Sensitive Software.” <i> 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019</i>, 2019, pp. 32–34."},"page":"32-34","related_material":{"link":[{"relation":"confirmation","url":"https://www.researchgate.net/publication/334258953_QEMU_for_Dynamic_Memory_Analysis_of_Security_Sensitive_Software"}]}},{"language":[{"iso":"eng"}],"_id":"24063","user_id":"15931","department":[{"_id":"58"}],"abstract":[{"text":"It its current Version 3.1.0 QEMU supports RISC-V RV32GC and RV64GC software emulation in user and full system mode. We will first give an overview of the current state of the QEMU RISC-V implementation. Thereafter, we will present the DecodeTree tool, which will be available with the next QEMU release. DecodeTree is a code generator included in QEMU that can generate the program logic for extracting and decoding opcodes and operands from a formal instruction list of the target architecture. This enables the structured implementation of just-in-time compilations to guarantee that the QEMU implementation meets the ISA specification. As such, we completely replaced the existing RISC-V RV32GC and RV64GC implementations by DecodeTree generations in the next official QEMU release, which is expected in spring 2019. We will demonstrate the DecodeTree applications by the example of RISC-V ISA subset configurations.","lang":"eng"}],"status":"public","type":"journal_article","publication":"2nd International Workshop on RISC-V Research Activities","title":"QEMU Support for RISC-V: Current State and Future Releases","date_updated":"2022-01-06T06:56:06Z","author":[{"last_name":"Adelt","full_name":"Adelt, Peer","id":"5603","first_name":"Peer"},{"first_name":"Bastian","full_name":"Koppelmann, Bastian","id":"25260","last_name":"Koppelmann"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"first_name":"Christoph","last_name":"Scheytt","id":"37144","full_name":"Scheytt, Christoph"}],"date_created":"2021-09-09T12:26:20Z","volume":"(Presentation)","year":"2019","citation":{"short":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, 2nd International Workshop on RISC-V Research Activities (Presentation) (2019).","mla":"Adelt, Peer, et al. “QEMU Support for RISC-V: Current State and Future Releases.” <i>2nd International Workshop on RISC-V Research Activities</i>, vol. (Presentation), 2019.","bibtex":"@article{Adelt_Koppelmann_Müller_Scheytt_2019, title={QEMU Support for RISC-V: Current State and Future Releases}, volume={(Presentation)}, journal={2nd International Workshop on RISC-V Research Activities}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2019} }","apa":"Adelt, P., Koppelmann, B., Müller, W., &#38; Scheytt, C. (2019). QEMU Support for RISC-V: Current State and Future Releases. <i>2nd International Workshop on RISC-V Research Activities</i>, <i>(Presentation)</i>.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “QEMU Support for RISC-V: Current State and Future Releases.” <i>2nd International Workshop on RISC-V Research Activities</i> (Presentation) (2019).","ieee":"P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “QEMU Support for RISC-V: Current State and Future Releases,” <i>2nd International Workshop on RISC-V Research Activities</i>, vol. (Presentation), 2019.","ama":"Adelt P, Koppelmann B, Müller W, Scheytt C. QEMU Support for RISC-V: Current State and Future Releases. <i>2nd International Workshop on RISC-V Research Activities</i>. 2019;(Presentation)."},"related_material":{"link":[{"relation":"confirmation","url":"https://www.edacentrum.de/veranstaltungen/risc-v/2019/programm"}]}},{"date_created":"2024-04-18T22:09:26Z","date_updated":"2024-04-18T22:09:33Z","title":"Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT","citation":{"chicago":"Bringmann, Oliver, Wolfgang Ecker, Wolfgang Müller, and Daniel Müller-Gridschneder, eds. <i>Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT</i>. Florence, Italy, 2019.","ieee":"O. Bringmann, W. Ecker, W. Müller, and D. Müller-Gridschneder, Eds., <i>Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT</i>. Florence, Italy, 2019.","ama":"Bringmann O, Ecker W, Müller W, Müller-Gridschneder D, eds. <i>Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT</i>.; 2019.","apa":"Bringmann, O., Ecker, W., Müller, W., &#38; Müller-Gridschneder, D. (Eds.). (2019). <i>Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT</i>.","bibtex":"@book{Bringmann_Ecker_Müller_Müller-Gridschneder_2019, place={Florence, Italy}, title={Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT}, year={2019} }","mla":"Bringmann, Oliver, et al., editors. <i>Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT</i>. 2019.","short":"O. Bringmann, W. Ecker, W. Müller, D. Müller-Gridschneder, eds., Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT, Florence, Italy, 2019."},"place":"Florence, Italy","year":"2019","user_id":"16243","department":[{"_id":"58"}],"_id":"53596","language":[{"iso":"eng"}],"type":"book_editor","status":"public","editor":[{"first_name":"Oliver","last_name":"Bringmann","full_name":"Bringmann, Oliver"},{"first_name":"Wolfgang","last_name":"Ecker","full_name":"Ecker, Wolfgang"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"full_name":"Müller-Gridschneder, Daniel","last_name":"Müller-Gridschneder","first_name":"Daniel"}]},{"date_created":"2021-09-13T07:38:01Z","author":[{"last_name":"Adelt","full_name":"Adelt, Peer","id":"5603","first_name":"Peer"},{"first_name":"Bastian","full_name":"Koppelmann, Bastian","id":"25260","last_name":"Koppelmann"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"}],"volume":"Presentation","date_updated":"2022-01-06T06:56:09Z","conference":{"location":"Munich, DE"},"title":"Current and Future RISC-V Activities for Virtual Prototyping and Chip Design","related_material":{"link":[{"url":"https://www.edacentrum.de/compact/current-and-future-risc-v-activities-virtual-prototyping-and-chip-design","relation":"confirmation"}]},"citation":{"mla":"Adelt, Peer, et al. “Current and Future RISC-V Activities for Virtual Prototyping and Chip Design.” <i>International Workshop on RISC-V Research Activities</i>, vol. Presentation, 2018.","bibtex":"@article{Adelt_Koppelmann_Müller_2018, title={Current and Future RISC-V Activities for Virtual Prototyping and Chip Design}, volume={Presentation}, journal={International Workshop on RISC-V Research Activities}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang}, year={2018} }","short":"P. Adelt, B. Koppelmann, W. Müller, International Workshop on RISC-V Research Activities Presentation (2018).","apa":"Adelt, P., Koppelmann, B., &#38; Müller, W. (2018). Current and Future RISC-V Activities for Virtual Prototyping and Chip Design. <i>International Workshop on RISC-V Research Activities</i>, <i>Presentation</i>.","ama":"Adelt P, Koppelmann B, Müller W. Current and Future RISC-V Activities for Virtual Prototyping and Chip Design. <i>International Workshop on RISC-V Research Activities</i>. 2018;Presentation.","chicago":"Adelt, Peer, Bastian Koppelmann, and Wolfgang Müller. “Current and Future RISC-V Activities for Virtual Prototyping and Chip Design.” <i>International Workshop on RISC-V Research Activities</i> Presentation (2018).","ieee":"P. Adelt, B. Koppelmann, and W. Müller, “Current and Future RISC-V Activities for Virtual Prototyping and Chip Design,” <i>International Workshop on RISC-V Research Activities</i>, vol. Presentation, 2018."},"year":"2018","user_id":"15931","department":[{"_id":"58"}],"_id":"24194","language":[{"iso":"eng"}],"type":"journal_article","publication":"International Workshop on RISC-V Research Activities","status":"public"},{"related_material":{"link":[{"url":"https://ieeexplore.ieee.org/document/8368549","relation":"confirmation"}]},"citation":{"ama":"Wu L, Hussain MK, Abughannam S, Müller W, Scheytt C, Ecker W. Analog fault simulation automation at schematic level with random sampling techniques. In: <i>2018 13th International Conference on Design &#38; Technology of Integrated Systems In Nanoscale Era (DTIS)) </i>. IEEE; 2018. doi:<a href=\"https://doi.org/10.1109/DTIS.2018.8368549\">10.1109/DTIS.2018.8368549</a>","chicago":"Wu, Liang, Mohammad Khizer Hussain, Saed Abughannam, Wolfgang Müller, Christoph Scheytt, and Wolfgang Ecker. “Analog Fault Simulation Automation at Schematic Level with Random Sampling Techniques.” In <i>2018 13th International Conference on Design &#38; Technology of Integrated Systems In Nanoscale Era (DTIS)) </i>. Italy/Taormina: IEEE, 2018. <a href=\"https://doi.org/10.1109/DTIS.2018.8368549\">https://doi.org/10.1109/DTIS.2018.8368549</a>.","ieee":"L. Wu, M. K. Hussain, S. Abughannam, W. Müller, C. Scheytt, and W. Ecker, “Analog fault simulation automation at schematic level with random sampling techniques,” 2018, doi: <a href=\"https://doi.org/10.1109/DTIS.2018.8368549\">10.1109/DTIS.2018.8368549</a>.","apa":"Wu, L., Hussain, M. K., Abughannam, S., Müller, W., Scheytt, C., &#38; Ecker, W. (2018). Analog fault simulation automation at schematic level with random sampling techniques. <i>2018 13th International Conference on Design &#38; Technology of Integrated Systems In Nanoscale Era (DTIS)) </i>. <a href=\"https://doi.org/10.1109/DTIS.2018.8368549\">https://doi.org/10.1109/DTIS.2018.8368549</a>","short":"L. Wu, M.K. Hussain, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in: 2018 13th International Conference on Design &#38; Technology of Integrated Systems In Nanoscale Era (DTIS)) , IEEE, Italy/Taormina, 2018.","bibtex":"@inproceedings{Wu_Hussain_Abughannam_Müller_Scheytt_Ecker_2018, place={Italy/Taormina}, title={Analog fault simulation automation at schematic level with random sampling techniques}, DOI={<a href=\"https://doi.org/10.1109/DTIS.2018.8368549\">10.1109/DTIS.2018.8368549</a>}, booktitle={2018 13th International Conference on Design &#38; Technology of Integrated Systems In Nanoscale Era (DTIS)) }, publisher={IEEE}, author={Wu, Liang and Hussain, Mohammad Khizer and Abughannam, Saed and Müller, Wolfgang and Scheytt, Christoph and Ecker, Wolfgang}, year={2018} }","mla":"Wu, Liang, et al. “Analog Fault Simulation Automation at Schematic Level with Random Sampling Techniques.” <i>2018 13th International Conference on Design &#38; Technology of Integrated Systems In Nanoscale Era (DTIS)) </i>, IEEE, 2018, doi:<a href=\"https://doi.org/10.1109/DTIS.2018.8368549\">10.1109/DTIS.2018.8368549</a>."},"place":"Italy/Taormina","year":"2018","date_created":"2021-09-13T07:38:03Z","author":[{"last_name":"Wu","id":"30401","full_name":"Wu, Liang","first_name":"Liang"},{"full_name":"Hussain, Mohammad Khizer","last_name":"Hussain","first_name":"Mohammad Khizer"},{"last_name":"Abughannam","full_name":"Abughannam, Saed","id":"37628","first_name":"Saed"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"first_name":"Christoph","id":"37144","full_name":"Scheytt, Christoph","last_name":"Scheytt"},{"last_name":"Ecker","full_name":"Ecker, Wolfgang","first_name":"Wolfgang"}],"publisher":"IEEE","date_updated":"2022-01-06T06:56:09Z","conference":{"start_date":"2018.04.09","end_date":"2018.04.12"},"doi":"10.1109/DTIS.2018.8368549","title":"Analog fault simulation automation at schematic level with random sampling techniques","type":"conference","publication":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)) ","status":"public","abstract":[{"lang":"eng","text":"This paper presents an approach for analog fault effect simulation automation based on random fault selection with a high fault coverage of the circuit under test by means of fault injection and simulation based on advanced sampling techniques. The random fault selection utilizes the likelihood of the fault occurrence of different electrical components in the circuit with a confidence level. Defect models of different devices are analyzed for the calculation of the fault probability. A case study with our implemented tool demonstrates that likelihood calculation and fault simulation provides means for efficient fault effect simulation automation."}],"user_id":"15931","department":[{"_id":"58"}],"_id":"24196","language":[{"iso":"eng"}]},{"date_created":"2024-04-18T22:03:47Z","date_updated":"2024-04-18T22:05:33Z","title":"Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT","citation":{"ieee":"O. Bringmann, W. Ecker, W. Müller, and D. Müller-Gridschneder, Eds., <i>Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT</i>. Dresden, Germany, 2018.","chicago":"Bringmann, Oliver, Wolfgang Ecker, Wolfgang Müller, and Daniel Müller-Gridschneder, eds. <i>Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT</i>. Dresden, Germany, 2018.","ama":"Bringmann O, Ecker W, Müller W, Müller-Gridschneder D, eds. <i>Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT</i>.; 2018.","mla":"Bringmann, Oliver, et al., editors. <i>Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT</i>. 2018.","bibtex":"@book{Bringmann_Ecker_Müller_Müller-Gridschneder_2018, place={Dresden, Germany}, title={Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT}, year={2018} }","short":"O. Bringmann, W. Ecker, W. Müller, D. Müller-Gridschneder, eds., Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT, Dresden, Germany, 2018.","apa":"Bringmann, O., Ecker, W., Müller, W., &#38; Müller-Gridschneder, D. (Eds.). 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Adelt, B. Koppelmann, W. Müller, D. Mueller-Gritschneder, B. Kleinjohann, C. Scheytt, in: Tagungsband des Wissenschaftsforums Intelligente Technische Systeme, Verlagsschriftenreihe des Heinz Nixdorf Instituts, Germany, Paderborn, 2017.","apa":"Adelt, P., Koppelmann, B., Müller, W., Mueller-Gritschneder, D., Kleinjohann, B., &#38; Scheytt, C. (2017). Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen. <i>Tagungsband des Wissenschaftsforums Intelligente Technische Systeme</i>. <a href=\"https://doi.org/10.17619/UNIPB/1-93\">https://doi.org/10.17619/UNIPB/1-93</a>","ieee":"P. Adelt, B. Koppelmann, W. Müller, D. Mueller-Gritschneder, B. Kleinjohann, and C. Scheytt, “Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen,” 2017, doi: <a href=\"https://doi.org/10.17619/UNIPB/1-93\">10.17619/UNIPB/1-93</a>.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Daniel Mueller-Gritschneder, Bernd Kleinjohann, and Christoph Scheytt. “Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen.” In <i>Tagungsband des Wissenschaftsforums Intelligente Technische Systeme</i>. Germany, Paderborn: Verlagsschriftenreihe des Heinz Nixdorf Instituts, 2017. <a href=\"https://doi.org/10.17619/UNIPB/1-93\">https://doi.org/10.17619/UNIPB/1-93</a>.","ama":"Adelt P, Koppelmann B, Müller W, Mueller-Gritschneder D, Kleinjohann B, Scheytt C. Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen. 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The parameters used in the docu-\r\nment to calculate the likelihood could be modi-\r\nfied by using more realistic data from the fab. \r\nWith the help of the fault simulator, the whole \r\ndesign flow of the fault effect simulation can be \r\nrealized automatically."}],"publication":"2nd Workshop on Resiliency in Embedded Electronic Systems (REES)","type":"conference","title":"SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study","author":[{"first_name":"Liang","last_name":"Wu","id":"30401","full_name":"Wu, Liang"},{"first_name":"Saed","last_name":"Abughannam","full_name":"Abughannam, Saed","id":"37628"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"id":"37144","full_name":"Scheytt, Christoph","last_name":"Scheytt","first_name":"Christoph"},{"first_name":"Wolfgang","last_name":"Ecker","full_name":"Ecker, Wolfgang"}],"date_created":"2021-09-13T08:20:39Z","date_updated":"2022-01-06T06:56:13Z","page":"68","citation":{"apa":"Wu, L., Abughannam, S., Müller, W., Scheytt, C., &#38; Ecker, W. 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Ecker, in: 2nd Workshop on Resiliency in Embedded Electronic Systems (REES), Lausanne, Switzerland, 2017, p. 68.","mla":"Wu, Liang, et al. “SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study.” <i>2nd Workshop on Resiliency in Embedded Electronic Systems (REES)</i>, 2017, p. 68.","chicago":"Wu, Liang, Saed Abughannam, Wolfgang Müller, Christoph Scheytt, and Wolfgang Ecker. “SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study.” In <i>2nd Workshop on Resiliency in Embedded Electronic Systems (REES)</i>, 68. Lausanne, Switzerland, 2017.","ieee":"L. Wu, S. Abughannam, W. Müller, C. Scheytt, and W. Ecker, “SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study,” in <i>2nd Workshop on Resiliency in Embedded Electronic Systems (REES)</i>, 2017, p. 68.","ama":"Wu L, Abughannam S, Müller W, Scheytt C, Ecker W. SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study. 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