[{"title":"A UML Profile for SysML-Based Comodeling for Embedded Systems Simulation and Synthesis","date_created":"2023-01-17T10:50:01Z","author":[{"last_name":"Mischkalla","full_name":"Mischkalla, Fabian","first_name":"Fabian"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"full_name":"He, Da","last_name":"He","first_name":"Da"}],"date_updated":"2023-01-17T10:50:10Z","citation":{"mla":"Mischkalla, Fabian, et al. “A UML Profile for SysML-Based Comodeling for Embedded Systems Simulation and Synthesis.” <i>Proceedings of the M-BED Workshop</i>, 2010.","short":"F. Mischkalla, W. Müller, D. He, in: Proceedings of the M-BED Workshop, Dresden, 2010.","bibtex":"@inproceedings{Mischkalla_Müller_He_2010, place={Dresden}, title={A UML Profile for SysML-Based Comodeling for Embedded Systems Simulation and Synthesis}, booktitle={Proceedings of the M-BED Workshop}, author={Mischkalla, Fabian and Müller, Wolfgang and He, Da}, year={2010} }","apa":"Mischkalla, F., Müller, W., &#38; He, D. (2010). A UML Profile for SysML-Based Comodeling for Embedded Systems Simulation and Synthesis. <i>Proceedings of the M-BED Workshop</i>.","ama":"Mischkalla F, Müller W, He D. A UML Profile for SysML-Based Comodeling for Embedded Systems Simulation and Synthesis. In: <i>Proceedings of the M-BED Workshop</i>. ; 2010.","chicago":"Mischkalla, Fabian, Wolfgang Müller, and Da He. “A UML Profile for SysML-Based Comodeling for Embedded Systems Simulation and Synthesis.” In <i>Proceedings of the M-BED Workshop</i>. Dresden, 2010.","ieee":"F. Mischkalla, W. Müller, and D. He, “A UML Profile for SysML-Based Comodeling for Embedded Systems Simulation and Synthesis,” 2010."},"year":"2010","place":"Dresden","language":[{"iso":"eng"}],"department":[{"_id":"672"}],"user_id":"5786","_id":"37042","status":"public","abstract":[{"text":"It's wide application in the area of software engineering, UML is still not fully accepted for other engineering domains like for electronic systems design. The main obstacle is due to a major gap in the design flow between UML-based modeling and verification. To overcome this gap, we introduce a UML profile for synthesizable SystemC and C and present its implementation in the context of the advanced SysML modeling environment of ARTiSAN Studio. We demonstrate how to customize Studio for SystemC/C comodeling so that it can serve as a verification and synthesis front-end.","lang":"eng"}],"publication":"Proceedings of the M-BED Workshop","type":"conference"},{"title":"Eine strukturierte Methode zur Generierung von SystemVerilog-Testumgebungen aus textuellen Anforderungsbeschreibungen","date_created":"2023-01-17T10:55:18Z","author":[{"first_name":"Alexander","full_name":"Bol, Alexander","last_name":"Bol"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"},{"full_name":"Krupp, Alexander","last_name":"Krupp","first_name":"Alexander"}],"date_updated":"2023-01-17T10:55:24Z","citation":{"mla":"Bol, Alexander, et al. “Eine Strukturierte Methode Zur Generierung von SystemVerilog-Testumgebungen Aus Textuellen Anforderungsbeschreibungen.” <i>Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV)</i>, 2010.","bibtex":"@inproceedings{Bol_Müller_Krupp_2010, place={Dresden}, title={Eine strukturierte Methode zur Generierung von SystemVerilog-Testumgebungen aus textuellen Anforderungsbeschreibungen}, booktitle={Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)}, author={Bol, Alexander and Müller, Wolfgang and Krupp, Alexander}, year={2010} }","short":"A. Bol, W. Müller, A. Krupp, in: Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV), Dresden, 2010.","apa":"Bol, A., Müller, W., &#38; Krupp, A. (2010). Eine strukturierte Methode zur Generierung von SystemVerilog-Testumgebungen aus textuellen Anforderungsbeschreibungen. <i>Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV)</i>.","ieee":"A. Bol, W. Müller, and A. Krupp, “Eine strukturierte Methode zur Generierung von SystemVerilog-Testumgebungen aus textuellen Anforderungsbeschreibungen,” 2010.","chicago":"Bol, Alexander, Wolfgang Müller, and Alexander Krupp. “Eine Strukturierte Methode Zur Generierung von SystemVerilog-Testumgebungen Aus Textuellen Anforderungsbeschreibungen.” In <i>Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV)</i>. Dresden, 2010.","ama":"Bol A, Müller W, Krupp A. Eine strukturierte Methode zur Generierung von SystemVerilog-Testumgebungen aus textuellen Anforderungsbeschreibungen. In: <i>Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV)</i>. ; 2010."},"year":"2010","place":"Dresden","language":[{"iso":"eng"}],"user_id":"5786","department":[{"_id":"672"}],"_id":"37043","status":"public","type":"conference","publication":"Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)"},{"title":"The SATURN Approach to SysML-based HW/SW Codesign","doi":"10.1007/978-94-007-1488-5_9","date_updated":"2023-01-17T11:19:53Z","date_created":"2023-01-17T11:19:45Z","author":[{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"first_name":"Da","last_name":"He","full_name":"He, Da"},{"last_name":"Mischkalla","full_name":"Mischkalla, Fabian","first_name":"Fabian"},{"first_name":"Arthur","full_name":"Wegele, Arthur","last_name":"Wegele"},{"last_name":"Larkham","full_name":"Larkham, Adrian","first_name":"Adrian"},{"full_name":"Whiston, Paul","last_name":"Whiston","first_name":"Paul"},{"last_name":"Penil","full_name":"Penil, Pablo","first_name":"Pablo"},{"first_name":"Eugenio","last_name":"Villar","full_name":"Villar, Eugenio"},{"full_name":"Mitas, Nikolaos","last_name":"Mitas","first_name":"Nikolaos"},{"last_name":"Kritharidis","full_name":"Kritharidis, Dimitros","first_name":"Dimitros"},{"full_name":"Azcarate, Florent","last_name":"Azcarate","first_name":"Florent"},{"first_name":"Manuel","last_name":"Carballeda","full_name":"Carballeda, Manuel"}],"year":"2010","citation":{"ieee":"W. Müller <i>et al.</i>, “The SATURN Approach to SysML-based HW/SW Codesign,” 2010, doi: <a href=\"https://doi.org/10.1007/978-94-007-1488-5_9\">10.1007/978-94-007-1488-5_9</a>.","chicago":"Müller, Wolfgang, Da He, Fabian Mischkalla, Arthur Wegele, Adrian Larkham, Paul Whiston, Pablo Penil, et al. “The SATURN Approach to SysML-Based HW/SW Codesign.” In <i>Proceedings of the IEEE Computer Society Annual Symposium on VLSI</i>. Lecture Notes in Electrical Engineering, 2010. <a href=\"https://doi.org/10.1007/978-94-007-1488-5_9\">https://doi.org/10.1007/978-94-007-1488-5_9</a>.","ama":"Müller W, He D, Mischkalla F, et al. The SATURN Approach to SysML-based HW/SW Codesign. In: <i>Proceedings of the IEEE Computer Society Annual Symposium on VLSI</i>. Lecture Notes in Electrical Engineering. ; 2010. doi:<a href=\"https://doi.org/10.1007/978-94-007-1488-5_9\">10.1007/978-94-007-1488-5_9</a>","mla":"Müller, Wolfgang, et al. “The SATURN Approach to SysML-Based HW/SW Codesign.” <i>Proceedings of the IEEE Computer Society Annual Symposium on VLSI</i>, 2010, doi:<a href=\"https://doi.org/10.1007/978-94-007-1488-5_9\">10.1007/978-94-007-1488-5_9</a>.","bibtex":"@inproceedings{Müller_He_Mischkalla_Wegele_Larkham_Whiston_Penil_Villar_Mitas_Kritharidis_et al._2010, series={Lecture Notes in Electrical Engineering}, title={The SATURN Approach to SysML-based HW/SW Codesign}, DOI={<a href=\"https://doi.org/10.1007/978-94-007-1488-5_9\">10.1007/978-94-007-1488-5_9</a>}, booktitle={Proceedings of the IEEE Computer Society Annual Symposium on VLSI}, author={Müller, Wolfgang and He, Da and Mischkalla, Fabian and Wegele, Arthur and Larkham, Adrian and Whiston, Paul and Penil, Pablo and Villar, Eugenio and Mitas, Nikolaos and Kritharidis, Dimitros and et al.}, year={2010}, collection={Lecture Notes in Electrical Engineering} }","short":"W. Müller, D. He, F. Mischkalla, A. Wegele, A. Larkham, P. Whiston, P. Penil, E. Villar, N. Mitas, D. Kritharidis, F. Azcarate, M. Carballeda, in: Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010.","apa":"Müller, W., He, D., Mischkalla, F., Wegele, A., Larkham, A., Whiston, P., Penil, P., Villar, E., Mitas, N., Kritharidis, D., Azcarate, F., &#38; Carballeda, M. (2010). The SATURN Approach to SysML-based HW/SW Codesign. <i>Proceedings of the IEEE Computer Society Annual Symposium on VLSI</i>. <a href=\"https://doi.org/10.1007/978-94-007-1488-5_9\">https://doi.org/10.1007/978-94-007-1488-5_9</a>"},"publication_identifier":{"eisbn":["978-94-007-1488-5"]},"keyword":["Communicate Sequential Process     Virtual Platform     Smart Camera     Synchronous Data Flow     Artisan Studio"],"language":[{"iso":"eng"}],"_id":"37050","department":[{"_id":"672"}],"user_id":"5786","series_title":"Lecture Notes in Electrical Engineering","abstract":[{"lang":"eng","text":"The main obstacle for the wide acceptance of UML and SysML in the design of electronic systems is due to a major gap in the design flow between UML-based modeling and SystemC-based verification. To overcome this gap, we present an approach developed in the SATURN project which introduces UML profiles for the co-modeling of SystemC and C with code generation support in the context of the SysML tool suite ARTiSAN Studio®. We finally discuss the evaluation of the approach by two case studies."}],"status":"public","publication":"Proceedings of the IEEE Computer Society Annual Symposium on VLSI","type":"conference"},{"publication_identifier":{"isbn":["978-3-642-15233-7"]},"place":"Dordrecht","year":"2010","citation":{"ama":"Müller W, Bol A, Krupp A, Lundkvist O. Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems. In: Kleinjohann L, Kleinjohann B, eds. Springer Verlag; 2010. doi:<a href=\"https://doi.org/10.1007/978-3-642-15234-4_9\">10.1007/978-3-642-15234-4_9</a>","ieee":"W. Müller, A. Bol, A. Krupp, and O. Lundkvist, “Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems,” 2010, doi: <a href=\"https://doi.org/10.1007/978-3-642-15234-4_9\">10.1007/978-3-642-15234-4_9</a>.","chicago":"Müller, Wolfgang, Alexander Bol, Alexander Krupp, and Ola Lundkvist. “Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems.” edited by L. Kleinjohann and B. Kleinjohann. Dordrecht: Springer Verlag, 2010. <a href=\"https://doi.org/10.1007/978-3-642-15234-4_9\">https://doi.org/10.1007/978-3-642-15234-4_9</a>.","apa":"Müller, W., Bol, A., Krupp, A., &#38; Lundkvist, O. (2010). <i>Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems</i> (L. Kleinjohann &#38; B. Kleinjohann, Eds.). Springer Verlag. <a href=\"https://doi.org/10.1007/978-3-642-15234-4_9\">https://doi.org/10.1007/978-3-642-15234-4_9</a>","short":"W. Müller, A. Bol, A. Krupp, O. Lundkvist, in: L. Kleinjohann, B. Kleinjohann (Eds.), Springer Verlag, Dordrecht, 2010.","mla":"Müller, Wolfgang, et al. <i>Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems</i>. Edited by L. Kleinjohann and B. Kleinjohann, Springer Verlag, 2010, doi:<a href=\"https://doi.org/10.1007/978-3-642-15234-4_9\">10.1007/978-3-642-15234-4_9</a>.","bibtex":"@inproceedings{Müller_Bol_Krupp_Lundkvist_2010, place={Dordrecht}, title={Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems}, DOI={<a href=\"https://doi.org/10.1007/978-3-642-15234-4_9\">10.1007/978-3-642-15234-4_9</a>}, publisher={Springer Verlag}, author={Müller, Wolfgang and Bol, Alexander and Krupp, Alexander and Lundkvist, Ola}, editor={Kleinjohann, L. and Kleinjohann, B.}, year={2010} }"},"date_updated":"2023-01-17T11:09:54Z","publisher":"Springer Verlag","author":[{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"},{"first_name":"Alexander","full_name":"Bol, Alexander","last_name":"Bol"},{"first_name":"Alexander","full_name":"Krupp, Alexander","last_name":"Krupp"},{"first_name":"Ola","last_name":"Lundkvist","full_name":"Lundkvist, Ola"}],"date_created":"2023-01-17T11:09:48Z","title":"Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems","doi":"10.1007/978-3-642-15234-4_9","conference":{"name":"IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES 2010)"},"type":"conference","editor":[{"first_name":"L.","last_name":"Kleinjohann","full_name":"Kleinjohann, L."},{"full_name":"Kleinjohann, B.","last_name":"Kleinjohann","first_name":"B."}],"abstract":[{"text":"We introduce a structured methodology for the generation of executable test environments from textual requirement specifications via UML class diagrams and the application of the classification tree methodology for embedded systems. The first phase is a stepwise transformation from unstructured English text into a textual normal form (TNF), which is automatically translated into UML class diagrams. After annotations of the class diagrams and the definition of test cases by sequence diagrams, both are converted into classification trees. From the classification trees we can finally generate SystemVerilog code. The methodology is introduced and evaluated by the example of an Adaptive Cruise Controller.","lang":"eng"}],"status":"public","_id":"37048","user_id":"5786","department":[{"_id":"672"}],"keyword":["Natural Language     UML     SystemVerilog     Testbenches"],"language":[{"iso":"eng"}]},{"editor":[{"last_name":"Kleinjohann","full_name":"Kleinjohann, L.","first_name":"L."},{"full_name":"Kleinjohann, B.","last_name":"Kleinjohann","first_name":"B."}],"status":"public","type":"conference","language":[{"iso":"eng"}],"_id":"37049","user_id":"5786","department":[{"_id":"672"}],"year":"2010","place":"Dordrecht","citation":{"apa":"Xie, T., Letombe, F., &#38; Müller, W. (2010). <i>Mutation-Analysis Directed Constrained Random Verification</i> (L. Kleinjohann &#38; B. Kleinjohann, Eds.). Springer Verlag.","short":"T. Xie, F. Letombe, W. Müller, in: L. Kleinjohann, B. Kleinjohann (Eds.), Springer Verlag, Dordrecht, 2010.","mla":"Xie, Tao, et al. <i>Mutation-Analysis Directed Constrained Random Verification</i>. Edited by L. Kleinjohann and B. Kleinjohann, Springer Verlag, 2010.","bibtex":"@inproceedings{Xie_Letombe_Müller_2010, place={Dordrecht}, title={Mutation-Analysis Directed Constrained Random Verification}, publisher={Springer Verlag}, author={Xie, Tao and Letombe, Florian and Müller, Wolfgang}, editor={Kleinjohann, L. and Kleinjohann, B.}, year={2010} }","ama":"Xie T, Letombe F, Müller W. Mutation-Analysis Directed Constrained Random Verification. In: Kleinjohann L, Kleinjohann B, eds. Springer Verlag; 2010.","chicago":"Xie, Tao, Florian Letombe, and Wolfgang Müller. “Mutation-Analysis Directed Constrained Random Verification.” edited by L. Kleinjohann and B. Kleinjohann. Dordrecht: Springer Verlag, 2010.","ieee":"T. Xie, F. Letombe, and W. Müller, “Mutation-Analysis Directed Constrained Random Verification,” 2010."},"title":"Mutation-Analysis Directed Constrained Random Verification","conference":{"name":"IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES 2010)"},"publisher":"Springer Verlag","date_updated":"2023-01-17T11:12:52Z","author":[{"first_name":"Tao","full_name":"Xie, Tao","last_name":"Xie"},{"first_name":"Florian","last_name":"Letombe","full_name":"Letombe, Florian"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"}],"date_created":"2023-01-17T11:11:51Z"},{"place":"Paris","year":"2010","citation":{"short":"T. Xie, G.B. Defo, W. Müller, in: Paris, 2010.","mla":"Xie, Tao, et al. <i>An Eclipse-Based Framework for the IP-XACT-Enabled Assembly of Mixed-Level IPs</i>. 2010.","bibtex":"@inproceedings{Xie_Defo_Müller_2010, place={Paris}, title={An Eclipse-based Framework for the IP-XACT-enabled Assembly of Mixed-Level IPs}, author={Xie, Tao and Defo, Gilles B. and Müller, Wolfgang}, year={2010} }","apa":"Xie, T., Defo, G. B., &#38; Müller, W. (2010). <i>An Eclipse-based Framework for the IP-XACT-enabled Assembly of Mixed-Level IPs</i>. First Workshop on Hands-on Platforms and tools for model-based engineering of Embedded Systems (HoPES 2010), Paris.","ieee":"T. Xie, G. B. Defo, and W. Müller, “An Eclipse-based Framework for the IP-XACT-enabled Assembly of Mixed-Level IPs,” presented at the First Workshop on Hands-on Platforms and tools for model-based engineering of Embedded Systems (HoPES 2010), Paris, 2010.","chicago":"Xie, Tao, Gilles B. Defo, and Wolfgang Müller. “An Eclipse-Based Framework for the IP-XACT-Enabled Assembly of Mixed-Level IPs.” Paris, 2010.","ama":"Xie T, Defo GB, Müller W. An Eclipse-based Framework for the IP-XACT-enabled Assembly of Mixed-Level IPs. In: ; 2010."},"title":"An Eclipse-based Framework for the IP-XACT-enabled Assembly of Mixed-Level IPs","conference":{"location":"Paris","name":"First Workshop on Hands-on Platforms and tools for model-based engineering of Embedded Systems (HoPES 2010)"},"date_updated":"2023-01-17T11:22:16Z","date_created":"2023-01-17T11:22:10Z","author":[{"first_name":"Tao","full_name":"Xie, Tao","last_name":"Xie"},{"first_name":"Gilles B.","last_name":"Defo","full_name":"Defo, Gilles B."},{"last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243","first_name":"Wolfgang"}],"status":"public","type":"conference","language":[{"iso":"eng"}],"_id":"37051","department":[{"_id":"672"}],"user_id":"5786"},{"citation":{"ieee":"G. B. Defo, W. Müller, and C. Kuznik, “Verification of a CAN Bus Model in SystemC with Functional Coverage,” presented at the International Symposium on Industrial Embedded System (SIES),  Trento, Italy, 2010, doi: <a href=\"https://doi.org/10.1109/SIES.2010.5551379\">10.1109/SIES.2010.5551379</a>.","chicago":"Defo, Gilles B., Wolfgang Müller, and Christoph Kuznik. “Verification of a CAN Bus Model in SystemC with Functional Coverage.” In <i>Proceedings of SIES 2010</i>.  Trento, Italy: IEEE, 2010. <a href=\"https://doi.org/10.1109/SIES.2010.5551379\">https://doi.org/10.1109/SIES.2010.5551379</a>.","ama":"Defo GB, Müller W, Kuznik C. Verification of a CAN Bus Model in SystemC with Functional Coverage. In: <i>Proceedings of SIES 2010</i>. IEEE; 2010. doi:<a href=\"https://doi.org/10.1109/SIES.2010.5551379\">10.1109/SIES.2010.5551379</a>","bibtex":"@inproceedings{Defo_Müller_Kuznik_2010, place={ Trento, Italy}, title={Verification of a CAN Bus Model in SystemC with Functional Coverage}, DOI={<a href=\"https://doi.org/10.1109/SIES.2010.5551379\">10.1109/SIES.2010.5551379</a>}, booktitle={Proceedings of SIES 2010}, publisher={IEEE}, author={Defo, Gilles B. and Müller, Wolfgang and Kuznik, Christoph}, year={2010} }","short":"G.B. Defo, W. Müller, C. Kuznik, in: Proceedings of SIES 2010, IEEE,  Trento, Italy, 2010.","mla":"Defo, Gilles B., et al. “Verification of a CAN Bus Model in SystemC with Functional Coverage.” <i>Proceedings of SIES 2010</i>, IEEE, 2010, doi:<a href=\"https://doi.org/10.1109/SIES.2010.5551379\">10.1109/SIES.2010.5551379</a>.","apa":"Defo, G. B., Müller, W., &#38; Kuznik, C. (2010). Verification of a CAN Bus Model in SystemC with Functional Coverage. <i>Proceedings of SIES 2010</i>. International Symposium on Industrial Embedded System (SIES),  Trento, Italy. <a href=\"https://doi.org/10.1109/SIES.2010.5551379\">https://doi.org/10.1109/SIES.2010.5551379</a>"},"year":"2010","place":" Trento, Italy","publication_identifier":{"eisbn":["978-1-4244-5841-7"]},"doi":"10.1109/SIES.2010.5551379","conference":{"location":" Trento, Italy","name":"International Symposium on Industrial Embedded System (SIES)"},"title":"Verification of a CAN Bus Model in SystemC with Functional Coverage","date_created":"2023-01-17T11:34:56Z","author":[{"full_name":"Defo, Gilles B.","last_name":"Defo","first_name":"Gilles B."},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"},{"first_name":"Christoph","full_name":"Kuznik, Christoph","last_name":"Kuznik"}],"date_updated":"2023-01-17T11:35:03Z","publisher":"IEEE","status":"public","abstract":[{"lang":"eng","text":"Many heterogeneous embedded systems, for example industrial automation and automotive applications, require hard-real time constraints to be exhaustively verified - which is a challenging task for the verification engineer. To cope with complexity, verification techniques working on different abstraction levels are best practice. SystemC is a versatile C++ based design and verification language, offering various mechanisms and constructs required for embedded systems modeling. Using the add-on SystemC Verification Library (SCV) elemental constrained-random stimuli techniques may be used for verification. However, SCV has several drawbacks such as lack of functional coverage. In this paper we present a functional coverage library that implements parts of the IEEE 1800-2005 SystemVerilog standard and allows capturing functional coverage throughout the design and verification process with SystemC. Moreover, we will demonstrate the usability of the approach with a case study working on a CAN bus model written in SystemC."}],"publication":"Proceedings of SIES 2010","type":"conference","language":[{"iso":"eng"}],"keyword":["Libraries","Generators","Transfer functions","Monitoring","Computational modeling","Driver circuits","Adaptation model"],"department":[{"_id":"672"}],"user_id":"5786","_id":"37057"},{"user_id":"5786","department":[{"_id":"672"}],"_id":"37056","language":[{"iso":"eng"}],"keyword":["Fault tolerant systems","Protocols","Redundancy","Runtime","Payloads","Schedules"],"type":"conference","publication":"Proceedings of SIES 2010","status":"public","abstract":[{"text":"In this paper we present an approach to increase the fault tolerance in FlexRay networks by introducing backup nodes to replace defect ECUs (Electronic Control Units). In order to reduce the memory requirements of such backup nodes, we distribute redundant tasks over different nodes and propose the distributed coordinated migration of tasks of the defect ECU to the backup node at runtime. This approach enhances our former work in, where we extended the FlexRay bus schedule by redundant slots to consider changes in the communication/slot assignment and investigated and evaluated different solutions to migrate the redundant tasks to the backup node using the static and/or dynamic segment of the communication cycle for transmissions. We present the approach of distributed coordination for migration and communication instead of additional dedicated coordinator nodes to further increase the fault tolerance. With this approach we improve the safety of FlexRay networks by avoiding a possible single point of failure due to a dedicated coordinator node also minimizing the necessary time needed for a reconfiguration after an ECU failure. Furthermore, we reduce the overhead within the communication and the demand for additional hardware components.","lang":"eng"}],"author":[{"last_name":"Klobedanz","full_name":"Klobedanz, Kay","first_name":"Kay"},{"first_name":"Gilles B.","full_name":"Defo, Gilles B.","last_name":"Defo"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"},{"last_name":"Kerstan","full_name":"Kerstan, Timo","first_name":"Timo"}],"date_created":"2023-01-17T11:31:38Z","date_updated":"2023-01-17T11:31:47Z","conference":{"name":"International Symposium on Industrial Embedded System (SIES)"},"doi":"10.1109/SIES.2010.5551384","title":"Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks","publication_identifier":{"eisbn":["978-1-4244-5841-7"]},"citation":{"chicago":"Klobedanz, Kay, Gilles B. Defo, Wolfgang Müller, and Timo Kerstan. “Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks.” In <i>Proceedings of SIES 2010</i>. Trento, Italien, 2010. <a href=\"https://doi.org/10.1109/SIES.2010.5551384\">https://doi.org/10.1109/SIES.2010.5551384</a>.","ieee":"K. Klobedanz, G. B. Defo, W. Müller, and T. Kerstan, “Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks,” presented at the International Symposium on Industrial Embedded System (SIES), 2010, doi: <a href=\"https://doi.org/10.1109/SIES.2010.5551384\">10.1109/SIES.2010.5551384</a>.","ama":"Klobedanz K, Defo GB, Müller W, Kerstan T. Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks. In: <i>Proceedings of SIES 2010</i>. ; 2010. doi:<a href=\"https://doi.org/10.1109/SIES.2010.5551384\">10.1109/SIES.2010.5551384</a>","apa":"Klobedanz, K., Defo, G. B., Müller, W., &#38; Kerstan, T. (2010). Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks. <i>Proceedings of SIES 2010</i>. International Symposium on Industrial Embedded System (SIES). <a href=\"https://doi.org/10.1109/SIES.2010.5551384\">https://doi.org/10.1109/SIES.2010.5551384</a>","mla":"Klobedanz, Kay, et al. “Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks.” <i>Proceedings of SIES 2010</i>, 2010, doi:<a href=\"https://doi.org/10.1109/SIES.2010.5551384\">10.1109/SIES.2010.5551384</a>.","bibtex":"@inproceedings{Klobedanz_Defo_Müller_Kerstan_2010, place={Trento, Italien}, title={Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks}, DOI={<a href=\"https://doi.org/10.1109/SIES.2010.5551384\">10.1109/SIES.2010.5551384</a>}, booktitle={Proceedings of SIES 2010}, author={Klobedanz, Kay and Defo, Gilles B. and Müller, Wolfgang and Kerstan, Timo}, year={2010} }","short":"K. Klobedanz, G.B. Defo, W. Müller, T. Kerstan, in: Proceedings of SIES 2010, Trento, Italien, 2010."},"place":"Trento, Italien","year":"2010"},{"type":"conference","publication":"Proceedings of HLDVT2010","abstract":[{"text":"Seamless HW/SW codesign flows support early verification of hardware and Hardware-dependent Software (HdS) like drivers, operating systems, and firmware. For early estimation and verification, the application of SystemC in combination with Instruction Set Simulators and Software Emulators like QEMU is widely accepted. In this article, we present an advanced design flow for HW, (RT)OS and HdS refinement and verification with focus on the transition from abstract RTOS verification to full system RTOS/HdS emulation. In the context of assertion-based verification, we introduce a set of generic real-time properties which can be reused and verified at different abstraction levels and discuss their application. The properties are presented by the means of IEEE standard PSL assertions which are applied for mixed SystemC/HdS models.","lang":"eng"}],"status":"public","_id":"37053","user_id":"5786","department":[{"_id":"672"}],"keyword":["Hardware","Microprogramming","Application software","Timing","Protocols","Virtual prototyping","Real time systems","Sampling methods","Operating systems","Emulation"],"language":[{"iso":"eng"}],"publication_identifier":{"eisbn":["978-1-4244-7806-4"]},"year":"2010","citation":{"short":"W. Müller, M.F. da S. Oliveira, H. Zabel, M. Becker, in: Proceedings of HLDVT2010, IEEE, 2010.","mla":"Müller, Wolfgang, et al. “Verification of Real-Time Properties for Hardware-Dependant Software.” <i>Proceedings of HLDVT2010</i>, IEEE, 2010.","bibtex":"@inproceedings{Müller_da S. Oliveira_Zabel_Becker_2010, title={Verification of Real-Time Properties for Hardware-Dependant Software}, booktitle={Proceedings of HLDVT2010}, publisher={IEEE}, author={Müller, Wolfgang and da S. Oliveira, Marcio F. and Zabel, Henning and Becker, Markus}, year={2010} }","apa":"Müller, W., da S. Oliveira, M. F., Zabel, H., &#38; Becker, M. (2010). Verification of Real-Time Properties for Hardware-Dependant Software. <i>Proceedings of HLDVT2010</i>. IEEE International High Level Design Validation and Test Workshop (HLDVT), Anaheim, FL, USA.","ama":"Müller W, da S. Oliveira MF, Zabel H, Becker M. Verification of Real-Time Properties for Hardware-Dependant Software. In: <i>Proceedings of HLDVT2010</i>. IEEE; 2010.","ieee":"W. Müller, M. F. da S. Oliveira, H. Zabel, and M. Becker, “Verification of Real-Time Properties for Hardware-Dependant Software,” presented at the IEEE International High Level Design Validation and Test Workshop (HLDVT), Anaheim, FL, USA, 2010.","chicago":"Müller, Wolfgang, Marcio F. da S. Oliveira, Henning Zabel, and Markus Becker. “Verification of Real-Time Properties for Hardware-Dependant Software.” In <i>Proceedings of HLDVT2010</i>. IEEE, 2010."},"date_updated":"2023-01-17T11:28:30Z","publisher":"IEEE","author":[{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"},{"last_name":"da S. Oliveira","full_name":"da S. Oliveira, Marcio F.","first_name":"Marcio F."},{"full_name":"Zabel, Henning","last_name":"Zabel","first_name":"Henning"},{"first_name":"Markus","full_name":"Becker, Markus","last_name":"Becker"}],"date_created":"2023-01-17T11:28:26Z","title":"Verification of Real-Time Properties for Hardware-Dependant Software","conference":{"name":"IEEE International High Level Design Validation and Test Workshop (HLDVT)","location":"Anaheim, FL, USA"}},{"title":"Design Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration","date_updated":"2023-01-17T11:37:44Z","date_created":"2023-01-17T11:37:39Z","author":[{"first_name":"Marcio F. S.","last_name":"Oliveira","full_name":"Oliveira, Marcio F. S."},{"last_name":"do Nascimento","full_name":"do Nascimento, Francisco Assis M.","first_name":"Francisco Assis M."},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"}],"place":"Antwerp, Belgium","year":"2010","citation":{"chicago":"Oliveira, Marcio F. S., Francisco Assis M. do Nascimento, and Wolfgang Müller. “Design Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration.” In <i>Proceedings of MoMPES 2010</i>. Antwerp, Belgium, 2010.","ieee":"M. F. S. Oliveira, F. A. M. do Nascimento, and W. Müller, “Design Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration,” 2010.","ama":"Oliveira MFS, do Nascimento FAM, Müller W. Design Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration. In: <i>Proceedings of MoMPES 2010</i>. ; 2010.","apa":"Oliveira, M. F. S., do Nascimento, F. A. M., &#38; Müller, W. (2010). Design Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration. <i>Proceedings of MoMPES 2010</i>.","bibtex":"@inproceedings{Oliveira_do Nascimento_Müller_2010, place={Antwerp, Belgium}, title={Design Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration}, booktitle={Proceedings of MoMPES 2010}, author={Oliveira, Marcio F. S. and do Nascimento, Francisco Assis M. and Müller, Wolfgang}, year={2010} }","mla":"Oliveira, Marcio F. S., et al. “Design Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration.” <i>Proceedings of MoMPES 2010</i>, 2010.","short":"M.F.S. Oliveira, F.A.M. do Nascimento, W. Müller, in: Proceedings of MoMPES 2010, Antwerp, Belgium, 2010."},"language":[{"iso":"eng"}],"_id":"37060","department":[{"_id":"672"}],"user_id":"5786","status":"public","publication":"Proceedings of MoMPES 2010","type":"conference"},{"date_created":"2023-01-17T10:44:46Z","author":[{"full_name":"Becker, Markus","last_name":"Becker","first_name":"Markus"},{"last_name":"Di Guglielmo","full_name":"Di Guglielmo, Giuseppe","first_name":"Giuseppe"},{"first_name":"Franco","last_name":"Fummi","full_name":"Fummi, Franco"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"first_name":"Graziano","full_name":"Pravadelli, Graziano","last_name":"Pravadelli"},{"full_name":"Xie, Tao","last_name":"Xie","first_name":"Tao"}],"date_updated":"2025-03-12T16:39:17Z","publisher":"IEEE","conference":{"location":"Dresden","name":"Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)"},"doi":"10.1109/DATE.2010.5456965","title":"RTOS-Aware Refinement for TLM2.0-based HW/SW Design","publication_identifier":{"eisbn":["978-3-9810801-6-2"]},"citation":{"apa":"Becker, M., Di Guglielmo, G., Fummi, F., Müller, W., Pravadelli, G., &#38; Xie, T. (2010). RTOS-Aware Refinement for TLM2.0-based HW/SW Design. <i>Proceedings of DATE’10</i>. Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden. <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">https://doi.org/10.1109/DATE.2010.5456965</a>","mla":"Becker, Markus, et al. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.” <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>.","short":"M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, T. Xie, in: Proceedings of DATE’10, IEEE, Dresden, 2010.","bibtex":"@inproceedings{Becker_Di Guglielmo_Fummi_Müller_Pravadelli_Xie_2010, place={Dresden}, title={RTOS-Aware Refinement for TLM2.0-based HW/SW Design}, DOI={<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>}, booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Becker, Markus and Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli, Graziano and Xie, Tao}, year={2010} }","ama":"Becker M, Di Guglielmo G, Fummi F, Müller W, Pravadelli G, Xie T. RTOS-Aware Refinement for TLM2.0-based HW/SW Design. In: <i>Proceedings of DATE’10</i>. IEEE; 2010. doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>","chicago":"Becker, Markus, Giuseppe Di Guglielmo, Franco Fummi, Wolfgang Müller, Graziano Pravadelli, and Tao Xie. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">https://doi.org/10.1109/DATE.2010.5456965</a>.","ieee":"M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, and T. Xie, “RTOS-Aware Refinement for TLM2.0-based HW/SW Design,” presented at the Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi: <a href=\"https://doi.org/10.1109/DATE.2010.5456965\">10.1109/DATE.2010.5456965</a>."},"place":"Dresden","year":"2010","user_id":"5786","_id":"37039","language":[{"iso":"eng"}],"keyword":["Timing","Hardware","Operating systems","Process design","Accuracy","Standards development","Context modeling","Real time systems","Communication channels","Microprogramming"],"type":"conference","publication":"Proceedings of DATE’10","status":"public","abstract":[{"lang":"eng","text":"Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms."}]},{"author":[{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"},{"first_name":"Alexander","full_name":"Bol, Alexander","last_name":"Bol"},{"first_name":"Alexander","full_name":"Krupp, Alexander","last_name":"Krupp"},{"first_name":"Ola","last_name":"Lundkvist","full_name":"Lundkvist, Ola"}],"date_created":"2023-01-17T11:05:55Z","date_updated":"2025-03-12T16:39:13Z","publisher":"Springer Verlag","conference":{"name":"IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES 2010)"},"doi":"10.1007/978-3-642-15234-4_9","title":"Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems","publication_identifier":{"isbn":["978-3-642-15233-7"]},"citation":{"mla":"Müller, Wolfgang, et al. <i>Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems</i>. Edited by L. Kleinjohann and B. Kleinjohann, Springer Verlag, 2010, doi:<a href=\"https://doi.org/10.1007/978-3-642-15234-4_9\">10.1007/978-3-642-15234-4_9</a>.","short":"W. Müller, A. Bol, A. Krupp, O. Lundkvist, in: L. Kleinjohann, B. Kleinjohann (Eds.), Springer Verlag, Dordrecht, 2010.","bibtex":"@inproceedings{Müller_Bol_Krupp_Lundkvist_2010, place={Dordrecht}, title={Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems}, DOI={<a href=\"https://doi.org/10.1007/978-3-642-15234-4_9\">10.1007/978-3-642-15234-4_9</a>}, publisher={Springer Verlag}, author={Müller, Wolfgang and Bol, Alexander and Krupp, Alexander and Lundkvist, Ola}, editor={Kleinjohann, L. and Kleinjohann, B.}, year={2010} }","apa":"Müller, W., Bol, A., Krupp, A., &#38; Lundkvist, O. (2010). <i>Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems</i> (L. Kleinjohann &#38; B. Kleinjohann, Eds.). Springer Verlag. <a href=\"https://doi.org/10.1007/978-3-642-15234-4_9\">https://doi.org/10.1007/978-3-642-15234-4_9</a>","ieee":"W. Müller, A. Bol, A. Krupp, and O. Lundkvist, “Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems,” 2010, doi: <a href=\"https://doi.org/10.1007/978-3-642-15234-4_9\">10.1007/978-3-642-15234-4_9</a>.","chicago":"Müller, Wolfgang, Alexander Bol, Alexander Krupp, and Ola Lundkvist. “Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems.” edited by L. Kleinjohann and B. Kleinjohann. Dordrecht: Springer Verlag, 2010. <a href=\"https://doi.org/10.1007/978-3-642-15234-4_9\">https://doi.org/10.1007/978-3-642-15234-4_9</a>.","ama":"Müller W, Bol A, Krupp A, Lundkvist O. Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems. In: Kleinjohann L, Kleinjohann B, eds. Springer Verlag; 2010. doi:<a href=\"https://doi.org/10.1007/978-3-642-15234-4_9\">10.1007/978-3-642-15234-4_9</a>"},"year":"2010","place":"Dordrecht","user_id":"5786","_id":"37047","language":[{"iso":"eng"}],"keyword":["Natural Language     UML     SystemVerilog     Testbenches"],"type":"conference","status":"public","abstract":[{"lang":"eng","text":"We introduce a structured methodology for the generation of executable test environments from textual requirement specifications via UML class diagrams and the application of the classification tree methodology for embedded systems. The first phase is a stepwise transformation from unstructured English text into a textual normal form (TNF), which is automatically translated into UML class diagrams. After annotations of the class diagrams and the definition of test cases by sequence diagrams, both are converted into classification trees. From the classification trees we can finally generate SystemVerilog code. The methodology is introduced and evaluated by the example of an Adaptive Cruise Controller."}],"editor":[{"full_name":"Kleinjohann, L.","last_name":"Kleinjohann","first_name":"L."},{"last_name":"Kleinjohann","full_name":"Kleinjohann, B.","first_name":"B."}]},{"publication_identifier":{"isbn":["978-1-4020-9435-4"]},"page":"233-260","citation":{"ama":"Zabel H, Müller W, Gerstlauer A. Accurate RTOS Modelling and Analysis with SystemC. In: Ecker W, Müller W, Dömer R, eds. <i>Hardware Dependent Software - Principles and Practice</i>. Springer Verlag; 2009:233-260. doi:<a href=\"https://doi.org/10.1007/978-1-4020-9436-1_9\">10.1007/978-1-4020-9436-1_9</a>","chicago":"Zabel, Henning, Wolfgang Müller, and Andreas Gerstlauer. “Accurate RTOS Modelling and Analysis with SystemC.” In <i>Hardware Dependent Software - Principles and Practice</i>, edited by Wolfgang Ecker, Wolfgang Müller, and Rainer Dömer, 233–60. Dordrecht: Springer Verlag, 2009. <a href=\"https://doi.org/10.1007/978-1-4020-9436-1_9\">https://doi.org/10.1007/978-1-4020-9436-1_9</a>.","ieee":"H. Zabel, W. Müller, and A. Gerstlauer, “Accurate RTOS Modelling and Analysis with SystemC,” in <i>Hardware Dependent Software - Principles and Practice</i>, W. Ecker, W. Müller, and R. Dömer, Eds. Dordrecht: Springer Verlag, 2009, pp. 233–260.","mla":"Zabel, Henning, et al. “Accurate RTOS Modelling and Analysis with SystemC.” <i>Hardware Dependent Software - Principles and Practice</i>, edited by Wolfgang Ecker et al., Springer Verlag, 2009, pp. 233–60, doi:<a href=\"https://doi.org/10.1007/978-1-4020-9436-1_9\">10.1007/978-1-4020-9436-1_9</a>.","bibtex":"@inbook{Zabel_Müller_Gerstlauer_2009, place={Dordrecht}, title={Accurate RTOS Modelling and Analysis with SystemC}, DOI={<a href=\"https://doi.org/10.1007/978-1-4020-9436-1_9\">10.1007/978-1-4020-9436-1_9</a>}, booktitle={Hardware Dependent Software - Principles and Practice}, publisher={Springer Verlag}, author={Zabel, Henning and Müller, Wolfgang and Gerstlauer, Andreas}, editor={Ecker, Wolfgang and Müller, Wolfgang and Dömer, Rainer}, year={2009}, pages={233–260} }","short":"H. Zabel, W. Müller, A. Gerstlauer, in: W. Ecker, W. Müller, R. Dömer (Eds.), Hardware Dependent Software - Principles and Practice, Springer Verlag, Dordrecht, 2009, pp. 233–260.","apa":"Zabel, H., Müller, W., &#38; Gerstlauer, A. (2009). Accurate RTOS Modelling and Analysis with SystemC. In W. Ecker, W. Müller, &#38; R. Dömer (Eds.), <i>Hardware Dependent Software - Principles and Practice</i> (pp. 233–260). Springer Verlag. <a href=\"https://doi.org/10.1007/978-1-4020-9436-1_9\">https://doi.org/10.1007/978-1-4020-9436-1_9</a>"},"place":"Dordrecht","year":"2009","author":[{"full_name":"Zabel, Henning","last_name":"Zabel","first_name":"Henning"},{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"},{"first_name":"Andreas","full_name":"Gerstlauer, Andreas","last_name":"Gerstlauer"}],"date_created":"2022-10-18T10:45:06Z","publisher":"Springer Verlag","date_updated":"2022-10-18T10:55:55Z","doi":"10.1007/978-1-4020-9436-1_9","title":"Accurate RTOS Modelling and Analysis with SystemC","publication":"Hardware Dependent Software - Principles and Practice","type":"book_chapter","status":"public","abstract":[{"text":"Today, mobile and embedded real-time systems have to cope with the migration\r\nand allocation of multiple software tasks running on top of a real-time operating\r\nsystem (RTOS) residing on one or several system processors. Each RTOS has to\r\nbe configured towards the individual needs of the application and environment.\r\nFor this, different scheduling strategies and task priorities have to be evaluated in\r\norder to keep execution and response times for a given task set. Abstract RTOS\r\nsimulation is applied to analyze different parameters in early design phases. This\r\nchapter presents a SystemC RTOS library for abstract yet accurate RTOS sim-\r\nulation, supporting modeling of preemption in the presence of prioritized and\r\nnested interrupts. After introducing basic principles of abstract RTOS simula-\r\ntion, we present our SystemC library in detail. Thereafter, we discuss related\r\napproaches and close with applications in electronic automotive systems design\r\nand some evaluations.","lang":"eng"}],"editor":[{"first_name":"Wolfgang","full_name":"Ecker, Wolfgang","last_name":"Ecker"},{"full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"},{"first_name":"Rainer","last_name":"Dömer","full_name":"Dömer, Rainer"}],"department":[{"_id":"672"}],"user_id":"5786","_id":"33813","language":[{"iso":"eng"}],"keyword":["RTOS Modelling","RTOS Simulation","SystemC","Task Scheduling","Interrupt Analysis"]},{"date_created":"2022-10-18T10:54:39Z","author":[{"full_name":"Ecker, Wolfgang","last_name":"Ecker","first_name":"Wolfgang"},{"last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243","first_name":"Wolfgang"},{"last_name":"Dömer","full_name":"Dömer, Rainer","first_name":"Rainer"}],"publisher":"Springer Verlag","date_updated":"2022-10-18T10:54:56Z","doi":"10.1007/978-1-4020-9436-1_1","title":"Hardware-dependent Software - Introduction and Overview","publication_identifier":{"isbn":["978-1-4020-9435-4"]},"citation":{"ama":"Ecker W, Müller W, Dömer R. Hardware-dependent Software - Introduction and Overview. In: Ecker W, Müller W, Dömer R, eds. <i>Hardware Dependent Software - Principles and Practice</i>. Springer Verlag; 2009:1-14. doi:<a href=\"https://doi.org/10.1007/978-1-4020-9436-1_1\">10.1007/978-1-4020-9436-1_1</a>","ieee":"W. Ecker, W. Müller, and R. Dömer, “Hardware-dependent Software - Introduction and Overview,” in <i>Hardware Dependent Software - Principles and Practice</i>, W. Ecker, W. Müller, and R. Dömer, Eds. Dordrecht: Springer Verlag, 2009, pp. 1–14.","chicago":"Ecker, Wolfgang, Wolfgang Müller, and Rainer Dömer. “Hardware-Dependent Software - Introduction and Overview.” In <i>Hardware Dependent Software - Principles and Practice</i>, edited by Wolfgang Ecker, Wolfgang Müller, and Rainer Dömer, 1–14. Dordrecht: Springer Verlag, 2009. <a href=\"https://doi.org/10.1007/978-1-4020-9436-1_1\">https://doi.org/10.1007/978-1-4020-9436-1_1</a>.","apa":"Ecker, W., Müller, W., &#38; Dömer, R. (2009). Hardware-dependent Software - Introduction and Overview. In W. Ecker, W. Müller, &#38; R. Dömer (Eds.), <i>Hardware Dependent Software - Principles and Practice</i> (pp. 1–14). Springer Verlag. <a href=\"https://doi.org/10.1007/978-1-4020-9436-1_1\">https://doi.org/10.1007/978-1-4020-9436-1_1</a>","bibtex":"@inbook{Ecker_Müller_Dömer_2009, place={Dordrecht}, title={Hardware-dependent Software - Introduction and Overview}, DOI={<a href=\"https://doi.org/10.1007/978-1-4020-9436-1_1\">10.1007/978-1-4020-9436-1_1</a>}, booktitle={Hardware Dependent Software - Principles and Practice}, publisher={Springer Verlag}, author={Ecker, Wolfgang and Müller, Wolfgang and Dömer, Rainer}, editor={Ecker, Wolfgang and Müller, Wolfgang and Dömer, Rainer}, year={2009}, pages={1–14} }","mla":"Ecker, Wolfgang, et al. “Hardware-Dependent Software - Introduction and Overview.” <i>Hardware Dependent Software - Principles and Practice</i>, edited by Wolfgang Ecker et al., Springer Verlag, 2009, pp. 1–14, doi:<a href=\"https://doi.org/10.1007/978-1-4020-9436-1_1\">10.1007/978-1-4020-9436-1_1</a>.","short":"W. Ecker, W. Müller, R. Dömer, in: W. Ecker, W. Müller, R. Dömer (Eds.), Hardware Dependent Software - Principles and Practice, Springer Verlag, Dordrecht, 2009, pp. 1–14."},"page":"1-14","place":"Dordrecht","year":"2009","user_id":"5786","department":[{"_id":"672"}],"_id":"33814","language":[{"iso":"eng"}],"keyword":["Hardware-dependent Software","Systems Complexity","Productivity Gap"],"type":"book_chapter","publication":"Hardware Dependent Software - Principles and Practice","status":"public","editor":[{"first_name":"Wolfgang","last_name":"Ecker","full_name":"Ecker, Wolfgang"},{"full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"},{"first_name":"Rainer","full_name":"Dömer, Rainer","last_name":"Dömer"}],"abstract":[{"text":"Rapidly rising system complexity has created a growing productivity gap in the\r\ndesign of electronic systems. One critical component is Hardware-dependent\r\nSoftware (HdS), the importance of which is often underestimated. In this chap-\r\nter, we introduce HdS and illustrate its role in the overall system design context.\r\nWe also provide a brief overview and define a basic HdS terminology and con-\r\nclude with a brief outlook over the following chapters in this book.","lang":"eng"}]},{"doi":"10.1007/978-1-4020-9436-1","title":"Hardware-dependent Software","date_created":"2023-01-25T22:20:51Z","date_updated":"2024-04-18T20:09:39Z","publisher":"Springer Netherlands","citation":{"ama":"Ecker W, Müller W, Dömer R, eds. <i>Hardware-Dependent Software</i>. Springer Netherlands; 2009. doi:<a href=\"https://doi.org/10.1007/978-1-4020-9436-1\">10.1007/978-1-4020-9436-1</a>","ieee":"W. Ecker, W. Müller, and R. Dömer, Eds., <i>Hardware-dependent Software</i>. Dordrecht: Springer Netherlands, 2009.","chicago":"Ecker, Wolfgang, Wolfgang Müller, and Rainer Dömer, eds. <i>Hardware-Dependent Software</i>. Dordrecht: Springer Netherlands, 2009. <a href=\"https://doi.org/10.1007/978-1-4020-9436-1\">https://doi.org/10.1007/978-1-4020-9436-1</a>.","apa":"Ecker, W., Müller, W., &#38; Dömer, R. (Eds.). (2009). <i>Hardware-dependent Software</i>. Springer Netherlands. <a href=\"https://doi.org/10.1007/978-1-4020-9436-1\">https://doi.org/10.1007/978-1-4020-9436-1</a>","mla":"Ecker, Wolfgang, et al., editors. <i>Hardware-Dependent Software</i>. Springer Netherlands, 2009, doi:<a href=\"https://doi.org/10.1007/978-1-4020-9436-1\">10.1007/978-1-4020-9436-1</a>.","short":"W. Ecker, W. Müller, R. Dömer, eds., Hardware-Dependent Software, Springer Netherlands, Dordrecht, 2009.","bibtex":"@book{Ecker_Müller_Dömer_2009, place={Dordrecht}, title={Hardware-dependent Software}, DOI={<a href=\"https://doi.org/10.1007/978-1-4020-9436-1\">10.1007/978-1-4020-9436-1</a>}, publisher={Springer Netherlands}, year={2009} }"},"place":"Dordrecht","year":"2009","publication_identifier":{"isbn":["9781402094354","9781402094361"]},"publication_status":"published","language":[{"iso":"eng"}],"alternative_title":["Principles and Practice"],"department":[{"_id":"58"}],"user_id":"15931","_id":"40119","status":"public","editor":[{"first_name":"Wolfgang","full_name":"Ecker, Wolfgang","last_name":"Ecker"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"first_name":"Rainer","last_name":"Dömer","full_name":"Dömer, Rainer"}],"type":"book_editor"},{"publication":"Proceedings of DATE'09","type":"conference","status":"public","abstract":[{"text":"IP-XACT is a well accepted standard for the exchange of IP components at Electronic System and Register Transfer Level. Still, the creation and manipulation of these descriptions at the XML level can be time-consuming and error-prone. In this paper, we show that the UML can be consistently applied as an efficient and comprehensible frontend for IP-XACT-based IP description and integration. For this, we present an IP-XACT UML profile that enables UML-based descriptions covering the same information as a corresponding IP-XACT description. This enables the automated generation of IP-XACT component and design descriptions from respective UML models. In particular, it also allows the integration of existing IPs with UML. To illustrate our approach, we present an application example based on the IBM PowerPC Evaluation Kit.","lang":"eng"}],"department":[{"_id":"672"}],"user_id":"5786","_id":"37067","language":[{"iso":"eng"}],"keyword":["Unified modeling language","XML","Power system modeling","Application software","Master-slave","Power system management","Acceleration","Scattering","Software engineering","Software standards"],"publication_identifier":{"isbn":["978-1-4244-3781-8"]},"citation":{"ama":"Schattkowsky T, Xie T, Müller W. A UML Frontend for IP-XACT-based IP Management. In: <i>Proceedings of DATE’09</i>. IEEE; 2009. doi:<a href=\"https://doi.org/10.1109/DATE.2009.5090664\">10.1109/DATE.2009.5090664</a>","chicago":"Schattkowsky, Tim, Tao Xie, and Wolfgang Müller. “A UML Frontend for IP-XACT-Based IP Management.” In <i>Proceedings of DATE’09</i>. Nice, France: IEEE, 2009. <a href=\"https://doi.org/10.1109/DATE.2009.5090664\">https://doi.org/10.1109/DATE.2009.5090664</a>.","ieee":"T. Schattkowsky, T. Xie, and W. Müller, “A UML Frontend for IP-XACT-based IP Management,” presented at the Design, Automation &#38; Test in Europe Conference &#38; Exhibition, 2009, doi: <a href=\"https://doi.org/10.1109/DATE.2009.5090664\">10.1109/DATE.2009.5090664</a>.","apa":"Schattkowsky, T., Xie, T., &#38; Müller, W. (2009). A UML Frontend for IP-XACT-based IP Management. <i>Proceedings of DATE’09</i>. Design, Automation &#38; Test in Europe Conference &#38; Exhibition. <a href=\"https://doi.org/10.1109/DATE.2009.5090664\">https://doi.org/10.1109/DATE.2009.5090664</a>","short":"T. Schattkowsky, T. Xie, W. Müller, in: Proceedings of DATE’09, IEEE, Nice, France, 2009.","mla":"Schattkowsky, Tim, et al. “A UML Frontend for IP-XACT-Based IP Management.” <i>Proceedings of DATE’09</i>, IEEE, 2009, doi:<a href=\"https://doi.org/10.1109/DATE.2009.5090664\">10.1109/DATE.2009.5090664</a>.","bibtex":"@inproceedings{Schattkowsky_Xie_Müller_2009, place={Nice, France}, title={A UML Frontend for IP-XACT-based IP Management}, DOI={<a href=\"https://doi.org/10.1109/DATE.2009.5090664\">10.1109/DATE.2009.5090664</a>}, booktitle={Proceedings of DATE’09}, publisher={IEEE}, author={Schattkowsky, Tim and Xie, Tao and Müller, Wolfgang}, year={2009} }"},"year":"2009","place":"Nice, France","date_created":"2023-01-17T11:54:02Z","author":[{"full_name":"Schattkowsky, Tim","last_name":"Schattkowsky","first_name":"Tim"},{"full_name":"Xie, Tao","last_name":"Xie","first_name":"Tao"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"}],"publisher":"IEEE","date_updated":"2023-01-17T11:54:07Z","doi":"10.1109/DATE.2009.5090664","conference":{"name":"Design, Automation & Test in Europe Conference & Exhibition"},"title":"A UML Frontend for IP-XACT-based IP Management"},{"date_created":"2023-01-17T11:51:44Z","author":[{"last_name":"Zabel","full_name":"Zabel, Henning","first_name":"Henning"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"}],"date_updated":"2023-01-17T11:51:48Z","doi":"10.1109/DATE.2009.5090925","conference":{"name":"Design, Automation & Test in Europe Conference & Exhibition"},"title":"Increased Accuracy through Noise Injection in Abstract RTOS Simulation","publication_identifier":{"isbn":["978-1-4244-3781-8"]},"citation":{"apa":"Zabel, H., &#38; Müller, W. (2009). Increased Accuracy through Noise Injection in Abstract RTOS Simulation. <i>Proceedings of DATE’09</i>. Design, Automation &#38; Test in Europe Conference &#38; Exhibition. <a href=\"https://doi.org/10.1109/DATE.2009.5090925\">https://doi.org/10.1109/DATE.2009.5090925</a>","short":"H. Zabel, W. Müller, in: Proceedings of DATE’09, Nice, France, 2009.","mla":"Zabel, Henning, and Wolfgang Müller. “Increased Accuracy through Noise Injection in Abstract RTOS Simulation.” <i>Proceedings of DATE’09</i>, 2009, doi:<a href=\"https://doi.org/10.1109/DATE.2009.5090925\">10.1109/DATE.2009.5090925</a>.","bibtex":"@inproceedings{Zabel_Müller_2009, place={Nice, France}, title={Increased Accuracy through Noise Injection in Abstract RTOS Simulation}, DOI={<a href=\"https://doi.org/10.1109/DATE.2009.5090925\">10.1109/DATE.2009.5090925</a>}, booktitle={Proceedings of DATE’09}, author={Zabel, Henning and Müller, Wolfgang}, year={2009} }","ieee":"H. Zabel and W. Müller, “Increased Accuracy through Noise Injection in Abstract RTOS Simulation,” presented at the Design, Automation &#38; Test in Europe Conference &#38; Exhibition, 2009, doi: <a href=\"https://doi.org/10.1109/DATE.2009.5090925\">10.1109/DATE.2009.5090925</a>.","chicago":"Zabel, Henning, and Wolfgang Müller. “Increased Accuracy through Noise Injection in Abstract RTOS Simulation.” In <i>Proceedings of DATE’09</i>. Nice, France, 2009. <a href=\"https://doi.org/10.1109/DATE.2009.5090925\">https://doi.org/10.1109/DATE.2009.5090925</a>.","ama":"Zabel H, Müller W. Increased Accuracy through Noise Injection in Abstract RTOS Simulation. In: <i>Proceedings of DATE’09</i>. ; 2009. doi:<a href=\"https://doi.org/10.1109/DATE.2009.5090925\">10.1109/DATE.2009.5090925</a>"},"year":"2009","place":"Nice, France","department":[{"_id":"672"}],"user_id":"5786","_id":"37066","language":[{"iso":"eng"}],"keyword":["Timing","Analytical models","Clocks","Performance analysis","Scheduling","Operating systems","Delay","Real time systems","Application software","Context modeling"],"publication":"Proceedings of DATE'09","type":"conference","status":"public","abstract":[{"text":"Today, mobile and embedded real-time systems have to cope with the migration and allocation of multiple software tasks running on top of a real-time operating system (RTOS) residing on one or multiple system processors. Abstract RTOS simulations and timing analysis applies for fast and early estimation to configure it towards the individual needs of the application and environment. In this context, a high accuracy of the simulation compared to an instruction set simulation (ISS) is of key importance. In this paper, we investigate the accuracy of abstract RTOS simulation and compare it to ISS and the behavior of the physical system. We show that we can reach an increased accuracy of the simulation when we inject noise into the time model. Our results indicate that it is sufficient to inject uniformly distributed random time values to the RTOS real-time clock.","lang":"eng"}]},{"type":"conference","publication":"Proceedings of IESS09","status":"public","abstract":[{"text":"Safety-critical automotive systems must fulfill hard real-time constraints to guarantee their reliability and safety requirements. In the context of network-based electronics systems, high-level timing requirements have to be carefully mastered and traced throughout the whole development process. In this paper, we outline the management of scheduling-specific timing information by the application of a steer-by-wire design example. We apply the principles of the AUTOSAR-compliant Timing Augmented Description Language (TADL) following the methodology introduced by the TIMMO project[2]. Focus of the example will be the identification of end-to-end timing constraints and their refinement by means of stimuli-response event chains.","lang":"eng"}],"user_id":"5786","department":[{"_id":"672"}],"_id":"37063","language":[{"iso":"eng"}],"keyword":["Abstraction Level     Controller Area Network     High Abstraction Level     Event Chain     Automotive System"],"publication_identifier":{"isbn":["978-3-642-04283-6"]},"citation":{"apa":"Klobedanz, K., Kuznik, C., Elfeky, A., &#38; Müller, W. (2009). Development of Automotive Communication Based Real-Time Systems - A Steer-by-Wire Case Study. <i>Proceedings of IESS09</i>. <a href=\"https://doi.org/10.1007/978-3-642-04284-3_20\">https://doi.org/10.1007/978-3-642-04284-3_20</a>","short":"K. Klobedanz, C. Kuznik, A. Elfeky, W. Müller, in: Proceedings of IESS09, Springer Verlag, 2009.","mla":"Klobedanz, Kay, et al. “Development of Automotive Communication Based Real-Time Systems - A Steer-by-Wire Case Study.” <i>Proceedings of IESS09</i>, Springer Verlag, 2009, doi:<a href=\"https://doi.org/10.1007/978-3-642-04284-3_20\">10.1007/978-3-642-04284-3_20</a>.","bibtex":"@inproceedings{Klobedanz_Kuznik_Elfeky_Müller_2009, title={Development of Automotive Communication Based Real-Time Systems - A Steer-by-Wire Case Study}, DOI={<a href=\"https://doi.org/10.1007/978-3-642-04284-3_20\">10.1007/978-3-642-04284-3_20</a>}, booktitle={Proceedings of IESS09}, publisher={Springer Verlag}, author={Klobedanz, Kay and Kuznik, Christoph and Elfeky, Ahmed and Müller, Wolfgang}, year={2009} }","ama":"Klobedanz K, Kuznik C, Elfeky A, Müller W. Development of Automotive Communication Based Real-Time Systems - A Steer-by-Wire Case Study. In: <i>Proceedings of IESS09</i>. Springer Verlag; 2009. doi:<a href=\"https://doi.org/10.1007/978-3-642-04284-3_20\">10.1007/978-3-642-04284-3_20</a>","ieee":"K. Klobedanz, C. Kuznik, A. Elfeky, and W. Müller, “Development of Automotive Communication Based Real-Time Systems - A Steer-by-Wire Case Study,” 2009, doi: <a href=\"https://doi.org/10.1007/978-3-642-04284-3_20\">10.1007/978-3-642-04284-3_20</a>.","chicago":"Klobedanz, Kay, Christoph Kuznik, Ahmed Elfeky, and Wolfgang Müller. “Development of Automotive Communication Based Real-Time Systems - A Steer-by-Wire Case Study.” In <i>Proceedings of IESS09</i>. Springer Verlag, 2009. <a href=\"https://doi.org/10.1007/978-3-642-04284-3_20\">https://doi.org/10.1007/978-3-642-04284-3_20</a>."},"year":"2009","author":[{"first_name":"Kay","full_name":"Klobedanz, Kay","last_name":"Klobedanz"},{"last_name":"Kuznik","full_name":"Kuznik, Christoph","first_name":"Christoph"},{"full_name":"Elfeky, Ahmed","last_name":"Elfeky","first_name":"Ahmed"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"}],"date_created":"2023-01-17T11:42:03Z","publisher":"Springer Verlag","date_updated":"2023-01-17T11:42:08Z","doi":"10.1007/978-3-642-04284-3_20","title":"Development of Automotive Communication Based Real-Time Systems - A Steer-by-Wire Case Study"},{"citation":{"mla":"Becker, Markus, et al. <i>Integration Abstrakter RTOS-Simulation in Den Entwurf Eingebetteter Automobiler E/E-Systeme</i>. 2009.","bibtex":"@inproceedings{Becker_Zabel_Müller_2009, title={Integration abstrakter RTOS-Simulation in den Entwurf eingebetteter automobiler E/E-Systeme}, author={Becker, Markus and Zabel, Henning and Müller, Wolfgang}, year={2009} }","short":"M. Becker, H. Zabel, W. Müller, in: 2009.","apa":"Becker, M., Zabel, H., &#38; Müller, W. (2009). <i>Integration abstrakter RTOS-Simulation in den Entwurf eingebetteter automobiler E/E-Systeme</i>. Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Berlin.","ama":"Becker M, Zabel H, Müller W. Integration abstrakter RTOS-Simulation in den Entwurf eingebetteter automobiler E/E-Systeme. In: ; 2009.","ieee":"M. Becker, H. Zabel, and W. Müller, “Integration abstrakter RTOS-Simulation in den Entwurf eingebetteter automobiler E/E-Systeme,” presented at the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Berlin, 2009.","chicago":"Becker, Markus, Henning Zabel, and Wolfgang Müller. “Integration Abstrakter RTOS-Simulation in Den Entwurf Eingebetteter Automobiler E/E-Systeme,” 2009."},"status":"public","year":"2009","type":"conference","language":[{"iso":"eng"}],"conference":{"location":"Berlin","name":"Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)"},"title":"Integration abstrakter RTOS-Simulation in den Entwurf eingebetteter automobiler E/E-Systeme","date_created":"2023-01-17T11:49:24Z","author":[{"last_name":"Becker","full_name":"Becker, Markus","first_name":"Markus"},{"full_name":"Zabel, Henning","last_name":"Zabel","first_name":"Henning"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"}],"user_id":"5786","department":[{"_id":"672"}],"date_updated":"2023-01-17T11:49:29Z","_id":"37064"},{"language":[{"iso":"eng"}],"department":[{"_id":"672"}],"user_id":"5786","_id":"37061","status":"public","publication":"Proceedings of IESS09","type":"conference","title":"Systematic Model-in-the-Loop Test of Embedded Control Systems","author":[{"full_name":"Krupp, Alexander","last_name":"Krupp","first_name":"Alexander"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"}],"date_created":"2023-01-17T11:39:08Z","date_updated":"2023-01-17T11:39:16Z","citation":{"mla":"Krupp, Alexander, and Wolfgang Müller. “Systematic Model-in-the-Loop Test of Embedded Control Systems.” <i>Proceedings of IESS09</i>, 2009.","short":"A. Krupp, W. Müller, in: Proceedings of IESS09, Friedrichshafen, 2009.","bibtex":"@inproceedings{Krupp_Müller_2009, place={Friedrichshafen}, title={Systematic Model-in-the-Loop Test of Embedded Control Systems}, booktitle={Proceedings of IESS09}, author={Krupp, Alexander and Müller, Wolfgang}, year={2009} }","apa":"Krupp, A., &#38; Müller, W. (2009). Systematic Model-in-the-Loop Test of Embedded Control Systems. <i>Proceedings of IESS09</i>.","ama":"Krupp A, Müller W. Systematic Model-in-the-Loop Test of Embedded Control Systems. In: <i>Proceedings of IESS09</i>. ; 2009.","ieee":"A. Krupp and W. Müller, “Systematic Model-in-the-Loop Test of Embedded Control Systems,” 2009.","chicago":"Krupp, Alexander, and Wolfgang Müller. “Systematic Model-in-the-Loop Test of Embedded Control Systems.” In <i>Proceedings of IESS09</i>. Friedrichshafen, 2009."},"year":"2009","place":"Friedrichshafen"}]