[{"date_created":"2021-09-30T08:17:50Z","author":[{"full_name":"Becker, Markus","last_name":"Becker","first_name":"Markus"},{"full_name":"Kuznik, Christoph","last_name":"Kuznik","first_name":"Christoph"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"}],"date_updated":"2022-01-06T06:56:53Z","title":"Fault Effect Modeling in a Heterogeneous SystemC Virtual Platform Framework for Cyber-Physical Systems","citation":{"apa":"Becker, M., Kuznik, C., &#38; Müller, W. (2014). Fault Effect Modeling in a Heterogeneous SystemC Virtual Platform Framework for Cyber-Physical Systems. <i>ACM/IEEE 5th International Conference on Cyber-Physical Systems</i>.","mla":"Becker, Markus, et al. “Fault Effect Modeling in a Heterogeneous SystemC Virtual Platform Framework for Cyber-Physical Systems.” <i>ACM/IEEE 5th International Conference on Cyber-Physical Systems</i>, 2014.","bibtex":"@inproceedings{Becker_Kuznik_Müller_2014, title={Fault Effect Modeling in a Heterogeneous SystemC Virtual Platform Framework for Cyber-Physical Systems}, booktitle={ACM/IEEE 5th International Conference on Cyber-Physical Systems}, author={Becker, Markus and Kuznik, Christoph and Müller, Wolfgang}, year={2014} }","short":"M. Becker, C. Kuznik, W. Müller, in: ACM/IEEE 5th International Conference on Cyber-Physical Systems, 2014.","chicago":"Becker, Markus, Christoph Kuznik, and Wolfgang Müller. “Fault Effect Modeling in a Heterogeneous SystemC Virtual Platform Framework for Cyber-Physical Systems.” In <i>ACM/IEEE 5th International Conference on Cyber-Physical Systems</i>, 2014.","ieee":"M. Becker, C. Kuznik, and W. Müller, “Fault Effect Modeling in a Heterogeneous SystemC Virtual Platform Framework for Cyber-Physical Systems,” 2014.","ama":"Becker M, Kuznik C, Müller W. Fault Effect Modeling in a Heterogeneous SystemC Virtual Platform Framework for Cyber-Physical Systems. In: <i>ACM/IEEE 5th International Conference on Cyber-Physical Systems</i>. ; 2014."},"year":"2014","department":[{"_id":"672"}],"user_id":"21240","_id":"25155","language":[{"iso":"eng"}],"publication":"ACM/IEEE 5th International Conference on Cyber-Physical Systems","type":"conference","status":"public"},{"_id":"25161","department":[{"_id":"672"}],"user_id":"21240","language":[{"iso":"eng"}],"publication":"17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) ","type":"conference","status":"public","date_updated":"2022-01-06T06:56:53Z","author":[{"first_name":"Bastian","last_name":"Koppelmann","full_name":"Koppelmann, Bastian","id":"25260"},{"last_name":"Becker","full_name":"Becker, Markus","first_name":"Markus"},{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"}],"date_created":"2021-09-30T09:51:08Z","title":"Portierung der TriCore-Architektur auf QEMU","year":"2014","citation":{"short":"B. Koppelmann, M. Becker, W. Müller, in: 17. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2014) , 2014.","bibtex":"@inproceedings{Koppelmann_Becker_Müller_2014, title={Portierung der TriCore-Architektur auf QEMU}, booktitle={17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) }, author={Koppelmann, Bastian and Becker, Markus and Müller, Wolfgang}, year={2014} }","mla":"Koppelmann, Bastian, et al. “Portierung Der TriCore-Architektur Auf QEMU.” <i>17. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2014) </i>, 2014.","apa":"Koppelmann, B., Becker, M., &#38; Müller, W. (2014). Portierung der TriCore-Architektur auf QEMU. <i>17. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2014) </i>.","ieee":"B. Koppelmann, M. Becker, and W. Müller, “Portierung der TriCore-Architektur auf QEMU,” 2014.","chicago":"Koppelmann, Bastian, Markus Becker, and Wolfgang Müller. “Portierung Der TriCore-Architektur Auf QEMU.” In <i>17. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2014) </i>, 2014.","ama":"Koppelmann B, Becker M, Müller W. Portierung der TriCore-Architektur auf QEMU. In: <i>17. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2014) </i>. ; 2014."}},{"user_id":"15931","department":[{"_id":"58"}],"_id":"24305","language":[{"iso":"eng"}],"type":"conference","publication":"Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)","status":"public","abstract":[{"lang":"eng","text":"Energy efficiency drives the development of more and more complex low-power designs. Based on dynamic power management techniques, multiple voltage islands as well as a huge amount of power states are specified that have to be tested carefully. In this context, low-power design should start at an early stage using state-of-the-art system-level modeling and simulation techniques. However, there is neither a programming language nor any modeling standard that reflects variable power together with its functional side effects in a well-suited abstract manner. To overcome this limitation, we present a modeling approach on top of SystemC TLM to capture low-power design characteristics at electronic system-level. We demonstrate the usability by means of an existing open-source low-power design. The experimental results show that appropriate TLM instrumentation cause only minimal simulation overhead, but offer sufficient details to identify common low-power design errors."}],"author":[{"first_name":"Fabian","last_name":"Mischkalla","full_name":"Mischkalla, Fabian"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"}],"date_created":"2021-09-14T07:06:51Z","publisher":"IEEE","date_updated":"2022-02-17T12:46:32Z","conference":{"start_date":"2014.07.14","end_date":"2014.07.17"},"doi":"10.1109/SAMOS.2014.6893219","title":"Architectural Low-Power Design Using Transaction-Based System Modeling and Simulation","related_material":{"link":[{"relation":"confirmation","url":"https://ieeexplore.ieee.org/document/6893219"}]},"publication_identifier":{"eisbn":["978-1-4799-3770-7"]},"citation":{"short":"F. Mischkalla, W. Müller, in: Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), IEEE, Greece, 2014.","mla":"Mischkalla, Fabian, and Wolfgang Müller. “Architectural Low-Power Design Using Transaction-Based System Modeling and Simulation.” <i>Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)</i>, IEEE, 2014, doi:<a href=\"https://doi.org/10.1109/SAMOS.2014.6893219\">10.1109/SAMOS.2014.6893219</a>.","bibtex":"@inproceedings{Mischkalla_Müller_2014, place={Greece}, title={Architectural Low-Power Design Using Transaction-Based System Modeling and Simulation}, DOI={<a href=\"https://doi.org/10.1109/SAMOS.2014.6893219\">10.1109/SAMOS.2014.6893219</a>}, booktitle={Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)}, publisher={IEEE}, author={Mischkalla, Fabian and Müller, Wolfgang}, year={2014} }","apa":"Mischkalla, F., &#38; Müller, W. (2014). Architectural Low-Power Design Using Transaction-Based System Modeling and Simulation. <i>Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)</i>. <a href=\"https://doi.org/10.1109/SAMOS.2014.6893219\">https://doi.org/10.1109/SAMOS.2014.6893219</a>","chicago":"Mischkalla, Fabian, and Wolfgang Müller. “Architectural Low-Power Design Using Transaction-Based System Modeling and Simulation.” In <i>Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)</i>. Greece: IEEE, 2014. <a href=\"https://doi.org/10.1109/SAMOS.2014.6893219\">https://doi.org/10.1109/SAMOS.2014.6893219</a>.","ieee":"F. Mischkalla and W. Müller, “Architectural Low-Power Design Using Transaction-Based System Modeling and Simulation,” 2014, doi: <a href=\"https://doi.org/10.1109/SAMOS.2014.6893219\">10.1109/SAMOS.2014.6893219</a>.","ama":"Mischkalla F, Müller W. Architectural Low-Power Design Using Transaction-Based System Modeling and Simulation. In: <i>Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)</i>. IEEE; 2014. doi:<a href=\"https://doi.org/10.1109/SAMOS.2014.6893219\">10.1109/SAMOS.2014.6893219</a>"},"place":"Greece","year":"2014"},{"author":[{"first_name":"Bastian","last_name":"Koppelmann","id":"25260","full_name":"Koppelmann, Bastian"},{"full_name":"Messidat, Bernd","last_name":"Messidat","first_name":"Bernd"},{"full_name":"Becker, Markus","last_name":"Becker","first_name":"Markus"},{"full_name":"Kuznik, Christoph","last_name":"Kuznik","first_name":"Christoph"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"full_name":"Scheytt, Christoph","id":"37144","last_name":"Scheytt","first_name":"Christoph"}],"date_created":"2021-09-14T07:06:47Z","date_updated":"2022-02-17T12:34:27Z","conference":{"start_date":"2014.10.14","location":"München, Germany"},"title":"Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU","related_material":{"link":[{"relation":"confirmation","url":"http://dvcon-europe.org/conference/dvcon-europe-2014/"}]},"citation":{"apa":"Koppelmann, B., Messidat, B., Becker, M., Kuznik, C., Müller, W., &#38; Scheytt, C. (2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. <i>Design and Verification Conference (DVCON EUROPE)</i>.","bibtex":"@article{Koppelmann_Messidat_Becker_Kuznik_Müller_Scheytt_2014, title={Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}, journal={Design and Verification Conference (DVCON EUROPE)}, author={Koppelmann, Bastian and Messidat, Bernd and Becker, Markus and Kuznik, Christoph and Müller, Wolfgang and Scheytt, Christoph}, year={2014} }","short":"B. Koppelmann, B. Messidat, M. Becker, C. Kuznik, W. Müller, C. Scheytt, Design and Verification Conference (DVCON EUROPE) (2014).","mla":"Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” <i>Design and Verification Conference (DVCON EUROPE)</i>, 2014.","chicago":"Koppelmann, Bastian, Bernd Messidat, Markus Becker, Christoph Kuznik, Wolfgang Müller, and Christoph Scheytt. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” <i>Design and Verification Conference (DVCON EUROPE)</i>, 2014.","ieee":"B. Koppelmann, B. Messidat, M. Becker, C. Kuznik, W. Müller, and C. Scheytt, “Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” <i>Design and Verification Conference (DVCON EUROPE)</i>, 2014.","ama":"Koppelmann B, Messidat B, Becker M, Kuznik C, Müller W, Scheytt C. Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. <i>Design and Verification Conference (DVCON EUROPE)</i>. Published online 2014."},"year":"2014","user_id":"15931","department":[{"_id":"58"}],"_id":"24302","language":[{"iso":"eng"}],"type":"journal_article","publication":"Design and Verification Conference (DVCON EUROPE)","status":"public","abstract":[{"lang":"eng","text":"In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation."}]},{"title":"Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure","conference":{"start_date":"2014.03.25"},"date_updated":"2022-02-17T13:14:13Z","author":[{"first_name":"Christoph","full_name":"Kuznik, Christoph","last_name":"Kuznik"},{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"}],"date_created":"2021-09-14T07:06:56Z","year":"2014","citation":{"ama":"Kuznik C, Müller W. Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure. <i>Design, Automation and Test in Europe DATE, University Booth, Dresden</i>. Published online 2014.","chicago":"Kuznik, Christoph, and Wolfgang Müller. “Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure.” <i>Design, Automation and Test in Europe DATE, University Booth, Dresden</i>, 2014.","ieee":"C. Kuznik and W. Müller, “Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure,” <i>Design, Automation and Test in Europe DATE, University Booth, Dresden</i>, 2014.","apa":"Kuznik, C., &#38; Müller, W. (2014). Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure. <i>Design, Automation and Test in Europe DATE, University Booth, Dresden</i>.","short":"C. Kuznik, W. Müller, Design, Automation and Test in Europe DATE, University Booth, Dresden (2014).","mla":"Kuznik, Christoph, and Wolfgang Müller. “Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure.” <i>Design, Automation and Test in Europe DATE, University Booth, Dresden</i>, 2014.","bibtex":"@article{Kuznik_Müller_2014, title={Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure}, journal={Design, Automation and Test in Europe DATE, University Booth, Dresden}, author={Kuznik, Christoph and Müller, Wolfgang}, year={2014} }"},"related_material":{"link":[{"relation":"confirmation","url":"https://www.edacentrum.de/effektiv/content/verific-mm-systematized-verification-metrics-generation-ucis-improved-automation-verificatio"}]},"language":[{"iso":"eng"}],"_id":"24309","department":[{"_id":"58"}],"user_id":"15931","abstract":[{"lang":"eng","text":"Verific-MM is an approach to systematize and accelerate the coverage plan engineering as well as the verification environment’s (functional) metric code generation -- usually a time-consuming and error-prone task -- in particular by (i) improving automation via assisted model-based approaches, utilizing recent industry standards such as UCIS and (ii) a supporting methodology suitable for various target (functional coverage) languages (IEEE-1800 SystemVerilog, IEEE-1647 e, IEEE-1666 SystemC)."}],"status":"public","publication":"Design, Automation and Test in Europe DATE, University Booth, Dresden","type":"journal_article"},{"citation":{"apa":"Oetjens, J.-H., Becker, M., Kuznik, C., Müller, W., Bannow, N., Brinkmann, O., Burger, A., Chaari, M., Chakraborty, S., Drechsler, R., Ecker, W., Grüttner, K., Kruse, T., Le, H. M., Mauderer, M., Mueller-Gritschneider, D., Poppen, F., Post, H., Reiter, Se., … Viehl, A. (2014). Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges. <i>Design Automation Conference (DAC)</i>. <a href=\"https://doi.org/10.1145/2593069.2602976\">https://doi.org/10.1145/2593069.2602976</a>","mla":"Oetjens, Jan-Hendrik, et al. “Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges.” <i>Design Automation Conference (DAC)</i>, 2014, doi:<a href=\"https://doi.org/10.1145/2593069.2602976\">10.1145/2593069.2602976</a>.","short":"J.-H. Oetjens, M. Becker, C. Kuznik, W. Müller, N. Bannow, O. Brinkmann, A. Burger, M. Chaari, S. Chakraborty, R. Drechsler, W. Ecker, K. Grüttner, T. Kruse, H.M. Le, M. Mauderer, D. Mueller-Gritschneider, F. Poppen, H. Post, Se. Reiter, W. Rosenstiel, S. Roth, U. Schlichtmann, A. Von Schwerin, B.A. Tabacaru, A. Viehl, in: Design Automation Conference (DAC), 2014.","bibtex":"@inproceedings{Oetjens_Becker_Kuznik_Müller_Bannow_Brinkmann_Burger_Chaari_Chakraborty_Drechsler_et al._2014, title={Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges}, DOI={<a href=\"https://doi.org/10.1145/2593069.2602976\">10.1145/2593069.2602976</a>}, booktitle={Design Automation Conference (DAC)}, author={Oetjens, Jan-Hendrik and Becker, Markus and Kuznik, Christoph and Müller, Wolfgang and Bannow, Nico and Brinkmann, Oliver and Burger, Andreas and Chaari, Moomen and Chakraborty, Samarjit and Drechsler, R. and et al.}, year={2014} }","ama":"Oetjens J-H, Becker M, Kuznik C, et al. Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges. In: <i>Design Automation Conference (DAC)</i>. ; 2014. doi:<a href=\"https://doi.org/10.1145/2593069.2602976\">10.1145/2593069.2602976</a>","chicago":"Oetjens, Jan-Hendrik, Markus Becker, Christoph Kuznik, Wolfgang Müller, Nico Bannow, Oliver Brinkmann, Andreas Burger, et al. “Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges.” In <i>Design Automation Conference (DAC)</i>, 2014. <a href=\"https://doi.org/10.1145/2593069.2602976\">https://doi.org/10.1145/2593069.2602976</a>.","ieee":"J.-H. Oetjens <i>et al.</i>, “Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges,” 2014, doi: <a href=\"https://doi.org/10.1145/2593069.2602976\">10.1145/2593069.2602976</a>."},"year":"2014","related_material":{"link":[{"relation":"confirmation","url":"https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6881440"}]},"doi":"10.1145/2593069.2602976","title":"Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges","author":[{"first_name":"Jan-Hendrik","last_name":"Oetjens","full_name":"Oetjens, Jan-Hendrik"},{"full_name":"Becker, Markus","last_name":"Becker","first_name":"Markus"},{"first_name":"Christoph","full_name":"Kuznik, Christoph","last_name":"Kuznik"},{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"},{"full_name":"Bannow, Nico","last_name":"Bannow","first_name":"Nico"},{"first_name":"Oliver","last_name":"Brinkmann","full_name":"Brinkmann, Oliver"},{"first_name":"Andreas","full_name":"Burger, Andreas","last_name":"Burger"},{"first_name":"Moomen","full_name":"Chaari, Moomen","last_name":"Chaari"},{"last_name":"Chakraborty","full_name":"Chakraborty, Samarjit","first_name":"Samarjit"},{"last_name":"Drechsler","full_name":"Drechsler, R.","first_name":"R."},{"first_name":"Wolfgang","last_name":"Ecker","full_name":"Ecker, Wolfgang"},{"full_name":"Grüttner, Kim","last_name":"Grüttner","first_name":"Kim"},{"first_name":"Thomas","last_name":"Kruse","full_name":"Kruse, Thomas"},{"first_name":"Hoang M","full_name":"Le, Hoang M","last_name":"Le"},{"last_name":"Mauderer","full_name":"Mauderer, M.","first_name":"M."},{"first_name":"Daniel","full_name":"Mueller-Gritschneider, Daniel","last_name":"Mueller-Gritschneider"},{"last_name":"Poppen","full_name":"Poppen, Frank","first_name":"Frank"},{"first_name":"Hendrik","full_name":"Post, Hendrik","last_name":"Post"},{"first_name":"SEbastian","full_name":"Reiter, SEbastian","last_name":"Reiter"},{"last_name":"Rosenstiel","full_name":"Rosenstiel, Wolfgang","first_name":"Wolfgang"},{"first_name":"S. ","full_name":"Roth, S. ","last_name":"Roth"},{"first_name":"Ulf","full_name":"Schlichtmann, Ulf","last_name":"Schlichtmann"},{"first_name":"Andreas","last_name":"Von Schwerin","full_name":"Von Schwerin, Andreas"},{"first_name":"Bogdan Andrei","last_name":"Tabacaru","full_name":"Tabacaru, Bogdan Andrei"},{"last_name":"Viehl","full_name":"Viehl, Alexander","first_name":"Alexander"}],"date_created":"2021-09-14T07:06:59Z","date_updated":"2022-02-17T13:47:16Z","status":"public","abstract":[{"text":"Intelligent automotive electronics significantly improved driving safety in the last decades. With the increasing complexity of automotive systems, dependability of the electronic components themselves and of their interaction must be assured to avoid any risk to driving safety due to unexpected failures caused by internal or external faults. Additionally, Virtual Prototypes (VPs) have been accepted in many areas of system development processes in the automotive industry as platforms for SW development, verification, and design space exploration. We believe that VPs will significantly contribute to the analysis of safety conditions for automotive electronics. This paper shows the advantages of such a methodology based on today's industrial needs, presents the current state of the art in this field, and outlines upcoming research challenges that need to be addressed to make this vision a reality.","lang":"eng"}],"publication":"Design Automation Conference (DAC)","type":"conference","language":[{"iso":"eng"}],"department":[{"_id":"58"}],"user_id":"15931","_id":"24311"},{"language":[{"iso":"eng"}],"_id":"25164","department":[{"_id":"672"}],"user_id":"16243","status":"public","publication":"Design, Automation and Test in Europe DATE, University Booth, Dresden","type":"journal_article","title":"HeroeS - A Framework for Heterogeneous Software-Intensive System Design with SystemC","date_updated":"2024-04-18T21:06:21Z","author":[{"full_name":"Becker, Markus","last_name":"Becker","first_name":"Markus"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"last_name":"Stroop","full_name":"Stroop, Joachim","first_name":"Joachim"},{"first_name":"Ulrich","full_name":"Kiffmeier, Ulrich","last_name":"Kiffmeier"}],"date_created":"2021-09-30T10:17:43Z","year":"2014","citation":{"ieee":"M. Becker, W. Müller, J. Stroop, and U. Kiffmeier, “HeroeS - A Framework for Heterogeneous Software-Intensive System Design with SystemC,” <i>Design, Automation and Test in Europe DATE, University Booth, Dresden</i>, 2014.","chicago":"Becker, Markus, Wolfgang Müller, Joachim Stroop, and Ulrich Kiffmeier. “HeroeS - A Framework for Heterogeneous Software-Intensive System Design with SystemC.” <i>Design, Automation and Test in Europe DATE, University Booth, Dresden</i>, 2014.","ama":"Becker M, Müller W, Stroop J, Kiffmeier U. HeroeS - A Framework for Heterogeneous Software-Intensive System Design with SystemC. <i>Design, Automation and Test in Europe DATE, University Booth, Dresden</i>. Published online 2014.","short":"M. Becker, W. Müller, J. Stroop, U. Kiffmeier, Design, Automation and Test in Europe DATE, University Booth, Dresden (2014).","mla":"Becker, Markus, et al. “HeroeS - A Framework for Heterogeneous Software-Intensive System Design with SystemC.” <i>Design, Automation and Test in Europe DATE, University Booth, Dresden</i>, 2014.","bibtex":"@article{Becker_Müller_Stroop_Kiffmeier_2014, title={HeroeS - A Framework for Heterogeneous Software-Intensive System Design with SystemC}, journal={Design, Automation and Test in Europe DATE, University Booth, Dresden}, author={Becker, Markus and Müller, Wolfgang and Stroop, Joachim and Kiffmeier, Ulrich}, year={2014} }","apa":"Becker, M., Müller, W., Stroop, J., &#38; Kiffmeier, U. (2014). HeroeS - A Framework for Heterogeneous Software-Intensive System Design with SystemC. <i>Design, Automation and Test in Europe DATE, University Booth, Dresden</i>."}},{"citation":{"ieee":"F. Mischkalla and W. Müller, “Architectural Low-Power Design Using Transaction-Based System Simulation,” Greece, Sep. 2014, IEEE, 2014.","chicago":"Mischkalla, Fabian, and Wolfgang Müller. “Architectural Low-Power Design Using Transaction-Based System Simulation.” In <i>Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)</i>. IEEE, 2014.","ama":"Mischkalla F, Müller W. Architectural Low-Power Design Using Transaction-Based System Simulation. In: <i>Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)</i>. IEEE; 2014.","apa":"Mischkalla, F., &#38; Müller, W. (2014). Architectural Low-Power Design Using Transaction-Based System Simulation. <i>Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)</i>.","bibtex":"@inproceedings{Mischkalla_Müller_2014, title={Architectural Low-Power Design Using Transaction-Based System Simulation}, booktitle={Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)}, publisher={IEEE}, author={Mischkalla, Fabian and Müller, Wolfgang}, year={2014} }","mla":"Mischkalla, Fabian, and Wolfgang Müller. “Architectural Low-Power Design Using Transaction-Based System Simulation.” <i>Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)</i>, IEEE, 2014.","short":"F. Mischkalla, W. Müller, in: Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), IEEE, 2014."},"year":"2014","author":[{"first_name":"Fabian","last_name":"Mischkalla","full_name":"Mischkalla, Fabian"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"}],"date_created":"2021-09-29T12:06:12Z","publisher":"IEEE","date_updated":"2023-01-16T11:29:24Z","conference":{"location":"Greece, Sep. 2014, IEEE"},"title":"Architectural Low-Power Design Using Transaction-Based System Simulation","publication":"Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)","type":"conference","status":"public","department":[{"_id":"58"}],"user_id":"5786","_id":"25120","language":[{"iso":"eng"}]},{"title":"Source code annotated memory leak detection for soft real time embedded systems with resource constraints","language":[{"iso":"eng"}],"_id":"25146","date_updated":"2023-01-16T11:36:02Z","department":[{"_id":"58"}],"date_created":"2021-09-30T07:18:43Z","user_id":"5786","author":[{"first_name":"M. tech. Mabel Mary","last_name":"Joy","full_name":"Joy, M. tech. Mabel Mary"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"},{"last_name":"Rammig","full_name":"Rammig, Franz-Josef","first_name":"Franz-Josef"}],"year":"2014","status":"public","citation":{"short":"M. tech. M.M. Joy, W. Müller, F.-J. Rammig, in: 12th IEEE International Conference on Embedded Computing, 2014.","mla":"Joy, M. tech. Mabel Mary, et al. “Source Code Annotated Memory Leak Detection for Soft Real Time Embedded Systems with Resource Constraints.” <i>12th IEEE International Conference on Embedded Computing</i>, 2014.","bibtex":"@inproceedings{Joy_Müller_Rammig_2014, title={Source code annotated memory leak detection for soft real time embedded systems with resource constraints}, booktitle={12th IEEE International conference on Embedded Computing}, author={Joy, M. tech. Mabel Mary and Müller, Wolfgang and Rammig, Franz-Josef}, year={2014} }","apa":"Joy, M. tech. M. M., Müller, W., &#38; Rammig, F.-J. (2014). Source code annotated memory leak detection for soft real time embedded systems with resource constraints. <i>12th IEEE International Conference on Embedded Computing</i>.","chicago":"Joy, M. tech. Mabel Mary, Wolfgang Müller, and Franz-Josef Rammig. “Source Code Annotated Memory Leak Detection for Soft Real Time Embedded Systems with Resource Constraints.” In <i>12th IEEE International Conference on Embedded Computing</i>, 2014.","ieee":"M. tech. M. M. Joy, W. Müller, and F.-J. Rammig, “Source code annotated memory leak detection for soft real time embedded systems with resource constraints,” 2014.","ama":"Joy M tech. MM, Müller W, Rammig F-J. Source code annotated memory leak detection for soft real time embedded systems with resource constraints. In: <i>12th IEEE International Conference on Embedded Computing</i>. ; 2014."},"publication":"12th IEEE International conference on Embedded Computing","type":"conference"},{"type":"conference","publication":"PATMOS 2014","status":"public","_id":"25144","user_id":"5786","department":[{"_id":"58"}],"language":[{"iso":"eng"}],"place":"Palma de Mallorca, Spain","year":"2014","citation":{"short":"F. Mischkalla, W. Müller, in: PATMOS 2014, Palma de Mallorca, Spain, 2014.","mla":"Mischkalla, Fabian, and Wolfgang Müller. “Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation.” <i>PATMOS 2014</i>, 2014.","bibtex":"@inproceedings{Mischkalla_Müller_2014, place={Palma de Mallorca, Spain}, title={Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation}, booktitle={PATMOS 2014}, author={Mischkalla, Fabian and Müller, Wolfgang}, year={2014} }","apa":"Mischkalla, F., &#38; Müller, W. (2014). Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation. <i>PATMOS 2014</i>.","chicago":"Mischkalla, Fabian, and Wolfgang Müller. “Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation.” In <i>PATMOS 2014</i>. Palma de Mallorca, Spain, 2014.","ieee":"F. Mischkalla and W. Müller, “Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation,” 2014.","ama":"Mischkalla F, Müller W. Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation. In: <i>PATMOS 2014</i>. ; 2014."},"date_updated":"2023-01-16T11:28:39Z","date_created":"2021-09-30T07:13:17Z","author":[{"last_name":"Mischkalla","full_name":"Mischkalla, Fabian","first_name":"Fabian"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"}],"title":"Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation"},{"type":"conference","abstract":[{"lang":"eng","text":"This paper presents an advanced eight levels spanning SystemC based virtual platform methodology and framework - referred to as HeroeS 3 - providing smooth application to platform mapping and continuous co-refinement of a virtual prototype with its physical environment model. For heterogeneity support, various SystemC extensions are combined covering continuous/discrete models of computation and different communication abstractions, such as analog mixed-signal models, abstract RTOS/HAL/middleware models, TLM bus models, and QEMU wrappers. We enable dependability assessment by Fault Effect Modeling (FEM) at the virtual prototype in order to avoid risking physical injury or damage. Also, simulation results are deterministic and can be evaluated interactively or offline. We apply FEM to both the physical environment model and the different abstractions of the virtual prototype. Currently, we focus on sensor failures and application control flow errors."}],"status":"public","_id":"36918","department":[{"_id":"58"}],"user_id":"5786","keyword":["Computational modeling","Finite element analysis","Prototypes","Abstracts","Software","Fault tolerance","Fault tolerant systems"],"language":[{"iso":"eng"}],"year":"2014","place":"Berlin","citation":{"ama":"Becker M, Kuznik C, Müller W. Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems. In: IEEE; 2014. doi:<a href=\"https://doi.org/10.1109/ICCPS.2014.6843726\">10.1109/ICCPS.2014.6843726</a>","ieee":"M. Becker, C. Kuznik, and W. Müller, “Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems,” presented at the ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS), Berlin, 2014, doi: <a href=\"https://doi.org/10.1109/ICCPS.2014.6843726\">10.1109/ICCPS.2014.6843726</a>.","chicago":"Becker, Markus, Christoph Kuznik, and Wolfgang Müller. “Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems.” Berlin: IEEE, 2014. <a href=\"https://doi.org/10.1109/ICCPS.2014.6843726\">https://doi.org/10.1109/ICCPS.2014.6843726</a>.","short":"M. Becker, C. Kuznik, W. Müller, in: IEEE, Berlin, 2014.","mla":"Becker, Markus, et al. <i>Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems</i>. IEEE, 2014, doi:<a href=\"https://doi.org/10.1109/ICCPS.2014.6843726\">10.1109/ICCPS.2014.6843726</a>.","bibtex":"@inproceedings{Becker_Kuznik_Müller_2014, place={Berlin}, title={Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems}, DOI={<a href=\"https://doi.org/10.1109/ICCPS.2014.6843726\">10.1109/ICCPS.2014.6843726</a>}, publisher={IEEE}, author={Becker, Markus and Kuznik, Christoph and Müller, Wolfgang}, year={2014} }","apa":"Becker, M., Kuznik, C., &#38; Müller, W. (2014). <i>Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems</i>. ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS), Berlin. <a href=\"https://doi.org/10.1109/ICCPS.2014.6843726\">https://doi.org/10.1109/ICCPS.2014.6843726</a>"},"date_updated":"2023-01-16T11:57:22Z","publisher":"IEEE","author":[{"last_name":"Becker","full_name":"Becker, Markus","first_name":"Markus"},{"full_name":"Kuznik, Christoph","last_name":"Kuznik","first_name":"Christoph"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"}],"date_created":"2023-01-16T11:57:08Z","title":"Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems","conference":{"location":"Berlin","name":"ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS)"},"doi":"10.1109/ICCPS.2014.6843726"},{"status":"public","abstract":[{"lang":"eng","text":"The ever-increasing complexity of heterogeneous electronic systems demand for intensified abstraction and automation efforts to improve design, verification and validation productivity, especially in earlier phases of system engineering. Within the verification activity various metrics can be applied to determine functional correctness or the overall progress. Here, a supporting verification methodology defining high-level verification planning down to the actual metric code development is essential. Moreover, an advanced assistance for the designer, such as a tooling infrastructure to automatize and accelerate the metric code implementation, is needed to minimize the influence of errorprone manual coding. In this article we present a single-source verification metric code-generation methodology for improved coverage automation. We determine (i) a suitable metric model for model-based capture of verification metrics as well as (ii) an assisted model-based processing and generation flow of the verification environment and metric skeletons. We apply our method to a SystemC case-study, in doing so, targeting metric code implementation productivity and consistency enhancement."}],"type":"conference","language":[{"iso":"eng"}],"keyword":["System Design","Verification"],"department":[{"_id":"58"}],"user_id":"5786","_id":"36917","citation":{"apa":"Kuznik, C., Müller, W., &#38; Defo, G. B. (2014). <i>An Assisted Single Source Verification Metric Model Code Generation Methodology</i>. Proceedings of the Electronic System Level Synthesis Conference (ESLSyn).","short":"C. Kuznik, W. Müller, G.B. Defo, in: San Francisco, USA, 2014.","mla":"Kuznik, Christoph, et al. <i>An Assisted Single Source Verification Metric Model Code Generation Methodology</i>. 2014.","bibtex":"@inproceedings{Kuznik_Müller_Defo_2014, place={San Francisco, USA}, title={An Assisted Single Source Verification Metric Model Code Generation Methodology}, author={Kuznik, Christoph and Müller, Wolfgang and Defo, Gilles Bertrand}, year={2014} }","ieee":"C. Kuznik, W. Müller, and G. B. Defo, “An Assisted Single Source Verification Metric Model Code Generation Methodology,” presented at the Proceedings of the Electronic System Level Synthesis Conference (ESLSyn), 2014.","chicago":"Kuznik, Christoph, Wolfgang Müller, and Gilles Bertrand Defo. “An Assisted Single Source Verification Metric Model Code Generation Methodology.” San Francisco, USA, 2014.","ama":"Kuznik C, Müller W, Defo GB. An Assisted Single Source Verification Metric Model Code Generation Methodology. In: ; 2014."},"year":"2014","place":"San Francisco, USA","conference":{"name":"Proceedings of the Electronic System Level Synthesis Conference (ESLSyn)"},"title":"An Assisted Single Source Verification Metric Model Code Generation Methodology","author":[{"first_name":"Christoph","full_name":"Kuznik, Christoph","last_name":"Kuznik"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"},{"last_name":"Defo","full_name":"Defo, Gilles Bertrand","first_name":"Gilles Bertrand"}],"date_created":"2023-01-16T11:43:50Z","date_updated":"2023-01-16T11:44:06Z"},{"author":[{"first_name":"Christoph","last_name":"Kuznik","full_name":"Kuznik, Christoph"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"}],"date_created":"2021-09-30T10:26:58Z","user_id":"5786","department":[{"_id":"58"}],"date_updated":"2023-01-16T11:46:54Z","_id":"25166","language":[{"iso":"ger"}],"title":"Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM","type":"conference","publication":"26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen","citation":{"apa":"Kuznik, C., &#38; Müller, W. (2014). Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM. <i>26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen</i>.","short":"C. Kuznik, W. Müller, in: 26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, 2014.","bibtex":"@inproceedings{Kuznik_Müller_2014, title={Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM}, booktitle={26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen}, author={Kuznik, Christoph and Müller, Wolfgang}, year={2014} }","mla":"Kuznik, Christoph, and Wolfgang Müller. “Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM.” <i>26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen</i>, 2014.","ieee":"C. Kuznik and W. Müller, “Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM,” 2014.","chicago":"Kuznik, Christoph, and Wolfgang Müller. “Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM.” In <i>26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen</i>, 2014.","ama":"Kuznik C, Müller W. Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM. In: <i>26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen</i>. ; 2014."},"status":"public","year":"2014","abstract":[{"text":"Zur Sicherstellung hoher Zuverlässigkeits- und Fehlertoleranzwerte von Schaltungen und ganzen Systemen finden vermehrt Test- und Verifikationsmethoden Anwendung die einen virtuellen Prototypen (VP) des Systems bereits frühzeitig im Entwurfsablauf einem Stresstest unterziehen. Hierbei werden speziell für die Domäne relevante Fehlerinjektoren verwendet (Digital, Mixed-Signal, Mechanik) die anhand von Fehlermodellen geeignete Testfälle erzeugen und in das System über Stimuli bzw. direkt injizieren. Jede effektive Anwendung einer Methode bedingt jedoch auch das Vorhandensein einer zugrundeliegenden Methodik. In diesem Beitrag wird die System Verification Methodology (SVM) vorgestellt werden, eine universell einsetzbare und erweiterbare Infrastruktur zur Beschreibung von Testumgebungen auf Basis der SystemC Sprache und Simulationskernels.","lang":"eng"}]},{"status":"public","type":"conference","publication":"17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) ","language":[{"iso":"ger"}],"user_id":"5786","department":[{"_id":"58"}],"_id":"25163","citation":{"ama":"Kuznik C, Defo BG, Müller W. Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung. In: <i>17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) </i>. ; 2014.","chicago":"Kuznik, Christoph, Bertrand Gilles Defo, and Wolfgang Müller. “Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung.” In <i>17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) </i>, 2014.","ieee":"C. Kuznik, B. G. Defo, and W. Müller, “Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung,” 2014.","bibtex":"@inproceedings{Kuznik_Defo_Müller_2014, title={Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung}, booktitle={17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) }, author={Kuznik, Christoph and Defo, Bertrand Gilles and Müller, Wolfgang}, year={2014} }","short":"C. Kuznik, B.G. Defo, W. Müller, in: 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) , 2014.","mla":"Kuznik, Christoph, et al. “Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung.” <i>17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) </i>, 2014.","apa":"Kuznik, C., Defo, B. G., &#38; Müller, W. (2014). Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung. <i>17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) </i>."},"year":"2014","title":"Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung","author":[{"full_name":"Kuznik, Christoph","last_name":"Kuznik","first_name":"Christoph"},{"first_name":"Bertrand Gilles","last_name":"Defo","full_name":"Defo, Bertrand Gilles"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"}],"date_created":"2021-09-30T10:11:13Z","date_updated":"2023-01-16T11:45:51Z"},{"status":"public","type":"journal_article","publication":"Electronic System Level Synthesis Conference (ESLSyn)","language":[{"iso":"eng"}],"user_id":"5786","department":[{"_id":"58"}],"_id":"25151","citation":{"ama":"Kuznik C, Defo BG, Müller W. An Assisted Single Source Verification Metric Model Code Generation Methodology. <i>Electronic System Level Synthesis Conference (ESLSyn)</i>. Published online 2014.","chicago":"Kuznik, Christoph, Bertrand Gilles Defo, and Wolfgang Müller. “An Assisted Single Source Verification Metric Model Code Generation Methodology.” <i>Electronic System Level Synthesis Conference (ESLSyn)</i>, 2014.","ieee":"C. Kuznik, B. G. Defo, and W. Müller, “An Assisted Single Source Verification Metric Model Code Generation Methodology,” <i>Electronic System Level Synthesis Conference (ESLSyn)</i>, 2014.","bibtex":"@article{Kuznik_Defo_Müller_2014, title={An Assisted Single Source Verification Metric Model Code Generation Methodology}, journal={Electronic System Level Synthesis Conference (ESLSyn)}, author={Kuznik, Christoph and Defo, Bertrand Gilles and Müller, Wolfgang}, year={2014} }","short":"C. Kuznik, B.G. Defo, W. Müller, Electronic System Level Synthesis Conference (ESLSyn) (2014).","mla":"Kuznik, Christoph, et al. “An Assisted Single Source Verification Metric Model Code Generation Methodology.” <i>Electronic System Level Synthesis Conference (ESLSyn)</i>, 2014.","apa":"Kuznik, C., Defo, B. G., &#38; Müller, W. (2014). An Assisted Single Source Verification Metric Model Code Generation Methodology. <i>Electronic System Level Synthesis Conference (ESLSyn)</i>."},"year":"2014","title":"An Assisted Single Source Verification Metric Model Code Generation Methodology","author":[{"first_name":"Christoph","full_name":"Kuznik, Christoph","last_name":"Kuznik"},{"first_name":"Bertrand Gilles","last_name":"Defo","full_name":"Defo, Bertrand Gilles"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"}],"date_created":"2021-09-30T08:05:38Z","date_updated":"2023-01-16T11:44:46Z"},{"date_updated":"2023-02-01T08:12:02Z","date_created":"2022-12-20T10:48:25Z","author":[{"first_name":"Bastian","last_name":"Koppelmann","id":"25260","full_name":"Koppelmann, Bastian"},{"first_name":"Bernd","last_name":"Messidat","full_name":"Messidat, Bernd"},{"last_name":"Becker","full_name":"Becker, Markus","first_name":"Markus"},{"last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243","first_name":"Wolfgang"},{"first_name":"J. Christoph","id":"37144","full_name":"Scheytt, J. Christoph","orcid":"https://orcid.org/0000-0002-5950-6618","last_name":"Scheytt"}],"title":"Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU","place":"München","year":"2014","citation":{"mla":"Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>, 2014.","short":"B. Koppelmann, B. Messidat, M. Becker, W. Müller, J.C. Scheytt, in: Proceedings of the Design and Verification Conference Europe (DVCON Europe), München, 2014.","bibtex":"@inproceedings{Koppelmann_Messidat_Becker_Müller_Scheytt_2014, place={München}, title={Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}, booktitle={Proceedings of the Design and Verification Conference Europe (DVCON Europe)}, author={Koppelmann, Bastian and Messidat, Bernd and Becker, Markus and Müller, Wolfgang and Scheytt, J. Christoph}, year={2014} }","apa":"Koppelmann, B., Messidat, B., Becker, M., Müller, W., &#38; Scheytt, J. C. (2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>.","chicago":"Koppelmann, Bastian, Bernd Messidat, Markus Becker, Wolfgang Müller, and J. Christoph Scheytt. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” In <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>. München, 2014.","ieee":"B. Koppelmann, B. Messidat, M. Becker, W. Müller, and J. C. Scheytt, “Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” 2014.","ama":"Koppelmann B, Messidat B, Becker M, Müller W, Scheytt JC. Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. In: <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>. ; 2014."},"_id":"34585","user_id":"15931","department":[{"_id":"58"}],"keyword":["System Design","Verification"],"language":[{"iso":"eng"}],"type":"conference","publication":"Proceedings of the Design and Verification Conference Europe (DVCON Europe)","abstract":[{"lang":"eng","text":"In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation."}],"status":"public"},{"title":"Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU","date_updated":"2025-02-26T14:42:18Z","author":[{"last_name":"Koppelmann","id":"25260","full_name":"Koppelmann, Bastian","first_name":"Bastian"},{"first_name":"Bernd","full_name":"Messidat, Bernd","last_name":"Messidat"},{"full_name":"Kuznik, Christoph","last_name":"Kuznik","first_name":"Christoph"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"},{"full_name":"Becker, Markus","last_name":"Becker","first_name":"Markus"},{"first_name":"J. Christoph","orcid":"https://orcid.org/0000-0002-5950-6618","last_name":"Scheytt","full_name":"Scheytt, J. Christoph","id":"37144"}],"date_created":"2022-12-20T10:45:38Z","place":"München","year":"2014","citation":{"bibtex":"@inproceedings{Koppelmann_Messidat_Kuznik_Müller_Becker_Scheytt_2014, place={München}, title={Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}, booktitle={Proceedings of the Design and Verification Conference Europe (DVCON Europe)}, author={Koppelmann, Bastian and Messidat, Bernd and Kuznik, Christoph and Müller, Wolfgang and Becker, Markus and Scheytt, J. Christoph}, year={2014} }","mla":"Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>, 2014.","short":"B. Koppelmann, B. Messidat, C. Kuznik, W. Müller, M. Becker, J.C. Scheytt, in: Proceedings of the Design and Verification Conference Europe (DVCON Europe), München, 2014.","apa":"Koppelmann, B., Messidat, B., Kuznik, C., Müller, W., Becker, M., &#38; Scheytt, J. C. (2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>.","chicago":"Koppelmann, Bastian, Bernd Messidat, Christoph Kuznik, Wolfgang Müller, Markus Becker, and J. Christoph Scheytt. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” In <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>. München, 2014.","ieee":"B. Koppelmann, B. Messidat, C. Kuznik, W. Müller, M. Becker, and J. C. Scheytt, “Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” 2014.","ama":"Koppelmann B, Messidat B, Kuznik C, Müller W, Becker M, Scheytt JC. Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. In: <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>. ; 2014."},"keyword":["System Design","Verification"],"language":[{"iso":"eng"}],"_id":"34583","department":[{"_id":"58"}],"user_id":"16243","abstract":[{"lang":"eng","text":"In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation."}],"status":"public","publication":"Proceedings of the Design and Verification Conference Europe (DVCON Europe)","type":"conference"},{"title":"Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU","conference":{"name":"DVCON Europe"},"date_updated":"2025-02-26T14:44:30Z","author":[{"first_name":"Markus","last_name":"Becker","full_name":"Becker, Markus"},{"first_name":"Christoph","last_name":"Kuznik","full_name":"Kuznik, Christoph"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"},{"first_name":"Bastian","full_name":"Koppelmann, Bastian","last_name":"Koppelmann"},{"first_name":"Bernd","last_name":"Messidat","full_name":"Messidat, Bernd"}],"date_created":"2022-12-20T10:37:51Z","place":"München","year":"2014","citation":{"short":"M. Becker, C. Kuznik, W. Müller, B. Koppelmann, B. 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