[{"date_created":"2023-01-16T11:57:08Z","author":[{"full_name":"Becker, Markus","last_name":"Becker","first_name":"Markus"},{"full_name":"Kuznik, Christoph","last_name":"Kuznik","first_name":"Christoph"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"}],"date_updated":"2023-01-16T11:57:22Z","publisher":"IEEE","doi":"10.1109/ICCPS.2014.6843726","conference":{"name":"ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS)","location":"Berlin"},"title":"Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems","citation":{"mla":"Becker, Markus, et al. <i>Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems</i>. IEEE, 2014, doi:<a href=\"https://doi.org/10.1109/ICCPS.2014.6843726\">10.1109/ICCPS.2014.6843726</a>.","short":"M. Becker, C. Kuznik, W. Müller, in: IEEE, Berlin, 2014.","bibtex":"@inproceedings{Becker_Kuznik_Müller_2014, place={Berlin}, title={Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems}, DOI={<a href=\"https://doi.org/10.1109/ICCPS.2014.6843726\">10.1109/ICCPS.2014.6843726</a>}, publisher={IEEE}, author={Becker, Markus and Kuznik, Christoph and Müller, Wolfgang}, year={2014} }","apa":"Becker, M., Kuznik, C., &#38; Müller, W. (2014). <i>Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems</i>. ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS), Berlin. <a href=\"https://doi.org/10.1109/ICCPS.2014.6843726\">https://doi.org/10.1109/ICCPS.2014.6843726</a>","chicago":"Becker, Markus, Christoph Kuznik, and Wolfgang Müller. “Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems.” Berlin: IEEE, 2014. <a href=\"https://doi.org/10.1109/ICCPS.2014.6843726\">https://doi.org/10.1109/ICCPS.2014.6843726</a>.","ieee":"M. Becker, C. Kuznik, and W. Müller, “Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems,” presented at the ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS), Berlin, 2014, doi: <a href=\"https://doi.org/10.1109/ICCPS.2014.6843726\">10.1109/ICCPS.2014.6843726</a>.","ama":"Becker M, Kuznik C, Müller W. Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems. In: IEEE; 2014. doi:<a href=\"https://doi.org/10.1109/ICCPS.2014.6843726\">10.1109/ICCPS.2014.6843726</a>"},"year":"2014","place":"Berlin","user_id":"5786","department":[{"_id":"58"}],"_id":"36918","language":[{"iso":"eng"}],"keyword":["Computational modeling","Finite element analysis","Prototypes","Abstracts","Software","Fault tolerance","Fault tolerant systems"],"type":"conference","status":"public","abstract":[{"lang":"eng","text":"This paper presents an advanced eight levels spanning SystemC based virtual platform methodology and framework - referred to as HeroeS 3 - providing smooth application to platform mapping and continuous co-refinement of a virtual prototype with its physical environment model. For heterogeneity support, various SystemC extensions are combined covering continuous/discrete models of computation and different communication abstractions, such as analog mixed-signal models, abstract RTOS/HAL/middleware models, TLM bus models, and QEMU wrappers. We enable dependability assessment by Fault Effect Modeling (FEM) at the virtual prototype in order to avoid risking physical injury or damage. Also, simulation results are deterministic and can be evaluated interactively or offline. We apply FEM to both the physical environment model and the different abstractions of the virtual prototype. Currently, we focus on sensor failures and application control flow errors."}]},{"department":[{"_id":"58"}],"user_id":"5786","_id":"36917","language":[{"iso":"eng"}],"keyword":["System Design","Verification"],"type":"conference","status":"public","abstract":[{"lang":"eng","text":"The ever-increasing complexity of heterogeneous electronic systems demand for intensified abstraction and automation efforts to improve design, verification and validation productivity, especially in earlier phases of system engineering. Within the verification activity various metrics can be applied to determine functional correctness or the overall progress. Here, a supporting verification methodology defining high-level verification planning down to the actual metric code development is essential. Moreover, an advanced assistance for the designer, such as a tooling infrastructure to automatize and accelerate the metric code implementation, is needed to minimize the influence of errorprone manual coding. In this article we present a single-source verification metric code-generation methodology for improved coverage automation. We determine (i) a suitable metric model for model-based capture of verification metrics as well as (ii) an assisted model-based processing and generation flow of the verification environment and metric skeletons. We apply our method to a SystemC case-study, in doing so, targeting metric code implementation productivity and consistency enhancement."}],"date_created":"2023-01-16T11:43:50Z","author":[{"first_name":"Christoph","last_name":"Kuznik","full_name":"Kuznik, Christoph"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"},{"full_name":"Defo, Gilles Bertrand","last_name":"Defo","first_name":"Gilles Bertrand"}],"date_updated":"2023-01-16T11:44:06Z","conference":{"name":"Proceedings of the Electronic System Level Synthesis Conference (ESLSyn)"},"title":"An Assisted Single Source Verification Metric Model Code Generation Methodology","citation":{"apa":"Kuznik, C., Müller, W., &#38; Defo, G. B. (2014). <i>An Assisted Single Source Verification Metric Model Code Generation Methodology</i>. Proceedings of the Electronic System Level Synthesis Conference (ESLSyn).","short":"C. Kuznik, W. Müller, G.B. Defo, in: San Francisco, USA, 2014.","bibtex":"@inproceedings{Kuznik_Müller_Defo_2014, place={San Francisco, USA}, title={An Assisted Single Source Verification Metric Model Code Generation Methodology}, author={Kuznik, Christoph and Müller, Wolfgang and Defo, Gilles Bertrand}, year={2014} }","mla":"Kuznik, Christoph, et al. <i>An Assisted Single Source Verification Metric Model Code Generation Methodology</i>. 2014.","chicago":"Kuznik, Christoph, Wolfgang Müller, and Gilles Bertrand Defo. “An Assisted Single Source Verification Metric Model Code Generation Methodology.” San Francisco, USA, 2014.","ieee":"C. Kuznik, W. Müller, and G. B. Defo, “An Assisted Single Source Verification Metric Model Code Generation Methodology,” presented at the Proceedings of the Electronic System Level Synthesis Conference (ESLSyn), 2014.","ama":"Kuznik C, Müller W, Defo GB. An Assisted Single Source Verification Metric Model Code Generation Methodology. In: ; 2014."},"year":"2014","place":"San Francisco, USA"},{"department":[{"_id":"58"}],"date_created":"2021-09-30T10:26:58Z","author":[{"first_name":"Christoph","full_name":"Kuznik, Christoph","last_name":"Kuznik"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"}],"user_id":"5786","_id":"25166","date_updated":"2023-01-16T11:46:54Z","language":[{"iso":"ger"}],"title":"Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM","publication":"26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen","type":"conference","status":"public","citation":{"ama":"Kuznik C, Müller W. Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM. In: <i>26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen</i>. ; 2014.","ieee":"C. Kuznik and W. Müller, “Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM,” 2014.","chicago":"Kuznik, Christoph, and Wolfgang Müller. “Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM.” In <i>26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen</i>, 2014.","short":"C. Kuznik, W. Müller, in: 26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, 2014.","bibtex":"@inproceedings{Kuznik_Müller_2014, title={Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM}, booktitle={26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen}, author={Kuznik, Christoph and Müller, Wolfgang}, year={2014} }","mla":"Kuznik, Christoph, and Wolfgang Müller. “Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM.” <i>26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen</i>, 2014.","apa":"Kuznik, C., &#38; Müller, W. (2014). Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM. <i>26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen</i>."},"abstract":[{"lang":"eng","text":"Zur Sicherstellung hoher Zuverlässigkeits- und Fehlertoleranzwerte von Schaltungen und ganzen Systemen finden vermehrt Test- und Verifikationsmethoden Anwendung die einen virtuellen Prototypen (VP) des Systems bereits frühzeitig im Entwurfsablauf einem Stresstest unterziehen. Hierbei werden speziell für die Domäne relevante Fehlerinjektoren verwendet (Digital, Mixed-Signal, Mechanik) die anhand von Fehlermodellen geeignete Testfälle erzeugen und in das System über Stimuli bzw. direkt injizieren. Jede effektive Anwendung einer Methode bedingt jedoch auch das Vorhandensein einer zugrundeliegenden Methodik. In diesem Beitrag wird die System Verification Methodology (SVM) vorgestellt werden, eine universell einsetzbare und erweiterbare Infrastruktur zur Beschreibung von Testumgebungen auf Basis der SystemC Sprache und Simulationskernels."}],"year":"2014"},{"status":"public","type":"conference","publication":"17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) ","language":[{"iso":"ger"}],"user_id":"5786","department":[{"_id":"58"}],"_id":"25163","citation":{"bibtex":"@inproceedings{Kuznik_Defo_Müller_2014, title={Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung}, booktitle={17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) }, author={Kuznik, Christoph and Defo, Bertrand Gilles and Müller, Wolfgang}, year={2014} }","short":"C. Kuznik, B.G. Defo, W. Müller, in: 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) , 2014.","mla":"Kuznik, Christoph, et al. “Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung.” <i>17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) </i>, 2014.","apa":"Kuznik, C., Defo, B. G., &#38; Müller, W. (2014). Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung. <i>17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) </i>.","ama":"Kuznik C, Defo BG, Müller W. Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung. In: <i>17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) </i>. ; 2014.","ieee":"C. Kuznik, B. G. Defo, and W. Müller, “Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung,” 2014.","chicago":"Kuznik, Christoph, Bertrand Gilles Defo, and Wolfgang Müller. “Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung.” In <i>17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) </i>, 2014."},"year":"2014","title":"Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung","author":[{"first_name":"Christoph","full_name":"Kuznik, Christoph","last_name":"Kuznik"},{"full_name":"Defo, Bertrand Gilles","last_name":"Defo","first_name":"Bertrand Gilles"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"}],"date_created":"2021-09-30T10:11:13Z","date_updated":"2023-01-16T11:45:51Z"},{"citation":{"ama":"Kuznik C, Defo BG, Müller W. An Assisted Single Source Verification Metric Model Code Generation Methodology. <i>Electronic System Level Synthesis Conference (ESLSyn)</i>. Published online 2014.","chicago":"Kuznik, Christoph, Bertrand Gilles Defo, and Wolfgang Müller. “An Assisted Single Source Verification Metric Model Code Generation Methodology.” <i>Electronic System Level Synthesis Conference (ESLSyn)</i>, 2014.","ieee":"C. Kuznik, B. G. Defo, and W. Müller, “An Assisted Single Source Verification Metric Model Code Generation Methodology,” <i>Electronic System Level Synthesis Conference (ESLSyn)</i>, 2014.","apa":"Kuznik, C., Defo, B. G., &#38; Müller, W. (2014). An Assisted Single Source Verification Metric Model Code Generation Methodology. <i>Electronic System Level Synthesis Conference (ESLSyn)</i>.","short":"C. Kuznik, B.G. Defo, W. Müller, Electronic System Level Synthesis Conference (ESLSyn) (2014).","mla":"Kuznik, Christoph, et al. “An Assisted Single Source Verification Metric Model Code Generation Methodology.” <i>Electronic System Level Synthesis Conference (ESLSyn)</i>, 2014.","bibtex":"@article{Kuznik_Defo_Müller_2014, title={An Assisted Single Source Verification Metric Model Code Generation Methodology}, journal={Electronic System Level Synthesis Conference (ESLSyn)}, author={Kuznik, Christoph and Defo, Bertrand Gilles and Müller, Wolfgang}, year={2014} }"},"year":"2014","title":"An Assisted Single Source Verification Metric Model Code Generation Methodology","author":[{"last_name":"Kuznik","full_name":"Kuznik, Christoph","first_name":"Christoph"},{"last_name":"Defo","full_name":"Defo, Bertrand Gilles","first_name":"Bertrand Gilles"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"}],"date_created":"2021-09-30T08:05:38Z","date_updated":"2023-01-16T11:44:46Z","status":"public","publication":"Electronic System Level Synthesis Conference (ESLSyn)","type":"journal_article","language":[{"iso":"eng"}],"department":[{"_id":"58"}],"user_id":"5786","_id":"25151"},{"language":[{"iso":"eng"}],"keyword":["System Design","Verification"],"user_id":"15931","department":[{"_id":"58"}],"_id":"34585","status":"public","abstract":[{"lang":"eng","text":"In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation."}],"type":"conference","publication":"Proceedings of the Design and Verification Conference Europe (DVCON Europe)","title":"Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU","author":[{"last_name":"Koppelmann","full_name":"Koppelmann, Bastian","id":"25260","first_name":"Bastian"},{"first_name":"Bernd","full_name":"Messidat, Bernd","last_name":"Messidat"},{"full_name":"Becker, Markus","last_name":"Becker","first_name":"Markus"},{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"},{"orcid":"https://orcid.org/0000-0002-5950-6618","last_name":"Scheytt","full_name":"Scheytt, J. Christoph","id":"37144","first_name":"J. Christoph"}],"date_created":"2022-12-20T10:48:25Z","date_updated":"2023-02-01T08:12:02Z","citation":{"short":"B. Koppelmann, B. Messidat, M. Becker, W. Müller, J.C. Scheytt, in: Proceedings of the Design and Verification Conference Europe (DVCON Europe), München, 2014.","mla":"Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>, 2014.","bibtex":"@inproceedings{Koppelmann_Messidat_Becker_Müller_Scheytt_2014, place={München}, title={Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}, booktitle={Proceedings of the Design and Verification Conference Europe (DVCON Europe)}, author={Koppelmann, Bastian and Messidat, Bernd and Becker, Markus and Müller, Wolfgang and Scheytt, J. Christoph}, year={2014} }","apa":"Koppelmann, B., Messidat, B., Becker, M., Müller, W., &#38; Scheytt, J. C. (2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>.","ama":"Koppelmann B, Messidat B, Becker M, Müller W, Scheytt JC. Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. In: <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>. ; 2014.","chicago":"Koppelmann, Bastian, Bernd Messidat, Markus Becker, Wolfgang Müller, and J. Christoph Scheytt. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” In <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>. München, 2014.","ieee":"B. Koppelmann, B. Messidat, M. Becker, W. Müller, and J. C. Scheytt, “Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” 2014."},"place":"München","year":"2014"},{"date_updated":"2025-02-26T14:42:18Z","author":[{"last_name":"Koppelmann","id":"25260","full_name":"Koppelmann, Bastian","first_name":"Bastian"},{"full_name":"Messidat, Bernd","last_name":"Messidat","first_name":"Bernd"},{"first_name":"Christoph","full_name":"Kuznik, Christoph","last_name":"Kuznik"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"},{"first_name":"Markus","full_name":"Becker, Markus","last_name":"Becker"},{"id":"37144","full_name":"Scheytt, J. Christoph","last_name":"Scheytt","orcid":"https://orcid.org/0000-0002-5950-6618","first_name":"J. Christoph"}],"date_created":"2022-12-20T10:45:38Z","title":"Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU","place":"München","year":"2014","citation":{"apa":"Koppelmann, B., Messidat, B., Kuznik, C., Müller, W., Becker, M., &#38; Scheytt, J. C. (2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>.","bibtex":"@inproceedings{Koppelmann_Messidat_Kuznik_Müller_Becker_Scheytt_2014, place={München}, title={Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}, booktitle={Proceedings of the Design and Verification Conference Europe (DVCON Europe)}, author={Koppelmann, Bastian and Messidat, Bernd and Kuznik, Christoph and Müller, Wolfgang and Becker, Markus and Scheytt, J. Christoph}, year={2014} }","mla":"Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>, 2014.","short":"B. Koppelmann, B. Messidat, C. Kuznik, W. Müller, M. Becker, J.C. Scheytt, in: Proceedings of the Design and Verification Conference Europe (DVCON Europe), München, 2014.","chicago":"Koppelmann, Bastian, Bernd Messidat, Christoph Kuznik, Wolfgang Müller, Markus Becker, and J. Christoph Scheytt. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” In <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>. München, 2014.","ieee":"B. Koppelmann, B. Messidat, C. Kuznik, W. Müller, M. Becker, and J. C. Scheytt, “Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” 2014.","ama":"Koppelmann B, Messidat B, Kuznik C, Müller W, Becker M, Scheytt JC. Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. In: <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>. ; 2014."},"_id":"34583","department":[{"_id":"58"}],"user_id":"16243","keyword":["System Design","Verification"],"language":[{"iso":"eng"}],"publication":"Proceedings of the Design and Verification Conference Europe (DVCON Europe)","type":"conference","abstract":[{"text":"In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation.","lang":"eng"}],"status":"public"},{"language":[{"iso":"eng"}],"user_id":"5786","_id":"34580","status":"public","abstract":[{"text":"In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation.","lang":"eng"}],"publication":"Proceedings of the Design and Verification Conference Europe ","type":"conference","conference":{"name":"DVCON Europe"},"title":"Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU","date_created":"2022-12-20T10:37:51Z","author":[{"first_name":"Markus","last_name":"Becker","full_name":"Becker, Markus"},{"full_name":"Kuznik, Christoph","last_name":"Kuznik","first_name":"Christoph"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"first_name":"Bastian","last_name":"Koppelmann","full_name":"Koppelmann, Bastian"},{"first_name":"Bernd","last_name":"Messidat","full_name":"Messidat, Bernd"}],"date_updated":"2025-02-26T14:44:30Z","citation":{"ieee":"M. Becker, C. Kuznik, W. Müller, B. Koppelmann, and B. Messidat, “Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” presented at the DVCON Europe, 2014.","chicago":"Becker, Markus, Christoph Kuznik, Wolfgang Müller, Bastian Koppelmann, and Bernd Messidat. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” In <i>Proceedings of the Design and Verification Conference Europe </i>. München, 2014.","ama":"Becker M, Kuznik C, Müller W, Koppelmann B, Messidat B. Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. In: <i>Proceedings of the Design and Verification Conference Europe </i>. ; 2014.","apa":"Becker, M., Kuznik, C., Müller, W., Koppelmann, B., &#38; Messidat, B. (2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. <i>Proceedings of the Design and Verification Conference Europe </i>. DVCON Europe.","mla":"Becker, Markus, et al. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” <i>Proceedings of the Design and Verification Conference Europe </i>, 2014.","short":"M. Becker, C. Kuznik, W. Müller, B. Koppelmann, B. Messidat, in: Proceedings of the Design and Verification Conference Europe , München, 2014.","bibtex":"@inproceedings{Becker_Kuznik_Müller_Koppelmann_Messidat_2014, place={München}, title={Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}, booktitle={Proceedings of the Design and Verification Conference Europe }, author={Becker, Markus and Kuznik, Christoph and Müller, Wolfgang and Koppelmann, Bastian and Messidat, Bernd}, year={2014} }"},"place":"München","year":"2014"},{"author":[{"first_name":"Bastian","full_name":"Koppelmann, Bastian","id":"25260","last_name":"Koppelmann"},{"last_name":"Messidat","full_name":"Messidat, Bernd","first_name":"Bernd"},{"first_name":"Markus","last_name":"Becker","full_name":"Becker, Markus"},{"last_name":"Kuznik","full_name":"Kuznik, Christoph","first_name":"Christoph"},{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"},{"first_name":"J. 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