[{"citation":{"ama":"Koppelmann B, Messidat B, Becker M, Müller W, Scheytt JC. Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. In: <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>. ; 2014.","ieee":"B. Koppelmann, B. Messidat, M. Becker, W. Müller, and J. C. Scheytt, “Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” 2014.","chicago":"Koppelmann, Bastian, Bernd Messidat, Markus Becker, Wolfgang Müller, and J. Christoph Scheytt. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” In <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>. München, 2014.","bibtex":"@inproceedings{Koppelmann_Messidat_Becker_Müller_Scheytt_2014, place={München}, title={Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}, booktitle={Proceedings of the Design and Verification Conference Europe (DVCON Europe)}, author={Koppelmann, Bastian and Messidat, Bernd and Becker, Markus and Müller, Wolfgang and Scheytt, J. Christoph}, year={2014} }","short":"B. Koppelmann, B. Messidat, M. Becker, W. Müller, J.C. Scheytt, in: Proceedings of the Design and Verification Conference Europe (DVCON Europe), München, 2014.","mla":"Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>, 2014.","apa":"Koppelmann, B., Messidat, B., Becker, M., Müller, W., &#38; Scheytt, J. C. (2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>."},"year":"2014","place":"München","title":"Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU","date_created":"2022-12-20T10:48:25Z","author":[{"last_name":"Koppelmann","full_name":"Koppelmann, Bastian","id":"25260","first_name":"Bastian"},{"first_name":"Bernd","last_name":"Messidat","full_name":"Messidat, Bernd"},{"last_name":"Becker","full_name":"Becker, Markus","first_name":"Markus"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"first_name":"J. Christoph","last_name":"Scheytt","orcid":"https://orcid.org/0000-0002-5950-6618","full_name":"Scheytt, J. Christoph","id":"37144"}],"date_updated":"2023-02-01T08:12:02Z","status":"public","abstract":[{"text":"In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation.","lang":"eng"}],"type":"conference","publication":"Proceedings of the Design and Verification Conference Europe (DVCON Europe)","language":[{"iso":"eng"}],"keyword":["System Design","Verification"],"user_id":"15931","department":[{"_id":"58"}],"_id":"34585"},{"place":"München","year":"2014","citation":{"apa":"Koppelmann, B., Messidat, B., Kuznik, C., Müller, W., Becker, M., &#38; Scheytt, J. C. (2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>.","bibtex":"@inproceedings{Koppelmann_Messidat_Kuznik_Müller_Becker_Scheytt_2014, place={München}, title={Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}, booktitle={Proceedings of the Design and Verification Conference Europe (DVCON Europe)}, author={Koppelmann, Bastian and Messidat, Bernd and Kuznik, Christoph and Müller, Wolfgang and Becker, Markus and Scheytt, J. Christoph}, year={2014} }","mla":"Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>, 2014.","short":"B. Koppelmann, B. Messidat, C. Kuznik, W. Müller, M. Becker, J.C. Scheytt, in: Proceedings of the Design and Verification Conference Europe (DVCON Europe), München, 2014.","ieee":"B. Koppelmann, B. Messidat, C. Kuznik, W. Müller, M. Becker, and J. C. Scheytt, “Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” 2014.","chicago":"Koppelmann, Bastian, Bernd Messidat, Christoph Kuznik, Wolfgang Müller, Markus Becker, and J. Christoph Scheytt. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” In <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>. München, 2014.","ama":"Koppelmann B, Messidat B, Kuznik C, Müller W, Becker M, Scheytt JC. Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. In: <i>Proceedings of the Design and Verification Conference Europe (DVCON Europe)</i>. ; 2014."},"date_updated":"2025-02-26T14:42:18Z","date_created":"2022-12-20T10:45:38Z","author":[{"last_name":"Koppelmann","id":"25260","full_name":"Koppelmann, Bastian","first_name":"Bastian"},{"full_name":"Messidat, Bernd","last_name":"Messidat","first_name":"Bernd"},{"first_name":"Christoph","full_name":"Kuznik, Christoph","last_name":"Kuznik"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"first_name":"Markus","last_name":"Becker","full_name":"Becker, Markus"},{"full_name":"Scheytt, J. Christoph","id":"37144","orcid":"https://orcid.org/0000-0002-5950-6618","last_name":"Scheytt","first_name":"J. Christoph"}],"title":"Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU","type":"conference","publication":"Proceedings of the Design and Verification Conference Europe (DVCON Europe)","abstract":[{"text":"In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation.","lang":"eng"}],"status":"public","_id":"34583","user_id":"16243","department":[{"_id":"58"}],"keyword":["System Design","Verification"],"language":[{"iso":"eng"}]},{"citation":{"apa":"Becker, M., Kuznik, C., Müller, W., Koppelmann, B., &#38; Messidat, B. (2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. <i>Proceedings of the Design and Verification Conference Europe </i>. DVCON Europe.","bibtex":"@inproceedings{Becker_Kuznik_Müller_Koppelmann_Messidat_2014, place={München}, title={Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}, booktitle={Proceedings of the Design and Verification Conference Europe }, author={Becker, Markus and Kuznik, Christoph and Müller, Wolfgang and Koppelmann, Bastian and Messidat, Bernd}, year={2014} }","short":"M. Becker, C. Kuznik, W. Müller, B. Koppelmann, B. Messidat, in: Proceedings of the Design and Verification Conference Europe , München, 2014.","mla":"Becker, Markus, et al. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” <i>Proceedings of the Design and Verification Conference Europe </i>, 2014.","ieee":"M. Becker, C. Kuznik, W. Müller, B. Koppelmann, and B. Messidat, “Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” presented at the DVCON Europe, 2014.","chicago":"Becker, Markus, Christoph Kuznik, Wolfgang Müller, Bastian Koppelmann, and Bernd Messidat. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” In <i>Proceedings of the Design and Verification Conference Europe </i>. München, 2014.","ama":"Becker M, Kuznik C, Müller W, Koppelmann B, Messidat B. Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. In: <i>Proceedings of the Design and Verification Conference Europe </i>. ; 2014."},"place":"München","year":"2014","author":[{"first_name":"Markus","full_name":"Becker, Markus","last_name":"Becker"},{"first_name":"Christoph","full_name":"Kuznik, Christoph","last_name":"Kuznik"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"},{"first_name":"Bastian","last_name":"Koppelmann","full_name":"Koppelmann, Bastian"},{"first_name":"Bernd","last_name":"Messidat","full_name":"Messidat, Bernd"}],"date_created":"2022-12-20T10:37:51Z","date_updated":"2025-02-26T14:44:30Z","conference":{"name":"DVCON Europe"},"title":"Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU","publication":"Proceedings of the Design and Verification Conference Europe ","type":"conference","status":"public","abstract":[{"lang":"eng","text":"In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation."}],"user_id":"5786","_id":"34580","language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"_id":"25117","user_id":"5786","department":[{"_id":"672"}],"status":"public","type":"journal_article","publication":"Design and Verification Conference (DVCON EUROPE)","title":"Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU","date_updated":"2025-02-26T14:44:48Z","author":[{"full_name":"Koppelmann, Bastian","id":"25260","last_name":"Koppelmann","first_name":"Bastian"},{"first_name":"Bernd","last_name":"Messidat","full_name":"Messidat, Bernd"},{"full_name":"Becker, Markus","last_name":"Becker","first_name":"Markus"},{"last_name":"Kuznik","full_name":"Kuznik, Christoph","first_name":"Christoph"},{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"},{"full_name":"Scheytt, J. Christoph","id":"37144","orcid":"https://orcid.org/0000-0002-5950-6618","last_name":"Scheytt","first_name":"J. Christoph"}],"date_created":"2021-09-29T10:47:35Z","year":"2014","citation":{"ieee":"B. Koppelmann, B. Messidat, M. Becker, C. Kuznik, W. Müller, and J. C. Scheytt, “Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” <i>Design and Verification Conference (DVCON EUROPE)</i>, 2014.","chicago":"Koppelmann, Bastian, Bernd Messidat, Markus Becker, Christoph Kuznik, Wolfgang Müller, and J. Christoph Scheytt. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” <i>Design and Verification Conference (DVCON EUROPE)</i>, 2014.","ama":"Koppelmann B, Messidat B, Becker M, Kuznik C, Müller W, Scheytt JC. Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. <i>Design and Verification Conference (DVCON EUROPE)</i>. Published online 2014.","bibtex":"@article{Koppelmann_Messidat_Becker_Kuznik_Müller_Scheytt_2014, title={Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}, journal={Design and Verification Conference (DVCON EUROPE)}, author={Koppelmann, Bastian and Messidat, Bernd and Becker, Markus and Kuznik, Christoph and Müller, Wolfgang and Scheytt, J. Christoph}, year={2014} }","mla":"Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” <i>Design and Verification Conference (DVCON EUROPE)</i>, 2014.","short":"B. Koppelmann, B. Messidat, M. Becker, C. Kuznik, W. Müller, J.C. Scheytt, Design and Verification Conference (DVCON EUROPE) (2014).","apa":"Koppelmann, B., Messidat, B., Becker, M., Kuznik, C., Müller, W., &#38; Scheytt, J. C. (2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. <i>Design and Verification Conference (DVCON EUROPE)</i>."}},{"status":"public","publication":"Design, Automation and Test in Europe DATE, University Booth, Dresden ","type":"journal_article","language":[{"iso":"eng"}],"_id":"25162","department":[{"_id":"672"}],"user_id":"5786","year":"2014","citation":{"ama":"Kuznik C, Müller W. Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure. <i>Design, Automation and Test in Europe DATE, University Booth, Dresden </i>. Published online 2014.","chicago":"Kuznik, Christoph, and Wolfgang Müller. “Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure.” <i>Design, Automation and Test in Europe DATE, University Booth, Dresden </i>, 2014.","ieee":"C. Kuznik and W. Müller, “Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure,” <i>Design, Automation and Test in Europe DATE, University Booth, Dresden </i>, 2014.","bibtex":"@article{Kuznik_Müller_2014, title={Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure}, journal={Design, Automation and Test in Europe DATE, University Booth, Dresden }, author={Kuznik, Christoph and Müller, Wolfgang}, year={2014} }","short":"C. Kuznik, W. Müller, Design, Automation and Test in Europe DATE, University Booth, Dresden  (2014).","mla":"Kuznik, Christoph, and Wolfgang Müller. “Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure.” <i>Design, Automation and Test in Europe DATE, University Booth, Dresden </i>, 2014.","apa":"Kuznik, C., &#38; Müller, W. (2014). Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure. <i>Design, Automation and Test in Europe DATE, University Booth, Dresden </i>."},"title":"Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure","date_updated":"2025-02-26T14:45:04Z","date_created":"2021-09-30T10:05:28Z","author":[{"full_name":"Kuznik, Christoph","last_name":"Kuznik","first_name":"Christoph"},{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"}]},{"publication":"Design Automation Conference (DAC)","type":"conference","status":"public","_id":"25169","department":[{"_id":"672"}],"user_id":"5786","language":[{"iso":"eng"}],"year":"2014","citation":{"chicago":"Oetjens, Jan-Hendrik, Markus Becker, Christoph Kuznik, and Wolfgang Müller. “Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges.” In <i>Design Automation Conference (DAC)</i>, 2014.","ieee":"J.-H. Oetjens, M. Becker, C. Kuznik, and W. Müller, “Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges,” 2014.","ama":"Oetjens J-H, Becker M, Kuznik C, Müller W. Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges. In: <i>Design Automation Conference (DAC)</i>. ; 2014.","apa":"Oetjens, J.-H., Becker, M., Kuznik, C., &#38; Müller, W. (2014). Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges. <i>Design Automation Conference (DAC)</i>.","bibtex":"@inproceedings{Oetjens_Becker_Kuznik_Müller_2014, title={Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges}, booktitle={Design Automation Conference (DAC)}, author={Oetjens, Jan-Hendrik and Becker, Markus and Kuznik, Christoph and Müller, Wolfgang}, year={2014} }","mla":"Oetjens, Jan-Hendrik, et al. “Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges.” <i>Design Automation Conference (DAC)</i>, 2014.","short":"J.-H. Oetjens, M. Becker, C. Kuznik, W. Müller, in: Design Automation Conference (DAC), 2014."},"date_updated":"2025-02-26T14:45:29Z","author":[{"first_name":"Jan-Hendrik","full_name":"Oetjens, Jan-Hendrik","last_name":"Oetjens"},{"first_name":"Markus","full_name":"Becker, Markus","last_name":"Becker"},{"first_name":"Christoph","last_name":"Kuznik","full_name":"Kuznik, Christoph"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"}],"date_created":"2021-09-30T11:01:14Z","title":"Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges"},{"type":"conference","publication":"Proceedings of AVICPS 2013, Dez. 2013 IEEE Computer Society,","status":"public","_id":"25270","user_id":"21240","department":[{"_id":"672"}],"language":[{"iso":"eng"}],"year":"2013","citation":{"apa":"Joy, M. tech. M. M., Müller, W., &#38; Rammig, F.-J. (2013). Early Phase Memory Leak Detection in Embedded Software Designs with Virtual Memory Management Model. <i>Proceedings of AVICPS 2013, Dez. 2013 IEEE Computer Society,</i>.","mla":"Joy, M. tech. Mabel Mary, et al. “Early Phase Memory Leak Detection in Embedded Software Designs with Virtual Memory Management Model.” <i>Proceedings of AVICPS 2013, Dez. 2013 IEEE Computer Society,</i> Linköping University Electronic Press, 2013.","bibtex":"@inproceedings{Joy_Müller_Rammig_2013, title={Early Phase Memory Leak Detection in Embedded Software Designs with Virtual Memory Management Model}, booktitle={Proceedings of AVICPS 2013, Dez. 2013 IEEE Computer Society,}, publisher={Linköping University Electronic Press}, author={Joy, M. tech. Mabel Mary and Müller, Wolfgang and Rammig, Franz-Josef}, year={2013} }","short":"M. tech. M.M. Joy, W. Müller, F.-J. Rammig, in: Proceedings of AVICPS 2013, Dez. 2013 IEEE Computer Society, Linköping University Electronic Press, 2013.","chicago":"Joy, M. tech. Mabel Mary, Wolfgang Müller, and Franz-Josef Rammig. “Early Phase Memory Leak Detection in Embedded Software Designs with Virtual Memory Management Model.” In <i>Proceedings of AVICPS 2013, Dez. 2013 IEEE Computer Society,</i>. Linköping University Electronic Press, 2013.","ieee":"M. tech. M. M. Joy, W. Müller, and F.-J. Rammig, “Early Phase Memory Leak Detection in Embedded Software Designs with Virtual Memory Management Model,” 2013.","ama":"Joy M tech. MM, Müller W, Rammig F-J. Early Phase Memory Leak Detection in Embedded Software Designs with Virtual Memory Management Model. In: <i>Proceedings of AVICPS 2013, Dez. 2013 IEEE Computer Society,</i>. Linköping University Electronic Press; 2013."},"publisher":"Linköping University Electronic Press","date_updated":"2022-01-06T06:56:58Z","author":[{"full_name":"Joy, M. tech. Mabel Mary","last_name":"Joy","first_name":"M. tech. Mabel Mary"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"last_name":"Rammig","full_name":"Rammig, Franz-Josef","first_name":"Franz-Josef"}],"date_created":"2021-10-04T08:25:24Z","title":"Early Phase Memory Leak Detection in Embedded Software Designs with Virtual Memory Management Model"},{"language":[{"iso":"eng"}],"department":[{"_id":"672"}],"user_id":"21240","_id":"25271","status":"public","publication":"Proceedings of International Conference on Applied Computing (AC)","type":"conference","title":"AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL- TIME SYSTEM ON MULTI-CORE PROCESSORS","author":[{"full_name":"He, Da","last_name":"He","first_name":"Da"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"}],"date_created":"2021-10-04T08:30:39Z","date_updated":"2022-01-06T06:56:58Z","citation":{"chicago":"He, Da, and Wolfgang Müller. “AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL- TIME SYSTEM ON MULTI-CORE PROCESSORS.” In <i>Proceedings of International Conference on Applied Computing (AC)</i>, 2013.","ieee":"D. He and W. Müller, “AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL- TIME SYSTEM ON MULTI-CORE PROCESSORS,” 2013.","ama":"He D, Müller W. AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL- TIME SYSTEM ON MULTI-CORE PROCESSORS. In: <i>Proceedings of International Conference on Applied Computing (AC)</i>. ; 2013.","apa":"He, D., &#38; Müller, W. (2013). AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL- TIME SYSTEM ON MULTI-CORE PROCESSORS. <i>Proceedings of International Conference on Applied Computing (AC)</i>.","mla":"He, Da, and Wolfgang Müller. “AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL- TIME SYSTEM ON MULTI-CORE PROCESSORS.” <i>Proceedings of International Conference on Applied Computing (AC)</i>, 2013.","short":"D. He, W. Müller, in: Proceedings of International Conference on Applied Computing (AC), 2013.","bibtex":"@inproceedings{He_Müller_2013, title={AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL- TIME SYSTEM ON MULTI-CORE PROCESSORS}, booktitle={Proceedings of International Conference on Applied Computing (AC)}, author={He, Da and Müller, Wolfgang}, year={2013} }"},"year":"2013"},{"date_updated":"2022-01-06T06:56:59Z","date_created":"2021-10-04T11:15:10Z","author":[{"first_name":"Fabian","last_name":"Mischkalla","full_name":"Mischkalla, Fabian"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"}],"title":" Efficient Power Intent Validation Using Loosely-Timed Simulation Models","year":"2013","citation":{"ieee":"F. Mischkalla and W. Müller, “ Efficient Power Intent Validation Using Loosely-Timed Simulation Models,” 2013.","chicago":"Mischkalla, Fabian, and Wolfgang Müller. “ Efficient Power Intent Validation Using Loosely-Timed Simulation Models.” In <i> 23rd International Workshop on Power And Timing Modeling, Optimization and Simulation, Sep. 2013</i>, 2013.","ama":"Mischkalla F, Müller W.  Efficient Power Intent Validation Using Loosely-Timed Simulation Models. In: <i> 23rd International Workshop on Power And Timing Modeling, Optimization and Simulation, Sep. 2013</i>. ; 2013.","bibtex":"@inproceedings{Mischkalla_Müller_2013, title={ Efficient Power Intent Validation Using Loosely-Timed Simulation Models}, booktitle={ 23rd International Workshop on Power And Timing Modeling, Optimization and Simulation, Sep. 2013}, author={Mischkalla, Fabian and Müller, Wolfgang}, year={2013} }","short":"F. Mischkalla, W. Müller, in:  23rd International Workshop on Power And Timing Modeling, Optimization and Simulation, Sep. 2013, 2013.","mla":"Mischkalla, Fabian, and Wolfgang Müller. “ Efficient Power Intent Validation Using Loosely-Timed Simulation Models.” <i> 23rd International Workshop on Power And Timing Modeling, Optimization and Simulation, Sep. 2013</i>, 2013.","apa":"Mischkalla, F., &#38; Müller, W. (2013).  Efficient Power Intent Validation Using Loosely-Timed Simulation Models. <i> 23rd International Workshop on Power And Timing Modeling, Optimization and Simulation, Sep. 2013</i>."},"_id":"25284","department":[{"_id":"672"}],"user_id":"21240","language":[{"iso":"eng"}],"publication":" 23rd International Workshop on Power And Timing Modeling, Optimization and Simulation, Sep. 2013","type":"conference","status":"public"},{"user_id":"21240","department":[{"_id":"672"}],"_id":"25291","language":[{"iso":"eng"}],"type":"conference","publication":"16th IEEE Computer Society Symposium on Object/Component/Service-oriented Real-time Distributed Computing","status":"public","author":[{"last_name":"Becker","full_name":"Becker, Markus","first_name":"Markus"},{"full_name":"Kiffmeier, Ulrich","last_name":"Kiffmeier","first_name":"Ulrich"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"}],"date_created":"2021-10-04T12:20:10Z","date_updated":"2022-01-06T06:56:59Z","title":"HeroeS: Virtual Platform Driven Integration of Heterogeneous Software Components for Multi-Core Real-Time Architectures","citation":{"bibtex":"@inproceedings{Becker_Kiffmeier_Müller_2013, title={HeroeS: Virtual Platform Driven Integration of Heterogeneous Software Components for Multi-Core Real-Time Architectures}, booktitle={16th IEEE Computer Society Symposium on Object/Component/Service-oriented Real-time Distributed Computing}, author={Becker, Markus and Kiffmeier, Ulrich and Müller, Wolfgang}, year={2013} }","mla":"Becker, Markus, et al. “HeroeS: Virtual Platform Driven Integration of Heterogeneous Software Components for Multi-Core Real-Time Architectures.” <i>16th IEEE Computer Society Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing</i>, 2013.","short":"M. Becker, U. Kiffmeier, W. Müller, in: 16th IEEE Computer Society Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2013.","apa":"Becker, M., Kiffmeier, U., &#38; Müller, W. (2013). HeroeS: Virtual Platform Driven Integration of Heterogeneous Software Components for Multi-Core Real-Time Architectures. <i>16th IEEE Computer Society Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing</i>.","ieee":"M. Becker, U. Kiffmeier, and W. Müller, “HeroeS: Virtual Platform Driven Integration of Heterogeneous Software Components for Multi-Core Real-Time Architectures,” 2013.","chicago":"Becker, Markus, Ulrich Kiffmeier, and Wolfgang Müller. “HeroeS: Virtual Platform Driven Integration of Heterogeneous Software Components for Multi-Core Real-Time Architectures.” In <i>16th IEEE Computer Society Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing</i>, 2013.","ama":"Becker M, Kiffmeier U, Müller W. HeroeS: Virtual Platform Driven Integration of Heterogeneous Software Components for Multi-Core Real-Time Architectures. In: <i>16th IEEE Computer Society Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing</i>. ; 2013."},"year":"2013"},{"year":"2013","citation":{"ama":"Kuznik C, F. S. Oliveira M, Müller W. SystemC Verification Components - An enhanced OVM/UVM for SystemC. In: <i>EdaWorkshop 13</i>. ; 2013.","chicago":"Kuznik, Christoph, Marcio F. S. Oliveira, and Wolfgang Müller. “SystemC Verification Components - An Enhanced OVM/UVM for SystemC.” In <i>EdaWorkshop 13</i>, 2013.","ieee":"C. Kuznik, M. F. S. Oliveira, and W. Müller, “SystemC Verification Components - An enhanced OVM/UVM for SystemC,” Mrz. 2013 - Poster, 2013.","apa":"Kuznik, C., F. S. Oliveira, M., &#38; Müller, W. (2013). SystemC Verification Components - An enhanced OVM/UVM for SystemC. <i>EdaWorkshop 13</i>.","short":"C. Kuznik, M. F. S. Oliveira, W. Müller, in: EdaWorkshop 13, 2013.","bibtex":"@inproceedings{Kuznik_F. S. Oliveira_Müller_2013, title={SystemC Verification Components - An enhanced OVM/UVM for SystemC}, booktitle={edaWorkshop 13}, author={Kuznik, Christoph and F. S. Oliveira, Marcio and Müller, Wolfgang}, year={2013} }","mla":"Kuznik, Christoph, et al. “SystemC Verification Components - An Enhanced OVM/UVM for SystemC.” <i>EdaWorkshop 13</i>, 2013."},"date_updated":"2022-01-06T06:57:07Z","author":[{"first_name":"Christoph","full_name":"Kuznik, Christoph","last_name":"Kuznik"},{"first_name":"Marcio","full_name":"F. S. Oliveira, Marcio","last_name":"F. S. Oliveira"},{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"}],"date_created":"2021-10-07T07:58:38Z","title":"SystemC Verification Components - An enhanced OVM/UVM for SystemC","conference":{"location":"Mrz. 2013 - Poster"},"publication":"edaWorkshop 13","type":"conference","status":"public","_id":"25606","department":[{"_id":"672"}],"user_id":"21240","language":[{"iso":"eng"}]},{"year":"2013","citation":{"chicago":"Mischkalla, Fabian, and Wolfgang Müller. “Funktionale Verifikation von Low-Power Designs unter Verwendung Virtueller Prototypen.” In <i>Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)</i>, 2013.","ieee":"F. Mischkalla and W. Müller, “Funktionale Verifikation von Low-Power Designs unter Verwendung Virtueller Prototypen,” 2013.","ama":"Mischkalla F, Müller W. Funktionale Verifikation von Low-Power Designs unter Verwendung Virtueller Prototypen. In: <i>Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)</i>. ; 2013.","apa":"Mischkalla, F., &#38; Müller, W. (2013). Funktionale Verifikation von Low-Power Designs unter Verwendung Virtueller Prototypen. <i>Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)</i>.","mla":"Mischkalla, Fabian, and Wolfgang Müller. “Funktionale Verifikation von Low-Power Designs unter Verwendung Virtueller Prototypen.” <i>Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)</i>, 2013.","bibtex":"@inproceedings{Mischkalla_Müller_2013, title={Funktionale Verifikation von Low-Power Designs unter Verwendung Virtueller Prototypen}, booktitle={Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)}, author={Mischkalla, Fabian and Müller, Wolfgang}, year={2013} }","short":"F. Mischkalla, W. Müller, in: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013."},"title":"Funktionale Verifikation von Low-Power Designs unter Verwendung Virtueller Prototypen","date_updated":"2022-01-06T06:57:08Z","date_created":"2021-10-07T08:27:55Z","author":[{"first_name":"Fabian","last_name":"Mischkalla","full_name":"Mischkalla, Fabian"},{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"}],"status":"public","publication":"Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)","type":"conference","language":[{"iso":"ger"}],"_id":"25612","department":[{"_id":"672"}],"user_id":"21240"},{"date_created":"2021-10-07T08:31:07Z","author":[{"full_name":"Kuznik, Christoph","last_name":"Kuznik","first_name":"Christoph"},{"first_name":"Marcio","full_name":"F. S. Oliveira, Marcio","last_name":"F. S. Oliveira"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"}],"date_updated":"2022-01-06T06:57:08Z","title":"SC OVM: An Advanced SystemC Library for OVM-based Verification","citation":{"bibtex":"@inproceedings{Kuznik_F. S. Oliveira_Müller_2013, title={SC OVM: An Advanced SystemC Library for OVM-based Verification}, booktitle={Open SANITAS SystemC Verification Workshop}, author={Kuznik, Christoph and F. S. Oliveira, Marcio and Müller, Wolfgang}, year={2013} }","mla":"Kuznik, Christoph, et al. “SC OVM: An Advanced SystemC Library for OVM-Based Verification.” <i>Open SANITAS SystemC Verification Workshop</i>, 2013.","short":"C. Kuznik, M. F. S. Oliveira, W. Müller, in: Open SANITAS SystemC Verification Workshop, 2013.","apa":"Kuznik, C., F. S. Oliveira, M., &#38; Müller, W. (2013). SC OVM: An Advanced SystemC Library for OVM-based Verification. <i>Open SANITAS SystemC Verification Workshop</i>.","ieee":"C. Kuznik, M. F. S. Oliveira, and W. Müller, “SC OVM: An Advanced SystemC Library for OVM-based Verification,” 2013.","chicago":"Kuznik, Christoph, Marcio F. S. Oliveira, and Wolfgang Müller. “SC OVM: An Advanced SystemC Library for OVM-Based Verification.” In <i>Open SANITAS SystemC Verification Workshop</i>, 2013.","ama":"Kuznik C, F. S. Oliveira M, Müller W. SC OVM: An Advanced SystemC Library for OVM-based Verification. In: <i>Open SANITAS SystemC Verification Workshop</i>. ; 2013."},"year":"2013","department":[{"_id":"672"}],"user_id":"21240","_id":"25614","language":[{"iso":"eng"}],"publication":"Open SANITAS SystemC Verification Workshop","type":"conference","status":"public"},{"citation":{"ama":"Engels G, Gerth C, Kleinjohann L, Kleinjohann B, Müller W.  Informationstechnik spart Ressourcen. <i>ForschungsForum Paderborn </i>. 2013.","ieee":"G. Engels, C. Gerth, L. Kleinjohann, B. Kleinjohann, and W. Müller, “ Informationstechnik spart Ressourcen,” <i>ForschungsForum Paderborn </i>, 2013.","chicago":"Engels, Gregor, Christian Gerth, Lisa Kleinjohann, Bernd Kleinjohann, and Wolfgang Müller. “ Informationstechnik spart Ressourcen.” <i>ForschungsForum Paderborn </i>, 2013.","short":"G. Engels, C. Gerth, L. Kleinjohann, B. Kleinjohann, W. Müller, ForschungsForum Paderborn  (2013).","bibtex":"@article{Engels_Gerth_Kleinjohann_Kleinjohann_Müller_2013, title={ Informationstechnik spart Ressourcen}, journal={ForschungsForum Paderborn }, author={Engels, Gregor and Gerth, Christian and Kleinjohann, Lisa and Kleinjohann, Bernd and Müller, Wolfgang}, year={2013} }","mla":"Engels, Gregor, et al. “ Informationstechnik spart Ressourcen.” <i>ForschungsForum Paderborn </i>, 2013.","apa":"Engels, G., Gerth, C., Kleinjohann, L., Kleinjohann, B., &#38; Müller, W. (2013).  Informationstechnik spart Ressourcen. <i>ForschungsForum Paderborn </i>."},"year":"2013","title":" Informationstechnik spart Ressourcen","date_created":"2021-10-07T08:34:47Z","author":[{"full_name":"Engels, Gregor","id":"107","last_name":"Engels","first_name":"Gregor"},{"full_name":"Gerth, Christian","last_name":"Gerth","first_name":"Christian"},{"first_name":"Lisa","last_name":"Kleinjohann","full_name":"Kleinjohann, Lisa","id":"15588"},{"full_name":"Kleinjohann, Bernd","last_name":"Kleinjohann","first_name":"Bernd"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"}],"date_updated":"2022-01-06T06:57:08Z","status":"public","publication":"ForschungsForum Paderborn ","type":"newspaper_article","language":[{"iso":"ger"}],"department":[{"_id":"672"}],"user_id":"21240","_id":"25615","publication_date":"2013-02-01"},{"date_updated":"2022-01-06T06:57:08Z","author":[{"first_name":"Christoph","last_name":"Kuznik","full_name":"Kuznik, Christoph"},{"first_name":"Marcio F.","last_name":"Oliveira","full_name":"Oliveira, Marcio F."},{"first_name":"Bertrand","full_name":"Defo, Bertrand","last_name":"Defo"},{"last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243","first_name":"Wolfgang"}],"date_created":"2021-10-07T08:51:16Z","title":"Systematic Application of UCIS to Improve the Automation on Verification Closure","year":"2013","citation":{"apa":"Kuznik, C., Oliveira, M. F., Defo, B., &#38; Müller, W. (2013). Systematic Application of UCIS to Improve the Automation on Verification Closure. <i>Proceedings of DVCON</i>.","short":"C. Kuznik, M.F. Oliveira, B. Defo, W. Müller, in: Proceedings of DVCON, 2013.","bibtex":"@inproceedings{Kuznik_Oliveira_Defo_Müller_2013, title={Systematic Application of UCIS to Improve the Automation on Verification Closure}, booktitle={Proceedings of DVCON}, author={Kuznik, Christoph and Oliveira, Marcio F. and Defo, Bertrand and Müller, Wolfgang}, year={2013} }","mla":"Kuznik, Christoph, et al. “Systematic Application of UCIS to Improve the Automation on Verification Closure.” <i>Proceedings of DVCON</i>, 2013.","chicago":"Kuznik, Christoph, Marcio F. Oliveira, Bertrand Defo, and Wolfgang Müller. “Systematic Application of UCIS to Improve the Automation on Verification Closure.” In <i>Proceedings of DVCON</i>, 2013.","ieee":"C. Kuznik, M. F. Oliveira, B. Defo, and W. Müller, “Systematic Application of UCIS to Improve the Automation on Verification Closure,” 2013.","ama":"Kuznik C, Oliveira MF, Defo B, Müller W. Systematic Application of UCIS to Improve the Automation on Verification Closure. In: <i>Proceedings of DVCON</i>. ; 2013."},"_id":"25620","user_id":"21240","department":[{"_id":"672"}],"language":[{"iso":"eng"}],"type":"conference","publication":"Proceedings of DVCON","status":"public"},{"status":"public","type":"conference","publication":"International Embedded Systems Symposium (IESS) 2013","language":[{"iso":"eng"}],"user_id":"21240","department":[{"_id":"672"}],"_id":"25632","citation":{"bibtex":"@inproceedings{Klobedanz_Jatzkowski_Rettberg_Müller_2013, title={Fault-Tolerant Deployment of Real-Time Software in AUTOSAR ECU Networks}, booktitle={International Embedded Systems Symposium (IESS) 2013}, publisher={Springer}, author={Klobedanz, Kay and Jatzkowski, Jan and Rettberg, Achim and Müller, Wolfgang}, year={2013} }","mla":"Klobedanz, Kay, et al. “Fault-Tolerant Deployment of Real-Time Software in AUTOSAR ECU Networks.” <i>International Embedded Systems Symposium (IESS) 2013</i>, Springer, 2013.","short":"K. Klobedanz, J. Jatzkowski, A. Rettberg, W. Müller, in: International Embedded Systems Symposium (IESS) 2013, Springer, 2013.","apa":"Klobedanz, K., Jatzkowski, J., Rettberg, A., &#38; Müller, W. (2013). Fault-Tolerant Deployment of Real-Time Software in AUTOSAR ECU Networks. <i>International Embedded Systems Symposium (IESS) 2013</i>.","ama":"Klobedanz K, Jatzkowski J, Rettberg A, Müller W. Fault-Tolerant Deployment of Real-Time Software in AUTOSAR ECU Networks. In: <i>International Embedded Systems Symposium (IESS) 2013</i>. Springer; 2013.","ieee":"K. Klobedanz, J. Jatzkowski, A. Rettberg, and W. Müller, “Fault-Tolerant Deployment of Real-Time Software in AUTOSAR ECU Networks,” 2013.","chicago":"Klobedanz, Kay, Jan Jatzkowski, Achim Rettberg, and Wolfgang Müller. “Fault-Tolerant Deployment of Real-Time Software in AUTOSAR ECU Networks.” In <i>International Embedded Systems Symposium (IESS) 2013</i>. Springer, 2013."},"year":"2013","title":"Fault-Tolerant Deployment of Real-Time Software in AUTOSAR ECU Networks","date_created":"2021-10-07T09:46:48Z","author":[{"last_name":"Klobedanz","full_name":"Klobedanz, Kay","first_name":"Kay"},{"last_name":"Jatzkowski","full_name":"Jatzkowski, Jan","first_name":"Jan"},{"first_name":"Achim","last_name":"Rettberg","full_name":"Rettberg, Achim"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"}],"date_updated":"2022-01-06T06:57:08Z","publisher":"Springer"},{"title":" A heuristic energy-aware approach for hard real-time systems on multi-core platforms","date_updated":"2022-01-06T06:57:12Z","date_created":"2021-10-07T09:49:15Z","author":[{"last_name":"He","full_name":"He, Da","first_name":"Da"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"}],"year":"2013","page":"845-857","citation":{"apa":"He, D., &#38; Müller, W. (2013).  A heuristic energy-aware approach for hard real-time systems on multi-core platforms. <i>Microprocessors and Microsystems - Embedded Hardware Design 37(6-7)</i>, 845–857.","mla":"He, Da, and Wolfgang Müller. “ A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms.” <i>Microprocessors and Microsystems - Embedded Hardware Design 37(6-7)</i>, 2013, pp. 845–57.","short":"D. He, W. Müller, Microprocessors and Microsystems - Embedded Hardware Design 37(6-7) (2013) 845–857.","bibtex":"@article{He_Müller_2013, title={ A heuristic energy-aware approach for hard real-time systems on multi-core platforms}, journal={Microprocessors and Microsystems - Embedded Hardware Design 37(6-7)}, author={He, Da and Müller, Wolfgang}, year={2013}, pages={845–857} }","ama":"He D, Müller W.  A heuristic energy-aware approach for hard real-time systems on multi-core platforms. <i>Microprocessors and Microsystems - Embedded Hardware Design 37(6-7)</i>. Published online 2013:845-857.","chicago":"He, Da, and Wolfgang Müller. “ A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms.” <i>Microprocessors and Microsystems - Embedded Hardware Design 37(6-7)</i>, 2013, 845–57.","ieee":"D. He and W. Müller, “ A heuristic energy-aware approach for hard real-time systems on multi-core platforms,” <i>Microprocessors and Microsystems - Embedded Hardware Design 37(6-7)</i>, pp. 845–857, 2013."},"language":[{"iso":"eng"}],"_id":"25740","department":[{"_id":"672"}],"user_id":"21240","status":"public","publication":"Microprocessors and Microsystems - Embedded Hardware Design 37(6-7)","type":"journal_article"},{"type":"book_chapter","publication":"Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future","status":"public","_id":"25743","user_id":"21240","department":[{"_id":"672"}],"language":[{"iso":"eng"}],"year":"2013","place":"Heidelberg","citation":{"short":"H. Anacker, M. Dellnitz, K. Flaßkamp, S. Grösbrink, P. Hartmann, C. Heinzemann, C. Horenkamp, L. Kleinjohann, B. Kleinjohann, S. Korf, M. Krüger, W. Müller, S. Ober-Blöbaum, S. Oberthür, M. Porrmann, C. Priesterjahn, W. Radkowski, C. Rasche, J. Rieke, M. Ringkamp, K. Stahl, D. Steenken, J. Stöcklein, R. Timmermann, A. Trächtler, K. Witting, T. Xie, S. Ziegert, in: Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future, Springer-Verlag, Heidelberg, 2013, pp. 187–356.","bibtex":"@inbook{Anacker_Dellnitz_Flaßkamp_Grösbrink_Hartmann_Heinzemann_Horenkamp_Kleinjohann_Kleinjohann_Korf_et al._2013, place={Heidelberg}, title={Methods for the Design and Development}, booktitle={Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future}, publisher={Springer-Verlag}, author={Anacker, Harald and Dellnitz, Michael and Flaßkamp, Kathrin and Grösbrink, Stefan and Hartmann, Philip and Heinzemann, Christian and Horenkamp, Christian and Kleinjohann, Lisa and Kleinjohann, Bernd and Korf, Sebastian and et al.}, year={2013}, pages={187–356} }","mla":"Anacker, Harald, et al. “Methods for the Design and Development.” <i>Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future</i>, Springer-Verlag, 2013, pp. 187–356.","apa":"Anacker, H., Dellnitz, M., Flaßkamp, K., Grösbrink, S., Hartmann, P., Heinzemann, C., Horenkamp, C., Kleinjohann, L., Kleinjohann, B., Korf, S., Krüger, M., Müller, W., Ober-Blöbaum, S., Oberthür, S., Porrmann, M., Priesterjahn, C., Radkowski, W., Rasche, C., Rieke, J., … Ziegert, S. (2013). Methods for the Design and Development. In <i>Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future</i> (pp. 187–356). Springer-Verlag.","ieee":"H. Anacker <i>et al.</i>, “Methods for the Design and Development,” in <i>Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future</i>, Heidelberg: Springer-Verlag, 2013, pp. 187–356.","chicago":"Anacker, Harald, Michael Dellnitz, Kathrin Flaßkamp, Stefan Grösbrink, Philip Hartmann, Christian Heinzemann, Christian Horenkamp, et al. “Methods for the Design and Development.” In <i>Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future</i>, 187–356. Heidelberg: Springer-Verlag, 2013.","ama":"Anacker H, Dellnitz M, Flaßkamp K, et al. Methods for the Design and Development. In: <i>Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future</i>. Springer-Verlag; 2013:187-356."},"page":"187-356","publisher":"Springer-Verlag","date_updated":"2022-01-06T06:57:12Z","date_created":"2021-10-07T10:07:43Z","author":[{"last_name":"Anacker","full_name":"Anacker, Harald","first_name":"Harald"},{"first_name":"Michael","last_name":"Dellnitz","full_name":"Dellnitz, Michael"},{"last_name":"Flaßkamp","full_name":"Flaßkamp, Kathrin","first_name":"Kathrin"},{"first_name":"Stefan","full_name":"Grösbrink, Stefan","last_name":"Grösbrink"},{"last_name":"Hartmann","full_name":"Hartmann, Philip","first_name":"Philip"},{"first_name":"Christian","full_name":"Heinzemann, Christian","last_name":"Heinzemann"},{"full_name":"Horenkamp, Christian","last_name":"Horenkamp","first_name":"Christian"},{"first_name":"Lisa","last_name":"Kleinjohann","id":"15588","full_name":"Kleinjohann, Lisa"},{"last_name":"Kleinjohann","full_name":"Kleinjohann, Bernd","first_name":"Bernd"},{"last_name":"Korf","full_name":"Korf, Sebastian","first_name":"Sebastian"},{"full_name":"Krüger, Martin","last_name":"Krüger","first_name":"Martin"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"},{"first_name":"Sina","full_name":"Ober-Blöbaum, Sina","id":"16494","last_name":"Ober-Blöbaum"},{"last_name":"Oberthür","id":"383","full_name":"Oberthür, Simon","first_name":"Simon"},{"first_name":"Mario","full_name":"Porrmann, Mario","last_name":"Porrmann"},{"first_name":"Claudia","full_name":"Priesterjahn, Claudia","last_name":"Priesterjahn"},{"full_name":"Radkowski, W.","last_name":"Radkowski","first_name":"W."},{"first_name":"Christoph","last_name":"Rasche","full_name":"Rasche, Christoph"},{"first_name":"Jan","last_name":"Rieke","full_name":"Rieke, Jan"},{"last_name":"Ringkamp","full_name":"Ringkamp, Maik","first_name":"Maik"},{"full_name":"Stahl, Katharina","last_name":"Stahl","first_name":"Katharina"},{"first_name":"Dominik","last_name":"Steenken","full_name":"Steenken, Dominik"},{"first_name":"Jörg","full_name":"Stöcklein, Jörg","last_name":"Stöcklein"},{"first_name":"Robert","full_name":"Timmermann, Robert","last_name":"Timmermann"},{"first_name":"Ansgar","full_name":"Trächtler, Ansgar","id":"552","last_name":"Trächtler"},{"last_name":"Witting","full_name":"Witting, Katrin","first_name":"Katrin"},{"first_name":"Tao","last_name":"Xie","full_name":"Xie, Tao"},{"full_name":"Ziegert, Steffen","last_name":"Ziegert","first_name":"Steffen"}],"title":"Methods for the Design and Development"},{"language":[{"iso":"eng"}],"keyword":["Time-varying systems","Time-domain analysis","Synchronization","Context modeling","Clocks","Semantics","Standards"],"user_id":"5786","department":[{"_id":"672"}],"_id":"36919","status":"public","abstract":[{"text":"Faced with increasing demands on energy efficiency, current electronic systems operate according to complex power management schemes including more and more fine-grained voltage frequency scaling and power shutdown scenarios. Consequently, validation of the power design intent should begin as early as possible at electronic system-level (ESL) together with first executable system specifications for integrity tests. However, today's system-level design methodologies usually focus on the abstraction of digital logic and time, so that typical low-power aspects cannot be considered so far. In this paper, we present a high-level modeling approach on top of the SystemC/TLM standard to simulate power distribution and voltage based implications in a \"loosely-timed\" functional execution context. The approach reuses legacy TLM models and prevents the need for detailed lock-step process synchronization in contrast to existing methods. A case study derived from an open source low-power design demonstrates the efficiency of our approach in terms of simulation performance and testability.","lang":"eng"}],"type":"conference","conference":{"name":"23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)"},"doi":"10.1109/PATMOS.2013.6662171","title":"Efficient Power-Intent Validation Using \"Loosely-Timed\" Simulation Models: A Non-Invasive Approach","date_created":"2023-01-16T12:08:03Z","author":[{"first_name":"Fabian","last_name":"Mischkalla","full_name":"Mischkalla, Fabian"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"}],"publisher":"IEEE","date_updated":"2023-01-16T12:08:17Z","citation":{"apa":"Mischkalla, F., &#38; Müller, W. (2013). <i>Efficient Power-Intent Validation Using “Loosely-Timed” Simulation Models: A Non-Invasive Approach</i>. 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). <a href=\"https://doi.org/10.1109/PATMOS.2013.6662171\">https://doi.org/10.1109/PATMOS.2013.6662171</a>","bibtex":"@inproceedings{Mischkalla_Müller_2013, place={Karlsruhe}, title={Efficient Power-Intent Validation Using “Loosely-Timed” Simulation Models: A Non-Invasive Approach}, DOI={<a href=\"https://doi.org/10.1109/PATMOS.2013.6662171\">10.1109/PATMOS.2013.6662171</a>}, publisher={IEEE}, author={Mischkalla, Fabian and Müller, Wolfgang}, year={2013} }","mla":"Mischkalla, Fabian, and Wolfgang Müller. <i>Efficient Power-Intent Validation Using “Loosely-Timed” Simulation Models: A Non-Invasive Approach</i>. IEEE, 2013, doi:<a href=\"https://doi.org/10.1109/PATMOS.2013.6662171\">10.1109/PATMOS.2013.6662171</a>.","short":"F. Mischkalla, W. Müller, in: IEEE, Karlsruhe, 2013.","ama":"Mischkalla F, Müller W. Efficient Power-Intent Validation Using “Loosely-Timed” Simulation Models: A Non-Invasive Approach. In: IEEE; 2013. doi:<a href=\"https://doi.org/10.1109/PATMOS.2013.6662171\">10.1109/PATMOS.2013.6662171</a>","ieee":"F. Mischkalla and W. Müller, “Efficient Power-Intent Validation Using ‘Loosely-Timed’ Simulation Models: A Non-Invasive Approach,” presented at the 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2013, doi: <a href=\"https://doi.org/10.1109/PATMOS.2013.6662171\">10.1109/PATMOS.2013.6662171</a>.","chicago":"Mischkalla, Fabian, and Wolfgang Müller. “Efficient Power-Intent Validation Using ‘Loosely-Timed’ Simulation Models: A Non-Invasive Approach.” Karlsruhe: IEEE, 2013. <a href=\"https://doi.org/10.1109/PATMOS.2013.6662171\">https://doi.org/10.1109/PATMOS.2013.6662171</a>."},"place":"Karlsruhe","year":"2013","publication_identifier":{"eisbn":["978-1-4799-1170-7"]}},{"publication_identifier":{"isbn":["978-989-8533-20-3 "]},"citation":{"apa":"He, D., &#38; Müller, W. (2013). An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors. In H. Weghorn (Ed.), <i>Proceedings of the International Conference on Applied Computing (AC)</i>.","ama":"He D, Müller W. An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors. In: Weghorn H, ed. <i>Proceedings of the International Conference on Applied Computing (AC)</i>. ; 2013.","mla":"He, Da, and Wolfgang Müller. “An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors.” <i>Proceedings of the International Conference on Applied Computing (AC)</i>, edited by Hans Weghorn, 2013.","bibtex":"@inproceedings{He_Müller_2013, place={Fort Worth, Texas, USA}, title={An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors}, booktitle={Proceedings of the International Conference on Applied Computing (AC)}, author={He, Da and Müller, Wolfgang}, editor={Weghorn, Hans}, year={2013} }","short":"D. He, W. Müller, in: H. Weghorn (Ed.), Proceedings of the International Conference on Applied Computing (AC), Fort Worth, Texas, USA, 2013.","chicago":"He, Da, and Wolfgang Müller. “An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors.” In <i>Proceedings of the International Conference on Applied Computing (AC)</i>, edited by Hans Weghorn. Fort Worth, Texas, USA, 2013.","ieee":"D. He and W. Müller, “An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors,” in <i>Proceedings of the International Conference on Applied Computing (AC)</i>, 2013."},"place":"Fort Worth, Texas, USA","year":"2013","date_created":"2023-01-16T12:12:58Z","author":[{"first_name":"Da","full_name":"He, Da","last_name":"He"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"}],"date_updated":"2023-01-16T12:15:44Z","title":"An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors","publication":"Proceedings of the International Conference on Applied Computing (AC)","type":"conference","status":"public","editor":[{"last_name":"Weghorn","full_name":"Weghorn, Hans","first_name":"Hans"}],"abstract":[{"lang":"eng","text":"In the electronic system development, energy consumption is clearly becoming one of the most important design concerns. From the system level point of view, Dynamic Power Management (DPM) and Dynamic Voltage and Frequency Scaling (DVFS) are two mostly applied techniques to adjust the tradeoff between the performance and power dissipation at runtime. In this paper, we study the problem of combined application of both techniques with regard to hard real-time systems running on cluster-based multi-core processors. To optimize the processor energy consumption, a heuristic based on simulated annealing with efficient termination criterion is proposed. The experiment results show that the proposed algorithm outperforms the existing approaches in terms of the energy reduction. "}],"department":[{"_id":"672"}],"user_id":"5786","_id":"36920","language":[{"iso":"eng"}],"keyword":["Dynamic Power Management","Dynamic Voltage and Frequency Scaling","Hard Real-Time","Multi-core Processor"]}]