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Published online 2013:845-857."},"year":"2013","department":[{"_id":"672"}],"user_id":"21240","_id":"25740","language":[{"iso":"eng"}],"publication":"Microprocessors and Microsystems - Embedded Hardware Design 37(6-7)","type":"journal_article","status":"public"},{"publication":"Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future","type":"book_chapter","status":"public","department":[{"_id":"672"}],"user_id":"21240","_id":"25743","language":[{"iso":"eng"}],"page":"187-356","citation":{"bibtex":"@inbook{Anacker_Dellnitz_Flaßkamp_Grösbrink_Hartmann_Heinzemann_Horenkamp_Kleinjohann_Kleinjohann_Korf_et al._2013, place={Heidelberg}, title={Methods for the Design and Development}, booktitle={Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future}, publisher={Springer-Verlag}, author={Anacker, Harald and Dellnitz, Michael and Flaßkamp, Kathrin and Grösbrink, Stefan and Hartmann, Philip and Heinzemann, Christian and Horenkamp, Christian and Kleinjohann, Lisa and Kleinjohann, Bernd and Korf, Sebastian and et al.}, year={2013}, pages={187–356} }","mla":"Anacker, Harald, et al. “Methods for the Design and Development.” <i>Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future</i>, Springer-Verlag, 2013, pp. 187–356.","short":"H. Anacker, M. Dellnitz, K. Flaßkamp, S. Grösbrink, P. Hartmann, C. Heinzemann, C. Horenkamp, L. Kleinjohann, B. Kleinjohann, S. Korf, M. Krüger, W. Müller, S. Ober-Blöbaum, S. Oberthür, M. Porrmann, C. Priesterjahn, W. Radkowski, C. Rasche, J. Rieke, M. Ringkamp, K. Stahl, D. Steenken, J. Stöcklein, R. Timmermann, A. Trächtler, K. Witting, T. Xie, S. Ziegert, in: Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future, Springer-Verlag, Heidelberg, 2013, pp. 187–356.","apa":"Anacker, H., Dellnitz, M., Flaßkamp, K., Grösbrink, S., Hartmann, P., Heinzemann, C., Horenkamp, C., Kleinjohann, L., Kleinjohann, B., Korf, S., Krüger, M., Müller, W., Ober-Blöbaum, S., Oberthür, S., Porrmann, M., Priesterjahn, C., Radkowski, W., Rasche, C., Rieke, J., … Ziegert, S. (2013). Methods for the Design and Development. In <i>Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future</i> (pp. 187–356). Springer-Verlag.","ama":"Anacker H, Dellnitz M, Flaßkamp K, et al. Methods for the Design and Development. In: <i>Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future</i>. Springer-Verlag; 2013:187-356.","chicago":"Anacker, Harald, Michael Dellnitz, Kathrin Flaßkamp, Stefan Grösbrink, Philip Hartmann, Christian Heinzemann, Christian Horenkamp, et al. “Methods for the Design and Development.” In <i>Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future</i>, 187–356. Heidelberg: Springer-Verlag, 2013.","ieee":"H. Anacker <i>et al.</i>, “Methods for the Design and Development,” in <i>Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future</i>, Heidelberg: Springer-Verlag, 2013, pp. 187–356."},"place":"Heidelberg","year":"2013","date_created":"2021-10-07T10:07:43Z","author":[{"first_name":"Harald","last_name":"Anacker","full_name":"Anacker, Harald"},{"last_name":"Dellnitz","full_name":"Dellnitz, Michael","first_name":"Michael"},{"first_name":"Kathrin","full_name":"Flaßkamp, Kathrin","last_name":"Flaßkamp"},{"full_name":"Grösbrink, Stefan","last_name":"Grösbrink","first_name":"Stefan"},{"first_name":"Philip","full_name":"Hartmann, Philip","last_name":"Hartmann"},{"full_name":"Heinzemann, Christian","last_name":"Heinzemann","first_name":"Christian"},{"last_name":"Horenkamp","full_name":"Horenkamp, Christian","first_name":"Christian"},{"full_name":"Kleinjohann, Lisa","id":"15588","last_name":"Kleinjohann","first_name":"Lisa"},{"first_name":"Bernd","full_name":"Kleinjohann, Bernd","last_name":"Kleinjohann"},{"first_name":"Sebastian","full_name":"Korf, Sebastian","last_name":"Korf"},{"last_name":"Krüger","full_name":"Krüger, Martin","first_name":"Martin"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"},{"first_name":"Sina","last_name":"Ober-Blöbaum","id":"16494","full_name":"Ober-Blöbaum, Sina"},{"first_name":"Simon","last_name":"Oberthür","id":"383","full_name":"Oberthür, Simon"},{"full_name":"Porrmann, Mario","last_name":"Porrmann","first_name":"Mario"},{"full_name":"Priesterjahn, Claudia","last_name":"Priesterjahn","first_name":"Claudia"},{"first_name":"W.","full_name":"Radkowski, W.","last_name":"Radkowski"},{"last_name":"Rasche","full_name":"Rasche, Christoph","first_name":"Christoph"},{"full_name":"Rieke, Jan","last_name":"Rieke","first_name":"Jan"},{"first_name":"Maik","last_name":"Ringkamp","full_name":"Ringkamp, Maik"},{"first_name":"Katharina","last_name":"Stahl","full_name":"Stahl, Katharina"},{"last_name":"Steenken","full_name":"Steenken, Dominik","first_name":"Dominik"},{"first_name":"Jörg","last_name":"Stöcklein","full_name":"Stöcklein, Jörg"},{"first_name":"Robert","full_name":"Timmermann, Robert","last_name":"Timmermann"},{"last_name":"Trächtler","id":"552","full_name":"Trächtler, Ansgar","first_name":"Ansgar"},{"first_name":"Katrin","full_name":"Witting, Katrin","last_name":"Witting"},{"full_name":"Xie, Tao","last_name":"Xie","first_name":"Tao"},{"first_name":"Steffen","last_name":"Ziegert","full_name":"Ziegert, Steffen"}],"date_updated":"2022-01-06T06:57:12Z","publisher":"Springer-Verlag","title":"Methods for the Design and Development"},{"status":"public","abstract":[{"lang":"eng","text":"Faced with increasing demands on energy efficiency, current electronic systems operate according to complex power management schemes including more and more fine-grained voltage frequency scaling and power shutdown scenarios. Consequently, validation of the power design intent should begin as early as possible at electronic system-level (ESL) together with first executable system specifications for integrity tests. However, today's system-level design methodologies usually focus on the abstraction of digital logic and time, so that typical low-power aspects cannot be considered so far. In this paper, we present a high-level modeling approach on top of the SystemC/TLM standard to simulate power distribution and voltage based implications in a \"loosely-timed\" functional execution context. The approach reuses legacy TLM models and prevents the need for detailed lock-step process synchronization in contrast to existing methods. A case study derived from an open source low-power design demonstrates the efficiency of our approach in terms of simulation performance and testability."}],"type":"conference","language":[{"iso":"eng"}],"keyword":["Time-varying systems","Time-domain analysis","Synchronization","Context modeling","Clocks","Semantics","Standards"],"department":[{"_id":"672"}],"user_id":"5786","_id":"36919","citation":{"apa":"Mischkalla, F., &#38; Müller, W. (2013). <i>Efficient Power-Intent Validation Using “Loosely-Timed” Simulation Models: A Non-Invasive Approach</i>. 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). <a href=\"https://doi.org/10.1109/PATMOS.2013.6662171\">https://doi.org/10.1109/PATMOS.2013.6662171</a>","mla":"Mischkalla, Fabian, and Wolfgang Müller. <i>Efficient Power-Intent Validation Using “Loosely-Timed” Simulation Models: A Non-Invasive Approach</i>. IEEE, 2013, doi:<a href=\"https://doi.org/10.1109/PATMOS.2013.6662171\">10.1109/PATMOS.2013.6662171</a>.","bibtex":"@inproceedings{Mischkalla_Müller_2013, place={Karlsruhe}, title={Efficient Power-Intent Validation Using “Loosely-Timed” Simulation Models: A Non-Invasive Approach}, DOI={<a href=\"https://doi.org/10.1109/PATMOS.2013.6662171\">10.1109/PATMOS.2013.6662171</a>}, publisher={IEEE}, author={Mischkalla, Fabian and Müller, Wolfgang}, year={2013} }","short":"F. Mischkalla, W. Müller, in: IEEE, Karlsruhe, 2013.","ieee":"F. Mischkalla and W. Müller, “Efficient Power-Intent Validation Using ‘Loosely-Timed’ Simulation Models: A Non-Invasive Approach,” presented at the 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2013, doi: <a href=\"https://doi.org/10.1109/PATMOS.2013.6662171\">10.1109/PATMOS.2013.6662171</a>.","chicago":"Mischkalla, Fabian, and Wolfgang Müller. “Efficient Power-Intent Validation Using ‘Loosely-Timed’ Simulation Models: A Non-Invasive Approach.” Karlsruhe: IEEE, 2013. <a href=\"https://doi.org/10.1109/PATMOS.2013.6662171\">https://doi.org/10.1109/PATMOS.2013.6662171</a>.","ama":"Mischkalla F, Müller W. Efficient Power-Intent Validation Using “Loosely-Timed” Simulation Models: A Non-Invasive Approach. In: IEEE; 2013. doi:<a href=\"https://doi.org/10.1109/PATMOS.2013.6662171\">10.1109/PATMOS.2013.6662171</a>"},"place":"Karlsruhe","year":"2013","publication_identifier":{"eisbn":["978-1-4799-1170-7"]},"doi":"10.1109/PATMOS.2013.6662171","conference":{"name":"23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)"},"title":"Efficient Power-Intent Validation Using \"Loosely-Timed\" Simulation Models: A Non-Invasive Approach","author":[{"full_name":"Mischkalla, Fabian","last_name":"Mischkalla","first_name":"Fabian"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"}],"date_created":"2023-01-16T12:08:03Z","date_updated":"2023-01-16T12:08:17Z","publisher":"IEEE"},{"title":"An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors","author":[{"first_name":"Da","full_name":"He, Da","last_name":"He"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"}],"date_created":"2023-01-16T12:12:58Z","date_updated":"2023-01-16T12:15:44Z","citation":{"chicago":"He, Da, and Wolfgang Müller. “An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors.” In <i>Proceedings of the International Conference on Applied Computing (AC)</i>, edited by Hans Weghorn. Fort Worth, Texas, USA, 2013.","ieee":"D. He and W. Müller, “An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors,” in <i>Proceedings of the International Conference on Applied Computing (AC)</i>, 2013.","bibtex":"@inproceedings{He_Müller_2013, place={Fort Worth, Texas, USA}, title={An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors}, booktitle={Proceedings of the International Conference on Applied Computing (AC)}, author={He, Da and Müller, Wolfgang}, editor={Weghorn, Hans}, year={2013} }","mla":"He, Da, and Wolfgang Müller. “An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors.” <i>Proceedings of the International Conference on Applied Computing (AC)</i>, edited by Hans Weghorn, 2013.","short":"D. He, W. Müller, in: H. Weghorn (Ed.), Proceedings of the International Conference on Applied Computing (AC), Fort Worth, Texas, USA, 2013.","apa":"He, D., &#38; Müller, W. (2013). An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors. In H. Weghorn (Ed.), <i>Proceedings of the International Conference on Applied Computing (AC)</i>.","ama":"He D, Müller W. An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors. In: Weghorn H, ed. <i>Proceedings of the International Conference on Applied Computing (AC)</i>. ; 2013."},"year":"2013","place":"Fort Worth, Texas, USA","publication_identifier":{"isbn":["978-989-8533-20-3 "]},"language":[{"iso":"eng"}],"keyword":["Dynamic Power Management","Dynamic Voltage and Frequency Scaling","Hard Real-Time","Multi-core Processor"],"department":[{"_id":"672"}],"user_id":"5786","_id":"36920","status":"public","abstract":[{"text":"In the electronic system development, energy consumption is clearly becoming one of the most important design concerns. From the system level point of view, Dynamic Power Management (DPM) and Dynamic Voltage and Frequency Scaling (DVFS) are two mostly applied techniques to adjust the tradeoff between the performance and power dissipation at runtime. In this paper, we study the problem of combined application of both techniques with regard to hard real-time systems running on cluster-based multi-core processors. To optimize the processor energy consumption, a heuristic based on simulated annealing with efficient termination criterion is proposed. The experiment results show that the proposed algorithm outperforms the existing approaches in terms of the energy reduction. ","lang":"eng"}],"editor":[{"last_name":"Weghorn","full_name":"Weghorn, Hans","first_name":"Hans"}],"publication":"Proceedings of the International Conference on Applied Computing (AC)","type":"conference"},{"department":[{"_id":"672"}],"user_id":"21240","_id":"25744","language":[{"iso":"eng"}],"publication":" In Proceedings of Advanced Computing and Communications Conference 2012 (ADCOM 2012)","type":"conference","status":"public","author":[{"last_name":"Joy","full_name":"Joy, M. tech. Mabel Mary","first_name":"M. tech. Mabel Mary"},{"last_name":"Becker","full_name":"Becker, Markus","first_name":"Markus"},{"last_name":"Mathews","full_name":"Mathews, Emi","first_name":"Emi"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"}],"date_created":"2021-10-07T10:33:59Z","publisher":"IEEE","date_updated":"2022-01-06T06:57:12Z","conference":{"location":" Bangalore, 14. - 16. Dez. 2012, IEEE"},"title":"Automated Source Code Annotation for Timing Analysis of Embedded Software","citation":{"apa":"Joy, M. tech. M. M., Becker, M., Mathews, E., &#38; Müller, W. (2012). Automated Source Code Annotation for Timing Analysis of Embedded Software. <i> In Proceedings of Advanced Computing and Communications Conference 2012 (ADCOM 2012)</i>.","short":"M. tech. M.M. Joy, M. Becker, E. Mathews, W. Müller, in:  In Proceedings of Advanced Computing and Communications Conference 2012 (ADCOM 2012), IEEE, 2012.","bibtex":"@inproceedings{Joy_Becker_Mathews_Müller_2012, title={Automated Source Code Annotation for Timing Analysis of Embedded Software}, booktitle={ In Proceedings of Advanced Computing and Communications Conference 2012 (ADCOM 2012)}, publisher={IEEE}, author={Joy, M. tech. Mabel Mary and Becker, Markus and Mathews, Emi and Müller, Wolfgang}, year={2012} }","mla":"Joy, M. tech. Mabel Mary, et al. “Automated Source Code Annotation for Timing Analysis of Embedded Software.” <i> In Proceedings of Advanced Computing and Communications Conference 2012 (ADCOM 2012)</i>, IEEE, 2012.","ama":"Joy M tech. MM, Becker M, Mathews E, Müller W. Automated Source Code Annotation for Timing Analysis of Embedded Software. In: <i> In Proceedings of Advanced Computing and Communications Conference 2012 (ADCOM 2012)</i>. IEEE; 2012.","chicago":"Joy, M. tech. Mabel Mary, Markus Becker, Emi Mathews, and Wolfgang Müller. “Automated Source Code Annotation for Timing Analysis of Embedded Software.” In <i> In Proceedings of Advanced Computing and Communications Conference 2012 (ADCOM 2012)</i>. IEEE, 2012.","ieee":"M. tech. M. M. Joy, M. Becker, E. Mathews, and W. Müller, “Automated Source Code Annotation for Timing Analysis of Embedded Software,”  Bangalore, 14. - 16. Dez. 2012, IEEE, 2012."},"year":"2012"},{"language":[{"iso":"eng"}],"_id":"25758","user_id":"21240","department":[{"_id":"672"}],"status":"public","type":"conference","publication":"EMSOFT'12: Teenth ACM International Conference on Embedded Software 2012 Proceedings ","title":"XEMU: An Efficient QEMU Based Binary Mutation Testing Framework for Embedded Software","date_updated":"2022-01-06T06:57:12Z","date_created":"2021-10-07T11:11:30Z","author":[{"last_name":"Becker","full_name":"Becker, Markus","first_name":"Markus"},{"last_name":"Baldin","full_name":"Baldin, Daniel","first_name":"Daniel"},{"full_name":"Kuznik, Christoph","last_name":"Kuznik","first_name":"Christoph"},{"first_name":"M. tech. Mabel Mary","full_name":"Joy, M. tech. Mabel Mary","last_name":"Joy"},{"last_name":"Xie","full_name":"Xie, Tao","first_name":"Tao"},{"last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243","first_name":"Wolfgang"}],"year":"2012","citation":{"ieee":"M. Becker, D. Baldin, C. Kuznik, M. tech. M. M. Joy, T. Xie, and W. Müller, “XEMU: An Efficient QEMU Based Binary Mutation Testing Framework for Embedded Software,” 2012.","chicago":"Becker, Markus, Daniel Baldin, Christoph Kuznik, M. tech. Mabel Mary Joy, Tao Xie, and Wolfgang Müller. “XEMU: An Efficient QEMU Based Binary Mutation Testing Framework for Embedded Software.” In <i>EMSOFT’12: Teenth ACM International Conference on Embedded Software 2012 Proceedings </i>, 2012.","ama":"Becker M, Baldin D, Kuznik C, Joy M tech. MM, Xie T, Müller W. XEMU: An Efficient QEMU Based Binary Mutation Testing Framework for Embedded Software. In: <i>EMSOFT’12: Teenth ACM International Conference on Embedded Software 2012 Proceedings </i>. ; 2012.","apa":"Becker, M., Baldin, D., Kuznik, C., Joy, M. tech. M. M., Xie, T., &#38; Müller, W. (2012). XEMU: An Efficient QEMU Based Binary Mutation Testing Framework for Embedded Software. <i>EMSOFT’12: Teenth ACM International Conference on Embedded Software 2012 Proceedings </i>.","bibtex":"@inproceedings{Becker_Baldin_Kuznik_Joy_Xie_Müller_2012, title={XEMU: An Efficient QEMU Based Binary Mutation Testing Framework for Embedded Software}, booktitle={EMSOFT’12: Teenth ACM International Conference on Embedded Software 2012 Proceedings }, author={Becker, Markus and Baldin, Daniel and Kuznik, Christoph and Joy, M. tech. Mabel Mary and Xie, Tao and Müller, Wolfgang}, year={2012} }","short":"M. Becker, D. Baldin, C. Kuznik, M. tech. M.M. Joy, T. Xie, W. Müller, in: EMSOFT’12: Teenth ACM International Conference on Embedded Software 2012 Proceedings , 2012.","mla":"Becker, Markus, et al. “XEMU: An Efficient QEMU Based Binary Mutation Testing Framework for Embedded Software.” <i>EMSOFT’12: Teenth ACM International Conference on Embedded Software 2012 Proceedings </i>, 2012."}},{"language":[{"iso":"eng"}],"_id":"25761","user_id":"21240","department":[{"_id":"672"}],"status":"public","type":"conference","publication":"CODES/ISSS '12: Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Proceedings","title":"The System Verification Methodology for Advanced TLM Verification","date_updated":"2022-01-06T06:57:12Z","date_created":"2021-10-07T11:16:29Z","author":[{"last_name":"Oliveira","full_name":"Oliveira, Marcio F.","first_name":"Marcio F."},{"first_name":"Christoph","full_name":"Kuznik, Christoph","last_name":"Kuznik"},{"last_name":"Le","full_name":"Le, Hoang M.","first_name":"Hoang M."},{"first_name":"Daniel","last_name":"Große","full_name":"Große, Daniel"},{"last_name":"Haedicke","full_name":"Haedicke, Finn","first_name":"Finn"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"first_name":"Rolf","last_name":"Drechsler","full_name":"Drechsler, Rolf"},{"first_name":"Wolfgang","last_name":"Ecker","full_name":"Ecker, Wolfgang"},{"first_name":"Volkan","full_name":"Esen, Volkan","last_name":"Esen"}],"year":"2012","citation":{"ama":"Oliveira MF, Kuznik C, Le HM, et al. The System Verification Methodology for Advanced TLM Verification. In: <i>CODES/ISSS ’12: Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Proceedings</i>. ; 2012.","ieee":"M. F. Oliveira <i>et al.</i>, “The System Verification Methodology for Advanced TLM Verification,” 2012.","chicago":"Oliveira, Marcio F., Christoph Kuznik, Hoang M. Le, Daniel Große, Finn Haedicke, Wolfgang Müller, Rolf Drechsler, Wolfgang Ecker, and Volkan Esen. “The System Verification Methodology for Advanced TLM Verification.” In <i>CODES/ISSS ’12: Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Proceedings</i>, 2012.","short":"M.F. Oliveira, C. Kuznik, H.M. Le, D. Große, F. Haedicke, W. Müller, R. Drechsler, W. Ecker, V. Esen, in: CODES/ISSS ’12: Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Proceedings, 2012.","bibtex":"@inproceedings{Oliveira_Kuznik_Le_Große_Haedicke_Müller_Drechsler_Ecker_Esen_2012, title={The System Verification Methodology for Advanced TLM Verification}, booktitle={CODES/ISSS ’12: Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Proceedings}, author={Oliveira, Marcio F. and Kuznik, Christoph and Le, Hoang M. and Große, Daniel and Haedicke, Finn and Müller, Wolfgang and Drechsler, Rolf and Ecker, Wolfgang and Esen, Volkan}, year={2012} }","mla":"Oliveira, Marcio F., et al. “The System Verification Methodology for Advanced TLM Verification.” <i>CODES/ISSS ’12: Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Proceedings</i>, 2012.","apa":"Oliveira, M. F., Kuznik, C., Le, H. M., Große, D., Haedicke, F., Müller, W., Drechsler, R., Ecker, W., &#38; Esen, V. (2012). The System Verification Methodology for Advanced TLM Verification. <i>CODES/ISSS ’12: Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Proceedings</i>."}},{"status":"public","type":"conference","publication":"15th Euromicro Conference on Digital System Design (DSD)","language":[{"iso":"eng"}],"_id":"25767","user_id":"21240","department":[{"_id":"672"}],"year":"2012","citation":{"ama":"He D, Müller W. A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms. In: <i>15th Euromicro Conference on Digital System Design (DSD)</i>. IEEE Xplore; 2012.","ieee":"D. He and W. Müller, “A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms,” 2012.","chicago":"He, Da, and Wolfgang Müller. “A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms.” In <i>15th Euromicro Conference on Digital System Design (DSD)</i>. IEEE Xplore, 2012.","mla":"He, Da, and Wolfgang Müller. “A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms.” <i>15th Euromicro Conference on Digital System Design (DSD)</i>, IEEE Xplore, 2012.","short":"D. He, W. Müller, in: 15th Euromicro Conference on Digital System Design (DSD), IEEE Xplore, 2012.","bibtex":"@inproceedings{He_Müller_2012, title={A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms}, booktitle={15th Euromicro Conference on Digital System Design (DSD)}, publisher={IEEE Xplore}, author={He, Da and Müller, Wolfgang}, year={2012} }","apa":"He, D., &#38; Müller, W. (2012). A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms. <i>15th Euromicro Conference on Digital System Design (DSD)</i>."},"title":"A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms","date_updated":"2022-01-06T06:57:12Z","publisher":"IEEE Xplore","date_created":"2021-10-07T12:11:29Z","author":[{"first_name":"Da","full_name":"He, Da","last_name":"He"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"}]},{"date_updated":"2022-01-06T06:57:15Z","date_created":"2021-10-11T08:39:53Z","author":[{"full_name":"Becker, Markus","last_name":"Becker","first_name":"Markus"},{"full_name":"Kuznik, Christoph","last_name":"Kuznik","first_name":"Christoph"},{"first_name":"M. tech. Mabel Mary","last_name":"Joy","full_name":"Joy, M. tech. Mabel Mary"},{"last_name":"Xie","full_name":"Xie, Tao","first_name":"Tao"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"}],"title":"Binary Mutation Testing Through Dynamic Translation","main_file_link":[{"url":"http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6263914&isnumber=6263904"}],"year":"2012","citation":{"mla":"Becker, Markus, et al. “Binary Mutation Testing Through Dynamic Translation.” <i> 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)</i>, 2012.","short":"M. Becker, C. Kuznik, M. tech. M.M. Joy, T. Xie, W. Müller, in:  42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2012.","bibtex":"@inproceedings{Becker_Kuznik_Joy_Xie_Müller_2012, title={Binary Mutation Testing Through Dynamic Translation}, booktitle={ 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)}, author={Becker, Markus and Kuznik, Christoph and Joy, M. tech. Mabel Mary and Xie, Tao and Müller, Wolfgang}, year={2012} }","apa":"Becker, M., Kuznik, C., Joy, M. tech. M. M., Xie, T., &#38; Müller, W. (2012). Binary Mutation Testing Through Dynamic Translation. <i> 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)</i>.","ieee":"M. Becker, C. Kuznik, M. tech. M. M. Joy, T. Xie, and W. Müller, “Binary Mutation Testing Through Dynamic Translation,” 2012.","chicago":"Becker, Markus, Christoph Kuznik, M. tech. Mabel Mary Joy, Tao Xie, and Wolfgang Müller. “Binary Mutation Testing Through Dynamic Translation.” In <i> 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)</i>, 2012.","ama":"Becker M, Kuznik C, Joy M tech. MM, Xie T, Müller W. Binary Mutation Testing Through Dynamic Translation. In: <i> 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)</i>. ; 2012."},"_id":"26022","user_id":"21240","department":[{"_id":"672"}],"language":[{"iso":"eng"}],"type":"conference","publication":" 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)","status":"public"}]