[{"title":"Fault-Tolerant Deployment of Real-Time Software in AUTOSAR ECU Networks","publisher":"Springer","date_updated":"2022-01-06T06:57:08Z","author":[{"full_name":"Klobedanz, Kay","last_name":"Klobedanz","first_name":"Kay"},{"first_name":"Jan","full_name":"Jatzkowski, Jan","last_name":"Jatzkowski"},{"full_name":"Rettberg, Achim","last_name":"Rettberg","first_name":"Achim"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"}],"date_created":"2021-10-07T09:46:48Z","year":"2013","citation":{"apa":"Klobedanz, K., Jatzkowski, J., Rettberg, A., &#38; Müller, W. (2013). Fault-Tolerant Deployment of Real-Time Software in AUTOSAR ECU Networks. <i>International Embedded Systems Symposium (IESS) 2013</i>.","bibtex":"@inproceedings{Klobedanz_Jatzkowski_Rettberg_Müller_2013, title={Fault-Tolerant Deployment of Real-Time Software in AUTOSAR ECU Networks}, booktitle={International Embedded Systems Symposium (IESS) 2013}, publisher={Springer}, author={Klobedanz, Kay and Jatzkowski, Jan and Rettberg, Achim and Müller, Wolfgang}, year={2013} }","short":"K. Klobedanz, J. Jatzkowski, A. Rettberg, W. Müller, in: International Embedded Systems Symposium (IESS) 2013, Springer, 2013.","mla":"Klobedanz, Kay, et al. “Fault-Tolerant Deployment of Real-Time Software in AUTOSAR ECU Networks.” <i>International Embedded Systems Symposium (IESS) 2013</i>, Springer, 2013.","ama":"Klobedanz K, Jatzkowski J, Rettberg A, Müller W. Fault-Tolerant Deployment of Real-Time Software in AUTOSAR ECU Networks. In: <i>International Embedded Systems Symposium (IESS) 2013</i>. Springer; 2013.","ieee":"K. Klobedanz, J. Jatzkowski, A. Rettberg, and W. Müller, “Fault-Tolerant Deployment of Real-Time Software in AUTOSAR ECU Networks,” 2013.","chicago":"Klobedanz, Kay, Jan Jatzkowski, Achim Rettberg, and Wolfgang Müller. “Fault-Tolerant Deployment of Real-Time Software in AUTOSAR ECU Networks.” In <i>International Embedded Systems Symposium (IESS) 2013</i>. Springer, 2013."},"language":[{"iso":"eng"}],"_id":"25632","department":[{"_id":"672"}],"user_id":"21240","status":"public","publication":"International Embedded Systems Symposium (IESS) 2013","type":"conference"},{"user_id":"21240","department":[{"_id":"672"}],"_id":"25740","language":[{"iso":"eng"}],"type":"journal_article","publication":"Microprocessors and Microsystems - Embedded Hardware Design 37(6-7)","status":"public","author":[{"first_name":"Da","full_name":"He, Da","last_name":"He"},{"last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243","first_name":"Wolfgang"}],"date_created":"2021-10-07T09:49:15Z","date_updated":"2022-01-06T06:57:12Z","title":" A heuristic energy-aware approach for hard real-time systems on multi-core platforms","citation":{"short":"D. He, W. Müller, Microprocessors and Microsystems - Embedded Hardware Design 37(6-7) (2013) 845–857.","bibtex":"@article{He_Müller_2013, title={ A heuristic energy-aware approach for hard real-time systems on multi-core platforms}, journal={Microprocessors and Microsystems - Embedded Hardware Design 37(6-7)}, author={He, Da and Müller, Wolfgang}, year={2013}, pages={845–857} }","mla":"He, Da, and Wolfgang Müller. “ A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms.” <i>Microprocessors and Microsystems - Embedded Hardware Design 37(6-7)</i>, 2013, pp. 845–57.","apa":"He, D., &#38; Müller, W. (2013).  A heuristic energy-aware approach for hard real-time systems on multi-core platforms. <i>Microprocessors and Microsystems - Embedded Hardware Design 37(6-7)</i>, 845–857.","chicago":"He, Da, and Wolfgang Müller. “ A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms.” <i>Microprocessors and Microsystems - Embedded Hardware Design 37(6-7)</i>, 2013, 845–57.","ieee":"D. He and W. Müller, “ A heuristic energy-aware approach for hard real-time systems on multi-core platforms,” <i>Microprocessors and Microsystems - Embedded Hardware Design 37(6-7)</i>, pp. 845–857, 2013.","ama":"He D, Müller W.  A heuristic energy-aware approach for hard real-time systems on multi-core platforms. <i>Microprocessors and Microsystems - Embedded Hardware Design 37(6-7)</i>. Published online 2013:845-857."},"page":"845-857","year":"2013"},{"year":"2013","place":"Heidelberg","citation":{"ama":"Anacker H, Dellnitz M, Flaßkamp K, et al. Methods for the Design and Development. In: <i>Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future</i>. Springer-Verlag; 2013:187-356.","chicago":"Anacker, Harald, Michael Dellnitz, Kathrin Flaßkamp, Stefan Grösbrink, Philip Hartmann, Christian Heinzemann, Christian Horenkamp, et al. “Methods for the Design and Development.” In <i>Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future</i>, 187–356. Heidelberg: Springer-Verlag, 2013.","ieee":"H. Anacker <i>et al.</i>, “Methods for the Design and Development,” in <i>Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future</i>, Heidelberg: Springer-Verlag, 2013, pp. 187–356.","short":"H. Anacker, M. Dellnitz, K. Flaßkamp, S. Grösbrink, P. Hartmann, C. Heinzemann, C. Horenkamp, L. Kleinjohann, B. Kleinjohann, S. Korf, M. Krüger, W. Müller, S. Ober-Blöbaum, S. Oberthür, M. Porrmann, C. Priesterjahn, W. Radkowski, C. Rasche, J. Rieke, M. Ringkamp, K. Stahl, D. Steenken, J. Stöcklein, R. Timmermann, A. Trächtler, K. Witting, T. Xie, S. Ziegert, in: Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future, Springer-Verlag, Heidelberg, 2013, pp. 187–356.","bibtex":"@inbook{Anacker_Dellnitz_Flaßkamp_Grösbrink_Hartmann_Heinzemann_Horenkamp_Kleinjohann_Kleinjohann_Korf_et al._2013, place={Heidelberg}, title={Methods for the Design and Development}, booktitle={Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future}, publisher={Springer-Verlag}, author={Anacker, Harald and Dellnitz, Michael and Flaßkamp, Kathrin and Grösbrink, Stefan and Hartmann, Philip and Heinzemann, Christian and Horenkamp, Christian and Kleinjohann, Lisa and Kleinjohann, Bernd and Korf, Sebastian and et al.}, year={2013}, pages={187–356} }","mla":"Anacker, Harald, et al. “Methods for the Design and Development.” <i>Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future</i>, Springer-Verlag, 2013, pp. 187–356.","apa":"Anacker, H., Dellnitz, M., Flaßkamp, K., Grösbrink, S., Hartmann, P., Heinzemann, C., Horenkamp, C., Kleinjohann, L., Kleinjohann, B., Korf, S., Krüger, M., Müller, W., Ober-Blöbaum, S., Oberthür, S., Porrmann, M., Priesterjahn, C., Radkowski, W., Rasche, C., Rieke, J., … Ziegert, S. (2013). Methods for the Design and Development. In <i>Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future</i> (pp. 187–356). Springer-Verlag."},"page":"187-356","date_updated":"2022-01-06T06:57:12Z","publisher":"Springer-Verlag","author":[{"first_name":"Harald","last_name":"Anacker","full_name":"Anacker, Harald"},{"last_name":"Dellnitz","full_name":"Dellnitz, Michael","first_name":"Michael"},{"last_name":"Flaßkamp","full_name":"Flaßkamp, Kathrin","first_name":"Kathrin"},{"first_name":"Stefan","full_name":"Grösbrink, Stefan","last_name":"Grösbrink"},{"first_name":"Philip","last_name":"Hartmann","full_name":"Hartmann, Philip"},{"full_name":"Heinzemann, Christian","last_name":"Heinzemann","first_name":"Christian"},{"full_name":"Horenkamp, Christian","last_name":"Horenkamp","first_name":"Christian"},{"last_name":"Kleinjohann","id":"15588","full_name":"Kleinjohann, Lisa","first_name":"Lisa"},{"full_name":"Kleinjohann, Bernd","last_name":"Kleinjohann","first_name":"Bernd"},{"first_name":"Sebastian","last_name":"Korf","full_name":"Korf, Sebastian"},{"first_name":"Martin","full_name":"Krüger, Martin","last_name":"Krüger"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"},{"first_name":"Sina","id":"16494","full_name":"Ober-Blöbaum, Sina","last_name":"Ober-Blöbaum"},{"first_name":"Simon","full_name":"Oberthür, Simon","id":"383","last_name":"Oberthür"},{"first_name":"Mario","last_name":"Porrmann","full_name":"Porrmann, Mario"},{"first_name":"Claudia","full_name":"Priesterjahn, Claudia","last_name":"Priesterjahn"},{"full_name":"Radkowski, W.","last_name":"Radkowski","first_name":"W."},{"last_name":"Rasche","full_name":"Rasche, Christoph","first_name":"Christoph"},{"first_name":"Jan","full_name":"Rieke, Jan","last_name":"Rieke"},{"full_name":"Ringkamp, Maik","last_name":"Ringkamp","first_name":"Maik"},{"first_name":"Katharina","full_name":"Stahl, Katharina","last_name":"Stahl"},{"first_name":"Dominik","last_name":"Steenken","full_name":"Steenken, Dominik"},{"first_name":"Jörg","full_name":"Stöcklein, Jörg","last_name":"Stöcklein"},{"first_name":"Robert","full_name":"Timmermann, Robert","last_name":"Timmermann"},{"first_name":"Ansgar","full_name":"Trächtler, Ansgar","id":"552","last_name":"Trächtler"},{"first_name":"Katrin","last_name":"Witting","full_name":"Witting, Katrin"},{"last_name":"Xie","full_name":"Xie, Tao","first_name":"Tao"},{"first_name":"Steffen","full_name":"Ziegert, Steffen","last_name":"Ziegert"}],"date_created":"2021-10-07T10:07:43Z","title":"Methods for the Design and Development","type":"book_chapter","publication":"Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future","status":"public","_id":"25743","user_id":"21240","department":[{"_id":"672"}],"language":[{"iso":"eng"}]},{"abstract":[{"lang":"eng","text":"Faced with increasing demands on energy efficiency, current electronic systems operate according to complex power management schemes including more and more fine-grained voltage frequency scaling and power shutdown scenarios. Consequently, validation of the power design intent should begin as early as possible at electronic system-level (ESL) together with first executable system specifications for integrity tests. However, today's system-level design methodologies usually focus on the abstraction of digital logic and time, so that typical low-power aspects cannot be considered so far. In this paper, we present a high-level modeling approach on top of the SystemC/TLM standard to simulate power distribution and voltage based implications in a \"loosely-timed\" functional execution context. The approach reuses legacy TLM models and prevents the need for detailed lock-step process synchronization in contrast to existing methods. A case study derived from an open source low-power design demonstrates the efficiency of our approach in terms of simulation performance and testability."}],"status":"public","type":"conference","keyword":["Time-varying systems","Time-domain analysis","Synchronization","Context modeling","Clocks","Semantics","Standards"],"language":[{"iso":"eng"}],"_id":"36919","department":[{"_id":"672"}],"user_id":"5786","place":"Karlsruhe","year":"2013","citation":{"mla":"Mischkalla, Fabian, and Wolfgang Müller. <i>Efficient Power-Intent Validation Using “Loosely-Timed” Simulation Models: A Non-Invasive Approach</i>. IEEE, 2013, doi:<a href=\"https://doi.org/10.1109/PATMOS.2013.6662171\">10.1109/PATMOS.2013.6662171</a>.","bibtex":"@inproceedings{Mischkalla_Müller_2013, place={Karlsruhe}, title={Efficient Power-Intent Validation Using “Loosely-Timed” Simulation Models: A Non-Invasive Approach}, DOI={<a href=\"https://doi.org/10.1109/PATMOS.2013.6662171\">10.1109/PATMOS.2013.6662171</a>}, publisher={IEEE}, author={Mischkalla, Fabian and Müller, Wolfgang}, year={2013} }","short":"F. Mischkalla, W. Müller, in: IEEE, Karlsruhe, 2013.","apa":"Mischkalla, F., &#38; Müller, W. (2013). <i>Efficient Power-Intent Validation Using “Loosely-Timed” Simulation Models: A Non-Invasive Approach</i>. 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). <a href=\"https://doi.org/10.1109/PATMOS.2013.6662171\">https://doi.org/10.1109/PATMOS.2013.6662171</a>","ama":"Mischkalla F, Müller W. Efficient Power-Intent Validation Using “Loosely-Timed” Simulation Models: A Non-Invasive Approach. In: IEEE; 2013. doi:<a href=\"https://doi.org/10.1109/PATMOS.2013.6662171\">10.1109/PATMOS.2013.6662171</a>","ieee":"F. Mischkalla and W. Müller, “Efficient Power-Intent Validation Using ‘Loosely-Timed’ Simulation Models: A Non-Invasive Approach,” presented at the 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2013, doi: <a href=\"https://doi.org/10.1109/PATMOS.2013.6662171\">10.1109/PATMOS.2013.6662171</a>.","chicago":"Mischkalla, Fabian, and Wolfgang Müller. “Efficient Power-Intent Validation Using ‘Loosely-Timed’ Simulation Models: A Non-Invasive Approach.” Karlsruhe: IEEE, 2013. <a href=\"https://doi.org/10.1109/PATMOS.2013.6662171\">https://doi.org/10.1109/PATMOS.2013.6662171</a>."},"publication_identifier":{"eisbn":["978-1-4799-1170-7"]},"title":"Efficient Power-Intent Validation Using \"Loosely-Timed\" Simulation Models: A Non-Invasive Approach","conference":{"name":"23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)"},"doi":"10.1109/PATMOS.2013.6662171","publisher":"IEEE","date_updated":"2023-01-16T12:08:17Z","date_created":"2023-01-16T12:08:03Z","author":[{"full_name":"Mischkalla, Fabian","last_name":"Mischkalla","first_name":"Fabian"},{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"}]},{"date_updated":"2023-01-16T12:15:44Z","date_created":"2023-01-16T12:12:58Z","author":[{"first_name":"Da","full_name":"He, Da","last_name":"He"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"}],"title":"An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors","publication_identifier":{"isbn":["978-989-8533-20-3 "]},"place":"Fort Worth, Texas, USA","year":"2013","citation":{"chicago":"He, Da, and Wolfgang Müller. “An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors.” In <i>Proceedings of the International Conference on Applied Computing (AC)</i>, edited by Hans Weghorn. Fort Worth, Texas, USA, 2013.","ieee":"D. He and W. Müller, “An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors,” in <i>Proceedings of the International Conference on Applied Computing (AC)</i>, 2013.","apa":"He, D., &#38; Müller, W. (2013). An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors. In H. Weghorn (Ed.), <i>Proceedings of the International Conference on Applied Computing (AC)</i>.","ama":"He D, Müller W. An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors. In: Weghorn H, ed. <i>Proceedings of the International Conference on Applied Computing (AC)</i>. ; 2013.","bibtex":"@inproceedings{He_Müller_2013, place={Fort Worth, Texas, USA}, title={An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors}, booktitle={Proceedings of the International Conference on Applied Computing (AC)}, author={He, Da and Müller, Wolfgang}, editor={Weghorn, Hans}, year={2013} }","short":"D. He, W. Müller, in: H. Weghorn (Ed.), Proceedings of the International Conference on Applied Computing (AC), Fort Worth, Texas, USA, 2013.","mla":"He, Da, and Wolfgang Müller. “An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors.” <i>Proceedings of the International Conference on Applied Computing (AC)</i>, edited by Hans Weghorn, 2013."},"_id":"36920","user_id":"5786","department":[{"_id":"672"}],"keyword":["Dynamic Power Management","Dynamic Voltage and Frequency Scaling","Hard Real-Time","Multi-core Processor"],"language":[{"iso":"eng"}],"type":"conference","publication":"Proceedings of the International Conference on Applied Computing (AC)","editor":[{"full_name":"Weghorn, Hans","last_name":"Weghorn","first_name":"Hans"}],"abstract":[{"text":"In the electronic system development, energy consumption is clearly becoming one of the most important design concerns. From the system level point of view, Dynamic Power Management (DPM) and Dynamic Voltage and Frequency Scaling (DVFS) are two mostly applied techniques to adjust the tradeoff between the performance and power dissipation at runtime. In this paper, we study the problem of combined application of both techniques with regard to hard real-time systems running on cluster-based multi-core processors. To optimize the processor energy consumption, a heuristic based on simulated annealing with efficient termination criterion is proposed. The experiment results show that the proposed algorithm outperforms the existing approaches in terms of the energy reduction. ","lang":"eng"}],"status":"public"},{"title":"Automated Source Code Annotation for Timing Analysis of Embedded Software","conference":{"location":" Bangalore, 14. - 16. Dez. 2012, IEEE"},"date_updated":"2022-01-06T06:57:12Z","publisher":"IEEE","author":[{"first_name":"M. tech. Mabel Mary","last_name":"Joy","full_name":"Joy, M. tech. Mabel Mary"},{"first_name":"Markus","full_name":"Becker, Markus","last_name":"Becker"},{"first_name":"Emi","last_name":"Mathews","full_name":"Mathews, Emi"},{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"}],"date_created":"2021-10-07T10:33:59Z","year":"2012","citation":{"ama":"Joy M tech. MM, Becker M, Mathews E, Müller W. Automated Source Code Annotation for Timing Analysis of Embedded Software. In: <i> In Proceedings of Advanced Computing and Communications Conference 2012 (ADCOM 2012)</i>. IEEE; 2012.","chicago":"Joy, M. tech. Mabel Mary, Markus Becker, Emi Mathews, and Wolfgang Müller. “Automated Source Code Annotation for Timing Analysis of Embedded Software.” In <i> In Proceedings of Advanced Computing and Communications Conference 2012 (ADCOM 2012)</i>. IEEE, 2012.","ieee":"M. tech. M. M. Joy, M. Becker, E. Mathews, and W. Müller, “Automated Source Code Annotation for Timing Analysis of Embedded Software,”  Bangalore, 14. - 16. Dez. 2012, IEEE, 2012.","bibtex":"@inproceedings{Joy_Becker_Mathews_Müller_2012, title={Automated Source Code Annotation for Timing Analysis of Embedded Software}, booktitle={ In Proceedings of Advanced Computing and Communications Conference 2012 (ADCOM 2012)}, publisher={IEEE}, author={Joy, M. tech. Mabel Mary and Becker, Markus and Mathews, Emi and Müller, Wolfgang}, year={2012} }","short":"M. tech. M.M. Joy, M. Becker, E. Mathews, W. Müller, in:  In Proceedings of Advanced Computing and Communications Conference 2012 (ADCOM 2012), IEEE, 2012.","mla":"Joy, M. tech. Mabel Mary, et al. “Automated Source Code Annotation for Timing Analysis of Embedded Software.” <i> In Proceedings of Advanced Computing and Communications Conference 2012 (ADCOM 2012)</i>, IEEE, 2012.","apa":"Joy, M. tech. M. M., Becker, M., Mathews, E., &#38; Müller, W. (2012). Automated Source Code Annotation for Timing Analysis of Embedded Software. <i> In Proceedings of Advanced Computing and Communications Conference 2012 (ADCOM 2012)</i>."},"language":[{"iso":"eng"}],"_id":"25744","department":[{"_id":"672"}],"user_id":"21240","status":"public","publication":" In Proceedings of Advanced Computing and Communications Conference 2012 (ADCOM 2012)","type":"conference"},{"status":"public","type":"conference","publication":"EMSOFT'12: Teenth ACM International Conference on Embedded Software 2012 Proceedings ","language":[{"iso":"eng"}],"_id":"25758","user_id":"21240","department":[{"_id":"672"}],"year":"2012","citation":{"mla":"Becker, Markus, et al. “XEMU: An Efficient QEMU Based Binary Mutation Testing Framework for Embedded Software.” <i>EMSOFT’12: Teenth ACM International Conference on Embedded Software 2012 Proceedings </i>, 2012.","short":"M. Becker, D. Baldin, C. Kuznik, M. tech. M.M. Joy, T. Xie, W. Müller, in: EMSOFT’12: Teenth ACM International Conference on Embedded Software 2012 Proceedings , 2012.","bibtex":"@inproceedings{Becker_Baldin_Kuznik_Joy_Xie_Müller_2012, title={XEMU: An Efficient QEMU Based Binary Mutation Testing Framework for Embedded Software}, booktitle={EMSOFT’12: Teenth ACM International Conference on Embedded Software 2012 Proceedings }, author={Becker, Markus and Baldin, Daniel and Kuznik, Christoph and Joy, M. tech. Mabel Mary and Xie, Tao and Müller, Wolfgang}, year={2012} }","apa":"Becker, M., Baldin, D., Kuznik, C., Joy, M. tech. M. M., Xie, T., &#38; Müller, W. (2012). XEMU: An Efficient QEMU Based Binary Mutation Testing Framework for Embedded Software. <i>EMSOFT’12: Teenth ACM International Conference on Embedded Software 2012 Proceedings </i>.","chicago":"Becker, Markus, Daniel Baldin, Christoph Kuznik, M. tech. Mabel Mary Joy, Tao Xie, and Wolfgang Müller. “XEMU: An Efficient QEMU Based Binary Mutation Testing Framework for Embedded Software.” In <i>EMSOFT’12: Teenth ACM International Conference on Embedded Software 2012 Proceedings </i>, 2012.","ieee":"M. Becker, D. Baldin, C. Kuznik, M. tech. M. M. Joy, T. Xie, and W. Müller, “XEMU: An Efficient QEMU Based Binary Mutation Testing Framework for Embedded Software,” 2012.","ama":"Becker M, Baldin D, Kuznik C, Joy M tech. MM, Xie T, Müller W. XEMU: An Efficient QEMU Based Binary Mutation Testing Framework for Embedded Software. In: <i>EMSOFT’12: Teenth ACM International Conference on Embedded Software 2012 Proceedings </i>. ; 2012."},"title":"XEMU: An Efficient QEMU Based Binary Mutation Testing Framework for Embedded Software","date_updated":"2022-01-06T06:57:12Z","date_created":"2021-10-07T11:11:30Z","author":[{"first_name":"Markus","last_name":"Becker","full_name":"Becker, Markus"},{"full_name":"Baldin, Daniel","last_name":"Baldin","first_name":"Daniel"},{"full_name":"Kuznik, Christoph","last_name":"Kuznik","first_name":"Christoph"},{"first_name":"M. tech. Mabel Mary","full_name":"Joy, M. tech. Mabel Mary","last_name":"Joy"},{"full_name":"Xie, Tao","last_name":"Xie","first_name":"Tao"},{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"}]},{"date_updated":"2022-01-06T06:57:12Z","author":[{"full_name":"Oliveira, Marcio F.","last_name":"Oliveira","first_name":"Marcio F."},{"full_name":"Kuznik, Christoph","last_name":"Kuznik","first_name":"Christoph"},{"first_name":"Hoang M.","last_name":"Le","full_name":"Le, Hoang M."},{"first_name":"Daniel","full_name":"Große, Daniel","last_name":"Große"},{"last_name":"Haedicke","full_name":"Haedicke, Finn","first_name":"Finn"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"},{"first_name":"Rolf","full_name":"Drechsler, Rolf","last_name":"Drechsler"},{"first_name":"Wolfgang","full_name":"Ecker, Wolfgang","last_name":"Ecker"},{"last_name":"Esen","full_name":"Esen, Volkan","first_name":"Volkan"}],"date_created":"2021-10-07T11:16:29Z","title":"The System Verification Methodology for Advanced TLM Verification","year":"2012","citation":{"ama":"Oliveira MF, Kuznik C, Le HM, et al. The System Verification Methodology for Advanced TLM Verification. In: <i>CODES/ISSS ’12: Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Proceedings</i>. ; 2012.","chicago":"Oliveira, Marcio F., Christoph Kuznik, Hoang M. Le, Daniel Große, Finn Haedicke, Wolfgang Müller, Rolf Drechsler, Wolfgang Ecker, and Volkan Esen. “The System Verification Methodology for Advanced TLM Verification.” In <i>CODES/ISSS ’12: Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Proceedings</i>, 2012.","ieee":"M. F. Oliveira <i>et al.</i>, “The System Verification Methodology for Advanced TLM Verification,” 2012.","short":"M.F. Oliveira, C. Kuznik, H.M. Le, D. Große, F. Haedicke, W. Müller, R. Drechsler, W. Ecker, V. Esen, in: CODES/ISSS ’12: Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Proceedings, 2012.","bibtex":"@inproceedings{Oliveira_Kuznik_Le_Große_Haedicke_Müller_Drechsler_Ecker_Esen_2012, title={The System Verification Methodology for Advanced TLM Verification}, booktitle={CODES/ISSS ’12: Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Proceedings}, author={Oliveira, Marcio F. and Kuznik, Christoph and Le, Hoang M. and Große, Daniel and Haedicke, Finn and Müller, Wolfgang and Drechsler, Rolf and Ecker, Wolfgang and Esen, Volkan}, year={2012} }","mla":"Oliveira, Marcio F., et al. “The System Verification Methodology for Advanced TLM Verification.” <i>CODES/ISSS ’12: Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Proceedings</i>, 2012.","apa":"Oliveira, M. F., Kuznik, C., Le, H. M., Große, D., Haedicke, F., Müller, W., Drechsler, R., Ecker, W., &#38; Esen, V. (2012). The System Verification Methodology for Advanced TLM Verification. <i>CODES/ISSS ’12: Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Proceedings</i>."},"_id":"25761","department":[{"_id":"672"}],"user_id":"21240","language":[{"iso":"eng"}],"publication":"CODES/ISSS '12: Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Proceedings","type":"conference","status":"public"},{"citation":{"ama":"He D, Müller W. A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms. In: <i>15th Euromicro Conference on Digital System Design (DSD)</i>. IEEE Xplore; 2012.","ieee":"D. He and W. Müller, “A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms,” 2012.","chicago":"He, Da, and Wolfgang Müller. “A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms.” In <i>15th Euromicro Conference on Digital System Design (DSD)</i>. IEEE Xplore, 2012.","apa":"He, D., &#38; Müller, W. (2012). A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms. <i>15th Euromicro Conference on Digital System Design (DSD)</i>.","bibtex":"@inproceedings{He_Müller_2012, title={A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms}, booktitle={15th Euromicro Conference on Digital System Design (DSD)}, publisher={IEEE Xplore}, author={He, Da and Müller, Wolfgang}, year={2012} }","short":"D. He, W. Müller, in: 15th Euromicro Conference on Digital System Design (DSD), IEEE Xplore, 2012.","mla":"He, Da, and Wolfgang Müller. “A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms.” <i>15th Euromicro Conference on Digital System Design (DSD)</i>, IEEE Xplore, 2012."},"year":"2012","date_created":"2021-10-07T12:11:29Z","author":[{"last_name":"He","full_name":"He, Da","first_name":"Da"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"}],"date_updated":"2022-01-06T06:57:12Z","publisher":"IEEE Xplore","title":"A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms","type":"conference","publication":"15th Euromicro Conference on Digital System Design (DSD)","status":"public","user_id":"21240","department":[{"_id":"672"}],"_id":"25767","language":[{"iso":"eng"}]},{"title":"Binary Mutation Testing Through Dynamic Translation","main_file_link":[{"url":"http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6263914&isnumber=6263904"}],"date_updated":"2022-01-06T06:57:15Z","date_created":"2021-10-11T08:39:53Z","author":[{"first_name":"Markus","last_name":"Becker","full_name":"Becker, Markus"},{"first_name":"Christoph","full_name":"Kuznik, Christoph","last_name":"Kuznik"},{"first_name":"M. tech. Mabel Mary","full_name":"Joy, M. tech. Mabel Mary","last_name":"Joy"},{"first_name":"Tao","last_name":"Xie","full_name":"Xie, Tao"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"}],"year":"2012","citation":{"ama":"Becker M, Kuznik C, Joy M tech. MM, Xie T, Müller W. Binary Mutation Testing Through Dynamic Translation. In: <i> 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)</i>. ; 2012.","chicago":"Becker, Markus, Christoph Kuznik, M. tech. Mabel Mary Joy, Tao Xie, and Wolfgang Müller. “Binary Mutation Testing Through Dynamic Translation.” In <i> 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)</i>, 2012.","ieee":"M. Becker, C. Kuznik, M. tech. M. M. Joy, T. Xie, and W. Müller, “Binary Mutation Testing Through Dynamic Translation,” 2012.","apa":"Becker, M., Kuznik, C., Joy, M. tech. M. M., Xie, T., &#38; Müller, W. (2012). Binary Mutation Testing Through Dynamic Translation. <i> 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)</i>.","short":"M. Becker, C. Kuznik, M. tech. M.M. Joy, T. Xie, W. Müller, in:  42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2012.","mla":"Becker, Markus, et al. “Binary Mutation Testing Through Dynamic Translation.” <i> 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)</i>, 2012.","bibtex":"@inproceedings{Becker_Kuznik_Joy_Xie_Müller_2012, title={Binary Mutation Testing Through Dynamic Translation}, booktitle={ 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)}, author={Becker, Markus and Kuznik, Christoph and Joy, M. tech. Mabel Mary and Xie, Tao and Müller, Wolfgang}, year={2012} }"},"language":[{"iso":"eng"}],"_id":"26022","department":[{"_id":"672"}],"user_id":"21240","status":"public","publication":" 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)","type":"conference"},{"title":"Enhanced Schedulability Analysis of Hard Real-Time Systems on Power Manageable Multi-Core Platforms","publisher":"IEEE Xplore","date_updated":"2022-01-06T06:57:15Z","date_created":"2021-10-11T08:43:05Z","author":[{"first_name":"Da","last_name":"He","full_name":"He, Da"},{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"}],"year":"2012","citation":{"bibtex":"@inproceedings{He_Müller_2012, title={Enhanced Schedulability Analysis of Hard Real-Time Systems on Power Manageable Multi-Core Platforms}, booktitle={Third International Symposium on Advances in Embedded Systems and Applications (ESA-2012)}, publisher={IEEE Xplore}, author={He, Da and Müller, Wolfgang}, year={2012} }","mla":"He, Da, and Wolfgang Müller. “Enhanced Schedulability Analysis of Hard Real-Time Systems on Power Manageable Multi-Core Platforms.” <i>Third International Symposium on Advances in Embedded Systems and Applications (ESA-2012)</i>, IEEE Xplore, 2012.","short":"D. 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IEEE Xplore, 2012."},"language":[{"iso":"eng"}],"_id":"26023","department":[{"_id":"672"}],"user_id":"21240","status":"public","publication":"Third International Symposium on Advances in Embedded Systems and Applications (ESA-2012)","type":"conference"},{"citation":{"apa":"Radke, S., Rülke, S., Oliveira, M. F., Kuznik, C., Müller, W., Ecker, W., Esen, V., Hufnagel, S., Bannow, N., Oetjens, J.-H., Brazdrum, H., Janssen, P., Le, H. M., Große, D., Haedicke, F., Drechsler, R., Koch, G., Burger, A., Bringmann, O., … Görgen, R. (2012). Compilation of Methodologies to Speed up the Verification Process at System Level. <i>EdaWorkshop 12</i>.","short":"S. Radke, S. Rülke, M.F. Oliveira, C. Kuznik, W. Müller, W. Ecker, V. Esen, S. Hufnagel, N. Bannow, J.-H. Oetjens, H. Brazdrum, P. Janssen, H.M. Le, D. Große, F. Haedicke, R. Drechsler, G. Koch, A. Burger, O. Bringmann, W. Rosenstiel, R. Görgen, in: EdaWorkshop 12, 2012.","bibtex":"@inproceedings{Radke_Rülke_Oliveira_Kuznik_Müller_Ecker_Esen_Hufnagel_Bannow_Oetjens_et al._2012, title={Compilation of Methodologies to Speed up the Verification Process at System Level}, booktitle={edaWorkshop 12}, author={Radke, Stephan and Rülke, Steffen and Oliveira, Marcio F. and Kuznik, Christoph and Müller, Wolfgang and Ecker, Wolfgang and Esen, Volkan and Hufnagel, Simon and Bannow, Nico and Oetjens, Jan-Hendrik and et al.}, year={2012} }","mla":"Radke, Stephan, et al. “Compilation of Methodologies to Speed up the Verification Process at System Level.” <i>EdaWorkshop 12</i>, 2012.","chicago":"Radke, Stephan, Steffen Rülke, Marcio F. Oliveira, Christoph Kuznik, Wolfgang Müller, Wolfgang Ecker, Volkan Esen, et al. “Compilation of Methodologies to Speed up the Verification Process at System Level.” In <i>EdaWorkshop 12</i>, 2012.","ieee":"S. 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IEEE Xplore; 2012.","chicago":"He, Da, and Wolfgang Müller. “Online Energy-Efficient Hard Real-Time Scheduling for Component Oriented Systems.” In <i>2012 IEEE 15th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC)</i>. IEEE Xplore, 2012.","ieee":"D. He and W. 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F., Kuznik, C., Müller, W., Ecker, W., &#38; Esen, V. (2012). A SystemC Library for Advanced TLM Verification. <i>Proceeding of Design and Verification Conference (DVCON)</i>.","bibtex":"@inproceedings{Oliveira_Kuznik_Müller_Ecker_Esen_2012, title={A SystemC Library for Advanced TLM Verification}, booktitle={Proceeding of Design and Verification Conference (DVCON)}, author={Oliveira, Marcio F. and Kuznik, Christoph and Müller, Wolfgang and Ecker, Wolfgang and Esen, Volkan}, year={2012} }","short":"M.F. Oliveira, C. Kuznik, W. Müller, W. Ecker, V. Esen, in: Proceeding of Design and Verification Conference (DVCON), 2012.","mla":"Oliveira, Marcio F., et al. “A SystemC Library for Advanced TLM Verification.” <i>Proceeding of Design and Verification Conference (DVCON)</i>, 2012.","ieee":"M. F. Oliveira, C. Kuznik, W. Müller, W. Ecker, and V. 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In: <i>Proceeding of Design and Verification Conference (DVCON)</i>. ; 2012."},"year":"2012"},{"_id":"26079","department":[{"_id":"672"}],"user_id":"21240","language":[{"iso":"eng"}],"publication":"Design, Automation and Test in Europe (DATE 2012)","type":"conference","status":"public","date_updated":"2022-01-06T06:57:16Z","date_created":"2021-10-12T10:06:15Z","author":[{"full_name":"Becker, Markus","last_name":"Becker","first_name":"Markus"},{"first_name":"Gilles Bertrand","full_name":"Gnokam Defo, Gilles Bertrand","last_name":"Gnokam Defo"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"},{"first_name":"F.","full_name":"Fummi, F.","last_name":"Fummi"},{"first_name":"G.","last_name":"Pravadelli","full_name":"Pravadelli, G."},{"last_name":"Vinco","full_name":"Vinco, Sara","first_name":"Sara"}],"title":"MOUSSE: scaling MOdelling and verification to complex heterogeneoUS embedded Systems Evolution","place":"Dresden","year":"2012","citation":{"ama":"Becker M, Gnokam Defo GB, Müller W, Fummi F, Pravadelli G, Vinco S. MOUSSE: scaling MOdelling and verification to complex heterogeneoUS embedded Systems Evolution. In: <i>Design, Automation and Test in Europe (DATE 2012)</i>. ; 2012.","ieee":"M. Becker, G. B. Gnokam Defo, W. Müller, F. Fummi, G. Pravadelli, and S. Vinco, “MOUSSE: scaling MOdelling and verification to complex heterogeneoUS embedded Systems Evolution,” 2012.","chicago":"Becker, Markus, Gilles Bertrand Gnokam Defo, Wolfgang Müller, F. Fummi, G. Pravadelli, and Sara Vinco. “MOUSSE: Scaling MOdelling and Verification to Complex HeterogeneoUS Embedded Systems Evolution.” In <i>Design, Automation and Test in Europe (DATE 2012)</i>. Dresden, 2012.","apa":"Becker, M., Gnokam Defo, G. B., Müller, W., Fummi, F., Pravadelli, G., &#38; Vinco, S. (2012). MOUSSE: scaling MOdelling and verification to complex heterogeneoUS embedded Systems Evolution. <i>Design, Automation and Test in Europe (DATE 2012)</i>.","bibtex":"@inproceedings{Becker_Gnokam Defo_Müller_Fummi_Pravadelli_Vinco_2012, place={Dresden}, title={MOUSSE: scaling MOdelling and verification to complex heterogeneoUS embedded Systems Evolution}, booktitle={Design, Automation and Test in Europe (DATE 2012)}, author={Becker, Markus and Gnokam Defo, Gilles Bertrand and Müller, Wolfgang and Fummi, F. and Pravadelli, G. and Vinco, Sara}, year={2012} }","mla":"Becker, Markus, et al. “MOUSSE: Scaling MOdelling and Verification to Complex HeterogeneoUS Embedded Systems Evolution.” <i>Design, Automation and Test in Europe (DATE 2012)</i>, 2012.","short":"M. Becker, G.B. Gnokam Defo, W. Müller, F. Fummi, G. Pravadelli, S. Vinco, in: Design, Automation and Test in Europe (DATE 2012), Dresden, 2012."}},{"citation":{"ieee":"M. Becker, C. Kuznik, M. tech. M. Joy, T. Xie, and W. Müller, “XEMU: A QEMU Based Binary Mutation Testing Framework,” 2012.","chicago":"Becker, Markus, Christoph Kuznik, M. tech. Mabel Joy, Tao Xie, and Wolfgang Müller. “XEMU: A QEMU Based Binary Mutation Testing Framework.” In <i>Design, Automation and Test in Europe DATE</i>. University Booth, Dresden, 2012.","ama":"Becker M, Kuznik C, Joy M tech. M, Xie T, Müller W. XEMU: A QEMU Based Binary Mutation Testing Framework. In: <i>Design, Automation and Test in Europe DATE</i>. ; 2012.","short":"M. Becker, C. Kuznik, M. tech. M. Joy, T. Xie, W. Müller, in: Design, Automation and Test in Europe DATE, University Booth, Dresden, 2012.","bibtex":"@inproceedings{Becker_Kuznik_Joy_Xie_Müller_2012, place={University Booth, Dresden}, title={XEMU: A QEMU Based Binary Mutation Testing Framework}, booktitle={Design, Automation and Test in Europe DATE}, author={Becker, Markus and Kuznik, Christoph and Joy, M. tech. Mabel and Xie, Tao and Müller, Wolfgang}, year={2012} }","mla":"Becker, Markus, et al. “XEMU: A QEMU Based Binary Mutation Testing Framework.” <i>Design, Automation and Test in Europe DATE</i>, 2012.","apa":"Becker, M., Kuznik, C., Joy, M. tech. M., Xie, T., &#38; Müller, W. (2012). XEMU: A QEMU Based Binary Mutation Testing Framework. <i>Design, Automation and Test in Europe DATE</i>."},"year":"2012","place":"University Booth, Dresden","date_created":"2021-10-12T10:57:15Z","author":[{"last_name":"Becker","full_name":"Becker, Markus","first_name":"Markus"},{"first_name":"Christoph","last_name":"Kuznik","full_name":"Kuznik, Christoph"},{"full_name":"Joy, M. tech. Mabel","last_name":"Joy","first_name":"M. tech. Mabel"},{"last_name":"Xie","full_name":"Xie, Tao","first_name":"Tao"},{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"}],"date_updated":"2022-01-06T06:57:16Z","title":"XEMU: A QEMU Based Binary Mutation Testing Framework","publication":"Design, Automation and Test in Europe DATE","type":"conference","status":"public","department":[{"_id":"672"}],"user_id":"21240","_id":"26080","language":[{"iso":"eng"}]},{"_id":"26092","user_id":"21240","department":[{"_id":"672"}],"language":[{"iso":"eng"}],"type":"conference","publication":"In Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012","status":"public","date_updated":"2022-01-06T06:57:16Z","date_created":"2021-10-13T10:36:35Z","author":[{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"},{"first_name":"Markus","full_name":"Becker, Markus","last_name":"Becker"},{"last_name":"Zabel","full_name":"Zabel, Henning","first_name":"Henning"},{"first_name":"Ahmed","full_name":"Elfeky, Ahmed","last_name":"Elfeky"},{"full_name":"DiPasquale, Anthony","last_name":"DiPasquale","first_name":"Anthony"}],"title":"Virtual Prototyping of Cyber-Physical Systems","year":"2012","place":"Sydney","citation":{"chicago":"Müller, Wolfgang, Markus Becker, Henning Zabel, Ahmed Elfeky, and Anthony DiPasquale. “Virtual Prototyping of Cyber-Physical Systems.” In <i>In Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012</i>. Sydney, 2012.","ieee":"W. Müller, M. Becker, H. Zabel, A. Elfeky, and A. DiPasquale, “Virtual Prototyping of Cyber-Physical Systems,” 2012.","ama":"Müller W, Becker M, Zabel H, Elfeky A, DiPasquale A. Virtual Prototyping of Cyber-Physical Systems. In: <i>In Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012</i>. ; 2012.","apa":"Müller, W., Becker, M., Zabel, H., Elfeky, A., &#38; DiPasquale, A. (2012). Virtual Prototyping of Cyber-Physical Systems. <i>In Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012</i>.","mla":"Müller, Wolfgang, et al. “Virtual Prototyping of Cyber-Physical Systems.” <i>In Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012</i>, 2012.","bibtex":"@inproceedings{Müller_Becker_Zabel_Elfeky_DiPasquale_2012, place={Sydney}, title={Virtual Prototyping of Cyber-Physical Systems}, booktitle={In Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012}, author={Müller, Wolfgang and Becker, Markus and Zabel, Henning and Elfeky, Ahmed and DiPasquale, Anthony}, year={2012} }","short":"W. Müller, M. Becker, H. Zabel, A. Elfeky, A. DiPasquale, in: In Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012, Sydney, 2012."}},{"abstract":[{"text":"The Unified Modeling Language (UML) is now widely accepted by the software community. More recently, UML has attracted attention as a unification language for systems description combining both hardware and software components. First, it has been recognized that electronic systems design can no longer be seen as an isolated hardware design activity. In addition, recent advances in tools supporting high level hardware synthesis from electronic system level languages, which are predominantly based on C/C++, open new perspectives for automatic code generation from UML models and opportunities to enhance the link between a high level specification and a concrete hardware/software implementation. Finally, UML has become a general purpose language which can be customized for specific purposes, such as the modelization of electronic systems. This chapter presents recent advances of the UML language applied to System-on-Chip (SoC) and hardware-related embedded systems design. In particular, several examples of specific UML customizations (UML profiles) relevant for SoC design are summarized. Various approaches associating UML with existing hardware/software design languages are presented. The question of tool support and association with well-known simulation environments, such as MATLAB/Simulink, is addressed as well. A concrete example of a UML profile for hardware/software co-modeling and code generation for hardware/software co-simulation is presented in more details for illustration purposes.","lang":"eng"}],"editor":[{"first_name":"Gabriela","last_name":"Nicolescu","full_name":"Nicolescu, Gabriela"},{"first_name":"Ian","last_name":"O'Connor","full_name":"O'Connor, Ian"},{"first_name":"Christian","last_name":"Piguet","full_name":"Piguet, Christian"}],"status":"public","publication":"Design Technology for Heterogeneous Embedded Systems","type":"book_chapter","language":[{"iso":"eng"}],"_id":"26695","department":[{"_id":"672"}],"user_id":"5786","year":"2012","page":"13-39","citation":{"ieee":"Y. Vanderperren, W. Müller, D. He, F. Mischkalla, and W. Dahaene, “Extending UML for Electronic Systems Design: A Code Generation Perspective,” in <i>Design Technology for Heterogeneous Embedded Systems</i>, 1st Edition. Auflage., G. Nicolescu, I. O’Connor, and C. Piguet, Eds. Springer Verlag, 2012, pp. 13–39.","chicago":"Vanderperren, Yves, Wolfgang Müller, Da He, Fabian Mischkalla, and Wim Dahaene. “Extending UML for Electronic Systems Design: A Code Generation Perspective.” In <i>Design Technology for Heterogeneous Embedded Systems</i>, edited by Gabriela Nicolescu, Ian O’Connor, and Christian Piguet, 1st Edition. Auflage., 13–39. Springer Verlag, 2012.","ama":"Vanderperren Y, Müller W, He D, Mischkalla F, Dahaene W. Extending UML for Electronic Systems Design: A Code Generation Perspective. In: Nicolescu G, O’Connor I, Piguet C, eds. <i>Design Technology for Heterogeneous Embedded Systems</i>. 1st Edition. Auflage. Springer Verlag; 2012:13-39.","bibtex":"@inbook{Vanderperren_Müller_He_Mischkalla_Dahaene_2012, edition={1st Edition. Auflage}, title={Extending UML for Electronic Systems Design: A Code Generation Perspective}, booktitle={Design Technology for Heterogeneous Embedded Systems}, publisher={Springer Verlag}, author={Vanderperren, Yves and Müller, Wolfgang and He, Da and Mischkalla, Fabian and Dahaene, Wim}, editor={Nicolescu, Gabriela and O’Connor, Ian and Piguet, Christian}, year={2012}, pages={13–39} }","short":"Y. Vanderperren, W. Müller, D. He, F. Mischkalla, W. Dahaene, in: G. Nicolescu, I. O’Connor, C. Piguet (Eds.), Design Technology for Heterogeneous Embedded Systems, 1st Edition. Auflage, Springer Verlag, 2012, pp. 13–39.","mla":"Vanderperren, Yves, et al. “Extending UML for Electronic Systems Design: A Code Generation Perspective.” <i>Design Technology for Heterogeneous Embedded Systems</i>, edited by Gabriela Nicolescu et al., 1st Edition. Auflage, Springer Verlag, 2012, pp. 13–39.","apa":"Vanderperren, Y., Müller, W., He, D., Mischkalla, F., &#38; Dahaene, W. (2012). Extending UML for Electronic Systems Design: A Code Generation Perspective. In G. Nicolescu, I. O’Connor, &#38; C. Piguet (Eds.), <i>Design Technology for Heterogeneous Embedded Systems</i> (1st Edition. Auflage, pp. 13–39). Springer Verlag."},"publication_identifier":{"isbn":["978-94-007-1125-9"]},"edition":"1st Edition. Auflage","title":"Extending UML for Electronic Systems Design: A Code Generation Perspective","date_updated":"2022-10-18T09:53:40Z","publisher":"Springer Verlag","author":[{"last_name":"Vanderperren","full_name":"Vanderperren, Yves","first_name":"Yves"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"},{"full_name":"He, Da","last_name":"He","first_name":"Da"},{"last_name":"Mischkalla","full_name":"Mischkalla, Fabian","first_name":"Fabian"},{"last_name":"Dahaene","full_name":"Dahaene, Wim","first_name":"Wim"}],"date_created":"2021-10-21T12:14:17Z"},{"abstract":[{"text":"We present an enhanced UVM for SystemC library which incorporates verification best practices from OVM-ML and UVM as well as project partner implementations. Moreover, we extended functionality and implemented missing features, such as domain specific components, stimuli sequence generation and management, call-back facilities, response to request routing, transaction recording and many more. Apart from that, we added crucial verification components, such as functional coverage.","lang":"eng"}],"status":"public","type":"journal_article","publication":"Design, Automation and Test in Europe DATE","language":[{"iso":"eng"}],"_id":"26038","user_id":"5786","department":[{"_id":"672"}],"year":"2012","citation":{"ama":"Kuznik C, Oliveira MF, Müller W. SYSTEMC UVM VERIFICATION COMPONENTS. <i>Design, Automation and Test in Europe DATE</i>. Published online 2012.","ieee":"C. Kuznik, M. F. Oliveira, and W. Müller, “SYSTEMC UVM VERIFICATION COMPONENTS,” <i>Design, Automation and Test in Europe DATE</i>, 2012.","chicago":"Kuznik, Christoph, Marcio F. Oliveira, and Wolfgang Müller. “SYSTEMC UVM VERIFICATION COMPONENTS.” <i>Design, Automation and Test in Europe DATE</i>, 2012.","short":"C. Kuznik, M.F. Oliveira, W. Müller, Design, Automation and Test in Europe DATE (2012).","bibtex":"@article{Kuznik_Oliveira_Müller_2012, title={SYSTEMC UVM VERIFICATION COMPONENTS}, journal={Design, Automation and Test in Europe DATE}, author={Kuznik, Christoph and Oliveira, Marcio F. and Müller, Wolfgang}, year={2012} }","mla":"Kuznik, Christoph, et al. “SYSTEMC UVM VERIFICATION COMPONENTS.” <i>Design, Automation and Test in Europe DATE</i>, 2012.","apa":"Kuznik, C., Oliveira, M. F., &#38; Müller, W. (2012). SYSTEMC UVM VERIFICATION COMPONENTS. <i>Design, Automation and Test in Europe DATE</i>."},"title":"SYSTEMC UVM VERIFICATION COMPONENTS","conference":{"location":" University Booth, Dresden , Mrz. 2012"},"date_updated":"2024-04-18T21:07:25Z","date_created":"2021-10-11T12:48:21Z","author":[{"full_name":"Kuznik, Christoph","last_name":"Kuznik","first_name":"Christoph"},{"first_name":"Marcio F.","full_name":"Oliveira, Marcio F.","last_name":"Oliveira"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"}]},{"citation":{"ama":"Müller W, Ecker W, eds. <i>Proceedings of the 1st Workshop on Metamodelling and Code Generation for Embedded Systems - MeCoEs </i>.; 2012.","chicago":"Müller, Wolfgang, and Wolfgang Ecker, eds. <i>Proceedings of the 1st Workshop on Metamodelling and Code Generation for Embedded Systems - MeCoEs </i>. Tampere, Finland, 2012.","ieee":"W. Müller and W. Ecker, Eds., <i>Proceedings of the 1st Workshop on Metamodelling and Code Generation for Embedded Systems - MeCoEs </i>. Tampere, Finland, 2012.","apa":"Müller, W., &#38; Ecker, W. (Eds.). (2012). <i>Proceedings of the 1st Workshop on Metamodelling and Code Generation for Embedded Systems - MeCoEs </i>.","mla":"Müller, Wolfgang, and Wolfgang Ecker, editors. <i>Proceedings of the 1st Workshop on Metamodelling and Code Generation for Embedded Systems - MeCoEs </i>. 2012.","short":"W. Müller, W. Ecker, eds., Proceedings of the 1st Workshop on Metamodelling and Code Generation for Embedded Systems - MeCoEs , Tampere, Finland, 2012.","bibtex":"@book{Müller_Ecker_2012, place={Tampere, Finland}, title={Proceedings of the 1st Workshop on Metamodelling and Code Generation for Embedded Systems - MeCoEs }, year={2012} }"},"year":"2012","place":"Tampere, Finland","date_created":"2024-04-18T21:48:40Z","date_updated":"2024-04-18T22:10:42Z","title":"Proceedings of the 1st Workshop on Metamodelling and Code Generation for Embedded Systems - MeCoEs ","type":"book_editor","status":"public","editor":[{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"full_name":"Ecker, Wolfgang","last_name":"Ecker","first_name":"Wolfgang"}],"user_id":"16243","department":[{"_id":"58"}],"_id":"53593","language":[{"iso":"eng"}]}]