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Vinco, in: Design, Automation and Test in Europe (DATE 2012), Dresden, 2012.","bibtex":"@inproceedings{Becker_Gnokam Defo_Müller_Fummi_Pravadelli_Vinco_2012, place={Dresden}, title={MOUSSE: scaling MOdelling and verification to complex heterogeneoUS embedded Systems Evolution}, booktitle={Design, Automation and Test in Europe (DATE 2012)}, author={Becker, Markus and Gnokam Defo, Gilles Bertrand and Müller, Wolfgang and Fummi, F. and Pravadelli, G. and Vinco, Sara}, year={2012} }","mla":"Becker, Markus, et al. “MOUSSE: Scaling MOdelling and Verification to Complex HeterogeneoUS Embedded Systems Evolution.” <i>Design, Automation and Test in Europe (DATE 2012)</i>, 2012."},"user_id":"21240","place":"Dresden","title":"MOUSSE: scaling MOdelling and verification to complex heterogeneoUS embedded Systems Evolution","author":[{"first_name":"Markus","full_name":"Becker, Markus","last_name":"Becker"},{"full_name":"Gnokam Defo, Gilles Bertrand","first_name":"Gilles Bertrand","last_name":"Gnokam Defo"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"first_name":"F.","full_name":"Fummi, F.","last_name":"Fummi"},{"full_name":"Pravadelli, G.","first_name":"G.","last_name":"Pravadelli"},{"full_name":"Vinco, Sara","first_name":"Sara","last_name":"Vinco"}]},{"_id":"26080","date_updated":"2022-01-06T06:57:16Z","date_created":"2021-10-12T10:57:15Z","publication":"Design, Automation and Test in Europe DATE","language":[{"iso":"eng"}],"year":"2012","type":"conference","status":"public","citation":{"chicago":"Becker, Markus, Christoph Kuznik, M. tech. Mabel Joy, Tao Xie, and Wolfgang Müller. “XEMU: A QEMU Based Binary Mutation Testing Framework.” In <i>Design, Automation and Test in Europe DATE</i>. University Booth, Dresden, 2012.","ieee":"M. Becker, C. Kuznik, M. tech. M. Joy, T. Xie, and W. Müller, “XEMU: A QEMU Based Binary Mutation Testing Framework,” 2012.","ama":"Becker M, Kuznik C, Joy M tech. M, Xie T, Müller W. XEMU: A QEMU Based Binary Mutation Testing Framework. In: <i>Design, Automation and Test in Europe DATE</i>. ; 2012.","apa":"Becker, M., Kuznik, C., Joy, M. tech. M., Xie, T., &#38; Müller, W. (2012). XEMU: A QEMU Based Binary Mutation Testing Framework. <i>Design, Automation and Test in Europe DATE</i>.","short":"M. Becker, C. Kuznik, M. tech. M. Joy, T. Xie, W. Müller, in: Design, Automation and Test in Europe DATE, University Booth, Dresden, 2012.","mla":"Becker, Markus, et al. “XEMU: A QEMU Based Binary Mutation Testing Framework.” <i>Design, Automation and Test in Europe DATE</i>, 2012.","bibtex":"@inproceedings{Becker_Kuznik_Joy_Xie_Müller_2012, place={University Booth, Dresden}, title={XEMU: A QEMU Based Binary Mutation Testing Framework}, booktitle={Design, Automation and Test in Europe DATE}, author={Becker, Markus and Kuznik, Christoph and Joy, M. tech. Mabel and Xie, Tao and Müller, Wolfgang}, year={2012} }"},"user_id":"21240","department":[{"_id":"672"}],"title":"XEMU: A QEMU Based Binary Mutation Testing Framework","author":[{"full_name":"Becker, Markus","first_name":"Markus","last_name":"Becker"},{"last_name":"Kuznik","full_name":"Kuznik, Christoph","first_name":"Christoph"},{"last_name":"Joy","first_name":"M. tech. Mabel","full_name":"Joy, M. tech. Mabel"},{"last_name":"Xie","full_name":"Xie, Tao","first_name":"Tao"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","last_name":"Müller","id":"16243"}],"place":"University Booth, Dresden"},{"department":[{"_id":"672"}],"citation":{"ieee":"W. Müller, M. Becker, H. Zabel, A. Elfeky, and A. DiPasquale, “Virtual Prototyping of Cyber-Physical Systems,” 2012.","chicago":"Müller, Wolfgang, Markus Becker, Henning Zabel, Ahmed Elfeky, and Anthony DiPasquale. “Virtual Prototyping of Cyber-Physical Systems.” In <i>In Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012</i>. Sydney, 2012.","ama":"Müller W, Becker M, Zabel H, Elfeky A, DiPasquale A. Virtual Prototyping of Cyber-Physical Systems. In: <i>In Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012</i>. ; 2012.","apa":"Müller, W., Becker, M., Zabel, H., Elfeky, A., &#38; DiPasquale, A. (2012). Virtual Prototyping of Cyber-Physical Systems. <i>In Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012</i>.","short":"W. Müller, M. Becker, H. Zabel, A. Elfeky, A. DiPasquale, in: In Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012, Sydney, 2012.","bibtex":"@inproceedings{Müller_Becker_Zabel_Elfeky_DiPasquale_2012, place={Sydney}, title={Virtual Prototyping of Cyber-Physical Systems}, booktitle={In Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012}, author={Müller, Wolfgang and Becker, Markus and Zabel, Henning and Elfeky, Ahmed and DiPasquale, Anthony}, year={2012} }","mla":"Müller, Wolfgang, et al. “Virtual Prototyping of Cyber-Physical Systems.” <i>In Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012</i>, 2012."},"user_id":"21240","place":"Sydney","title":"Virtual Prototyping of Cyber-Physical Systems","author":[{"full_name":"Müller, Wolfgang","first_name":"Wolfgang","id":"16243","last_name":"Müller"},{"first_name":"Markus","full_name":"Becker, Markus","last_name":"Becker"},{"last_name":"Zabel","full_name":"Zabel, Henning","first_name":"Henning"},{"last_name":"Elfeky","first_name":"Ahmed","full_name":"Elfeky, Ahmed"},{"first_name":"Anthony","full_name":"DiPasquale, Anthony","last_name":"DiPasquale"}],"date_updated":"2022-01-06T06:57:16Z","_id":"26092","year":"2012","type":"conference","language":[{"iso":"eng"}],"status":"public","publication":"In Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012","date_created":"2021-10-13T10:36:35Z"},{"citation":{"bibtex":"@inbook{Vanderperren_Müller_He_Mischkalla_Dahaene_2012, edition={1st Edition. Auflage}, title={Extending UML for Electronic Systems Design: A Code Generation Perspective}, booktitle={Design Technology for Heterogeneous Embedded Systems}, publisher={Springer Verlag}, author={Vanderperren, Yves and Müller, Wolfgang and He, Da and Mischkalla, Fabian and Dahaene, Wim}, editor={Nicolescu, Gabriela and O’Connor, Ian and Piguet, Christian}, year={2012}, pages={13–39} }","mla":"Vanderperren, Yves, et al. “Extending UML for Electronic Systems Design: A Code Generation Perspective.” <i>Design Technology for Heterogeneous Embedded Systems</i>, edited by Gabriela Nicolescu et al., 1st Edition. Auflage, Springer Verlag, 2012, pp. 13–39.","short":"Y. Vanderperren, W. Müller, D. He, F. Mischkalla, W. Dahaene, in: G. Nicolescu, I. O’Connor, C. Piguet (Eds.), Design Technology for Heterogeneous Embedded Systems, 1st Edition. Auflage, Springer Verlag, 2012, pp. 13–39.","ama":"Vanderperren Y, Müller W, He D, Mischkalla F, Dahaene W. Extending UML for Electronic Systems Design: A Code Generation Perspective. In: Nicolescu G, O’Connor I, Piguet C, eds. <i>Design Technology for Heterogeneous Embedded Systems</i>. 1st Edition. Auflage. Springer Verlag; 2012:13-39.","apa":"Vanderperren, Y., Müller, W., He, D., Mischkalla, F., &#38; Dahaene, W. (2012). Extending UML for Electronic Systems Design: A Code Generation Perspective. In G. Nicolescu, I. O’Connor, &#38; C. Piguet (Eds.), <i>Design Technology for Heterogeneous Embedded Systems</i> (1st Edition. Auflage, pp. 13–39). Springer Verlag.","ieee":"Y. Vanderperren, W. Müller, D. He, F. Mischkalla, and W. Dahaene, “Extending UML for Electronic Systems Design: A Code Generation Perspective,” in <i>Design Technology for Heterogeneous Embedded Systems</i>, 1st Edition. Auflage., G. Nicolescu, I. O’Connor, and C. Piguet, Eds. Springer Verlag, 2012, pp. 13–39.","chicago":"Vanderperren, Yves, Wolfgang Müller, Da He, Fabian Mischkalla, and Wim Dahaene. “Extending UML for Electronic Systems Design: A Code Generation Perspective.” In <i>Design Technology for Heterogeneous Embedded Systems</i>, edited by Gabriela Nicolescu, Ian O’Connor, and Christian Piguet, 1st Edition. Auflage., 13–39. Springer Verlag, 2012."},"user_id":"5786","department":[{"_id":"672"}],"title":"Extending UML for Electronic Systems Design: A Code Generation Perspective","editor":[{"first_name":"Gabriela","full_name":"Nicolescu, Gabriela","last_name":"Nicolescu"},{"full_name":"O'Connor, Ian","first_name":"Ian","last_name":"O'Connor"},{"last_name":"Piguet","first_name":"Christian","full_name":"Piguet, Christian"}],"author":[{"first_name":"Yves","full_name":"Vanderperren, Yves","last_name":"Vanderperren"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"last_name":"He","first_name":"Da","full_name":"He, Da"},{"last_name":"Mischkalla","first_name":"Fabian","full_name":"Mischkalla, Fabian"},{"last_name":"Dahaene","first_name":"Wim","full_name":"Dahaene, Wim"}],"abstract":[{"text":"The Unified Modeling Language (UML) is now widely accepted by the software community. More recently, UML has attracted attention as a unification language for systems description combining both hardware and software components. First, it has been recognized that electronic systems design can no longer be seen as an isolated hardware design activity. In addition, recent advances in tools supporting high level hardware synthesis from electronic system level languages, which are predominantly based on C/C++, open new perspectives for automatic code generation from UML models and opportunities to enhance the link between a high level specification and a concrete hardware/software implementation. Finally, UML has become a general purpose language which can be customized for specific purposes, such as the modelization of electronic systems. This chapter presents recent advances of the UML language applied to System-on-Chip (SoC) and hardware-related embedded systems design. In particular, several examples of specific UML customizations (UML profiles) relevant for SoC design are summarized. Various approaches associating UML with existing hardware/software design languages are presented. The question of tool support and association with well-known simulation environments, such as MATLAB/Simulink, is addressed as well. A concrete example of a UML profile for hardware/software co-modeling and code generation for hardware/software co-simulation is presented in more details for illustration purposes.","lang":"eng"}],"_id":"26695","page":"13-39","date_updated":"2022-10-18T09:53:40Z","edition":"1st Edition. Auflage","publication":"Design Technology for Heterogeneous Embedded Systems","date_created":"2021-10-21T12:14:17Z","publisher":"Springer Verlag","year":"2012","type":"book_chapter","publication_identifier":{"isbn":["978-94-007-1125-9"]},"language":[{"iso":"eng"}],"status":"public"},{"abstract":[{"lang":"eng","text":"We present an enhanced UVM for SystemC library which incorporates verification best practices from OVM-ML and UVM as well as project partner implementations. Moreover, we extended functionality and implemented missing features, such as domain specific components, stimuli sequence generation and management, call-back facilities, response to request routing, transaction recording and many more. Apart from that, we added crucial verification components, such as functional coverage."}],"author":[{"first_name":"Christoph","full_name":"Kuznik, Christoph","last_name":"Kuznik"},{"last_name":"Oliveira","full_name":"Oliveira, Marcio F.","first_name":"Marcio F."},{"id":"16243","last_name":"Müller","full_name":"Müller, Wolfgang","first_name":"Wolfgang"}],"conference":{"location":" University Booth, Dresden , Mrz. 2012"},"title":"SYSTEMC UVM VERIFICATION COMPONENTS","department":[{"_id":"672"}],"user_id":"5786","citation":{"short":"C. Kuznik, M.F. Oliveira, W. Müller, Design, Automation and Test in Europe DATE (2012).","mla":"Kuznik, Christoph, et al. “SYSTEMC UVM VERIFICATION COMPONENTS.” <i>Design, Automation and Test in Europe DATE</i>, 2012.","bibtex":"@article{Kuznik_Oliveira_Müller_2012, title={SYSTEMC UVM VERIFICATION COMPONENTS}, journal={Design, Automation and Test in Europe DATE}, author={Kuznik, Christoph and Oliveira, Marcio F. and Müller, Wolfgang}, year={2012} }","chicago":"Kuznik, Christoph, Marcio F. Oliveira, and Wolfgang Müller. “SYSTEMC UVM VERIFICATION COMPONENTS.” <i>Design, Automation and Test in Europe DATE</i>, 2012.","ieee":"C. Kuznik, M. F. Oliveira, and W. Müller, “SYSTEMC UVM VERIFICATION COMPONENTS,” <i>Design, Automation and Test in Europe DATE</i>, 2012.","apa":"Kuznik, C., Oliveira, M. F., &#38; Müller, W. (2012). SYSTEMC UVM VERIFICATION COMPONENTS. <i>Design, Automation and Test in Europe DATE</i>.","ama":"Kuznik C, Oliveira MF, Müller W. SYSTEMC UVM VERIFICATION COMPONENTS. <i>Design, Automation and Test in Europe DATE</i>. Published online 2012."},"status":"public","year":"2012","type":"journal_article","language":[{"iso":"eng"}],"publication":"Design, Automation and Test in Europe DATE","date_created":"2021-10-11T12:48:21Z","date_updated":"2024-04-18T21:07:25Z","_id":"26038"},{"editor":[{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"first_name":"Wolfgang","full_name":"Ecker, Wolfgang","last_name":"Ecker"}],"title":"Proceedings of the 1st Workshop on Metamodelling and Code Generation for Embedded Systems - MeCoEs ","place":"Tampere, Finland","user_id":"16243","citation":{"mla":"Müller, Wolfgang, and Wolfgang Ecker, editors. <i>Proceedings of the 1st Workshop on Metamodelling and Code Generation for Embedded Systems - MeCoEs </i>. 2012.","apa":"Müller, W., &#38; Ecker, W. (Eds.). (2012). <i>Proceedings of the 1st Workshop on Metamodelling and Code Generation for Embedded Systems - MeCoEs </i>.","bibtex":"@book{Müller_Ecker_2012, place={Tampere, Finland}, title={Proceedings of the 1st Workshop on Metamodelling and Code Generation for Embedded Systems - MeCoEs }, year={2012} }","ama":"Müller W, Ecker W, eds. <i>Proceedings of the 1st Workshop on Metamodelling and Code Generation for Embedded Systems - MeCoEs </i>.; 2012.","chicago":"Müller, Wolfgang, and Wolfgang Ecker, eds. <i>Proceedings of the 1st Workshop on Metamodelling and Code Generation for Embedded Systems - MeCoEs </i>. Tampere, Finland, 2012.","short":"W. Müller, W. Ecker, eds., Proceedings of the 1st Workshop on Metamodelling and Code Generation for Embedded Systems - MeCoEs , Tampere, Finland, 2012.","ieee":"W. Müller and W. Ecker, Eds., <i>Proceedings of the 1st Workshop on Metamodelling and Code Generation for Embedded Systems - MeCoEs </i>. Tampere, Finland, 2012."},"department":[{"_id":"58"}],"date_created":"2024-04-18T21:48:40Z","status":"public","language":[{"iso":"eng"}],"year":"2012","type":"book_editor","_id":"53593","date_updated":"2024-04-18T22:10:42Z"},{"date_updated":"2023-01-16T12:25:33Z","_id":"36922","language":[{"iso":"eng"}],"year":"2012","type":"conference","publication_identifier":{"eisbn":["978-0-7695-4669-8"]},"status":"public","date_created":"2023-01-16T12:23:50Z","publisher":"IEEE","department":[{"_id":"672"}],"citation":{"bibtex":"@inproceedings{Klobedanz_Müller_Rettberg_2012, place={Shenzhen, China }, title={An Approach for Self-Reconfiguring and Fault-Tolerant Distributed Real-Time Systems}, DOI={<a href=\"https://doi.org/10.1109/ISORCW.2012.41\">10.1109/ISORCW.2012.41</a>}, publisher={IEEE}, author={Klobedanz, Kay and Müller, Wolfgang and Rettberg, Achim}, year={2012} }","mla":"Klobedanz, Kay, et al. <i>An Approach for Self-Reconfiguring and Fault-Tolerant Distributed Real-Time Systems</i>. IEEE, 2012, doi:<a href=\"https://doi.org/10.1109/ISORCW.2012.41\">10.1109/ISORCW.2012.41</a>.","short":"K. Klobedanz, W. Müller, A. Rettberg, in: IEEE, Shenzhen, China , 2012.","ama":"Klobedanz K, Müller W, Rettberg A. An Approach for Self-Reconfiguring and Fault-Tolerant Distributed Real-Time Systems. In: IEEE; 2012. doi:<a href=\"https://doi.org/10.1109/ISORCW.2012.41\">10.1109/ISORCW.2012.41</a>","apa":"Klobedanz, K., Müller, W., &#38; Rettberg, A. (2012). <i>An Approach for Self-Reconfiguring and Fault-Tolerant Distributed Real-Time Systems</i>. IEEE 15th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops. <a href=\"https://doi.org/10.1109/ISORCW.2012.41\">https://doi.org/10.1109/ISORCW.2012.41</a>","ieee":"K. Klobedanz, W. Müller, and A. Rettberg, “An Approach for Self-Reconfiguring and Fault-Tolerant Distributed Real-Time Systems,” presented at the IEEE 15th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2012, doi: <a href=\"https://doi.org/10.1109/ISORCW.2012.41\">10.1109/ISORCW.2012.41</a>.","chicago":"Klobedanz, Kay, Wolfgang Müller, and Achim Rettberg. “An Approach for Self-Reconfiguring and Fault-Tolerant Distributed Real-Time Systems.” Shenzhen, China : IEEE, 2012. <a href=\"https://doi.org/10.1109/ISORCW.2012.41\">https://doi.org/10.1109/ISORCW.2012.41</a>."},"keyword":["Real time systems","Fault tolerant systems","Schedules","Protocols","Redundancy","Delay"],"user_id":"5786","place":"Shenzhen, China ","doi":"10.1109/ISORCW.2012.41","abstract":[{"lang":"eng","text":"In this paper we present an approach for the self reconfiguration of distributed micro-controllers for increased fault tolerance. Based on a modified distributed system topology utilizing a time division multiple access (TDMA) protocol, i.e., Flex Ray, we present a self-organized distributed coordinator concept which performs the self-reconfiguration in the case of node failures. We introduce a distributed coordinator, which utilizes redundant slots in the Flex Ray communication schedule and combines messages in configured protocol frames and slots to avoid a complete bus restart. As such, the self-reconfiguration is realized by means of predetermined information about resulting changes in the communication dependencies and (re-)assignments determined in the design phase. To retrieve the necessary information, we present an analytical approach, which determines a combined solution for the initial configuration and all possible reconfigurations for the remaining nodes of the Flex Ray network in case of node failures. Hence, through this method we can design self-reconfiguring network-based systems enabling the handling of node failures for an increased fault tolerance."}],"title":"An Approach for Self-Reconfiguring and Fault-Tolerant Distributed Real-Time Systems","conference":{"name":"IEEE 15th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops"},"author":[{"last_name":"Klobedanz","first_name":"Kay","full_name":"Klobedanz, Kay"},{"full_name":"Müller, Wolfgang","first_name":"Wolfgang","id":"16243","last_name":"Müller"},{"first_name":"Achim","full_name":"Rettberg, Achim","last_name":"Rettberg"}]},{"year":"2012","type":"conference","language":[{"iso":"eng"}],"status":"public","publication":"Proceedings of the Design & Verification Conference (DVCon)","date_created":"2023-01-16T12:19:39Z","date_updated":"2023-01-16T12:21:17Z","_id":"36921","place":"San Jose","title":"Towards an Enhanced UVM for SystemC","author":[{"first_name":"M. F.","full_name":"Oliveira, M. F.","last_name":"Oliveira"},{"full_name":"Kuznik, Christoph","first_name":"Christoph","last_name":"Kuznik"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","last_name":"Müller","id":"16243"},{"last_name":"Esen","full_name":"Esen, V.","first_name":"V."},{"last_name":"Ecker","first_name":"W.","full_name":"Ecker, W."}],"department":[{"_id":"672"}],"citation":{"ieee":"M. F. Oliveira, C. Kuznik, W. Müller, V. Esen, and W. Ecker, “Towards an Enhanced UVM for SystemC,” 2012.","short":"M.F. Oliveira, C. Kuznik, W. Müller, V. Esen, W. Ecker, in: Proceedings of the Design &#38; Verification Conference (DVCon), San Jose, 2012.","chicago":"Oliveira, M. F., Christoph Kuznik, Wolfgang Müller, V. Esen, and W. Ecker. “Towards an Enhanced UVM for SystemC.” In <i>Proceedings of the Design &#38; Verification Conference (DVCon)</i>. San Jose, 2012.","bibtex":"@inproceedings{Oliveira_Kuznik_Müller_Esen_Ecker_2012, place={San Jose}, title={Towards an Enhanced UVM for SystemC}, booktitle={Proceedings of the Design &#38; Verification Conference (DVCon)}, author={Oliveira, M. F. and Kuznik, Christoph and Müller, Wolfgang and Esen, V. and Ecker, W.}, year={2012} }","ama":"Oliveira MF, Kuznik C, Müller W, Esen V, Ecker W. Towards an Enhanced UVM for SystemC. In: <i>Proceedings of the Design &#38; Verification Conference (DVCon)</i>. ; 2012.","apa":"Oliveira, M. F., Kuznik, C., Müller, W., Esen, V., &#38; Ecker, W. (2012). Towards an Enhanced UVM for SystemC. <i>Proceedings of the Design &#38; Verification Conference (DVCon)</i>.","mla":"Oliveira, M. F., et al. “Towards an Enhanced UVM for SystemC.” <i>Proceedings of the Design &#38; Verification Conference (DVCon)</i>, 2012."},"user_id":"5786"},{"_id":"36994","date_updated":"2023-01-17T08:46:29Z","publisher":"IEEE","publication":"Proceedings of SOCC2012","date_created":"2023-01-17T08:46:14Z","status":"public","type":"conference","publication_identifier":{"eisbn":["978-1-4673-1295-0"]},"year":"2012","language":[{"iso":"eng"}],"user_id":"5786","keyword":["Analytical models","Hardware design languages","Microprocessors","Cost function","Data models","Search problems","IP networks"],"citation":{"apa":"Xie, T., Müller, W., &#38; Letombe, F. (2012). Mutation-Analysis Driven Functional Verification of a Soft Microprocessor. <i>Proceedings of SOCC2012</i>. <a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">https://doi.org/10.1109/SOCC.2012.6398362</a>","ama":"Xie T, Müller W, Letombe F. Mutation-Analysis Driven Functional Verification of a Soft Microprocessor. In: <i>Proceedings of SOCC2012</i>. IEEE; 2012. doi:<a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">10.1109/SOCC.2012.6398362</a>","bibtex":"@inproceedings{Xie_Müller_Letombe_2012, place={ Niagara Falls, NY, USA }, title={Mutation-Analysis Driven Functional Verification of a Soft Microprocessor}, DOI={<a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">10.1109/SOCC.2012.6398362</a>}, booktitle={Proceedings of SOCC2012}, publisher={IEEE}, author={Xie, Tao  and Müller, Wolfgang and Letombe, Florian}, year={2012} }","mla":"Xie, Tao, et al. “Mutation-Analysis Driven Functional Verification of a Soft Microprocessor.” <i>Proceedings of SOCC2012</i>, IEEE, 2012, doi:<a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">10.1109/SOCC.2012.6398362</a>.","ieee":"T. Xie, W. Müller, and F. Letombe, “Mutation-Analysis Driven Functional Verification of a Soft Microprocessor,” 2012, doi: <a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">10.1109/SOCC.2012.6398362</a>.","short":"T. Xie, W. Müller, F. Letombe, in: Proceedings of SOCC2012, IEEE,  Niagara Falls, NY, USA , 2012.","chicago":"Xie, Tao , Wolfgang Müller, and Florian Letombe. “Mutation-Analysis Driven Functional Verification of a Soft Microprocessor.” In <i>Proceedings of SOCC2012</i>.  Niagara Falls, NY, USA : IEEE, 2012. <a href=\"https://doi.org/10.1109/SOCC.2012.6398362\">https://doi.org/10.1109/SOCC.2012.6398362</a>."},"department":[{"_id":"672"}],"author":[{"full_name":"Xie, Tao ","first_name":"Tao ","last_name":"Xie"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","last_name":"Müller","id":"16243"},{"full_name":"Letombe, Florian","first_name":"Florian","last_name":"Letombe"}],"title":"Mutation-Analysis Driven Functional Verification of a Soft Microprocessor","abstract":[{"lang":"eng","text":"This paper proposes a quality driven, simulation based approach to functional design verification, which applies mainly to IP-level HDL designs with well specified test instruction format and is evaluated on a soft microprocessor core MB-LITE [5]. The approach utilizes mutation analysis as the quality metric to steer an automated simulation data generation process. It leads to a simulation flow with two phases towards an enhanced mutation analysis result. First in a random simulation phase, an in-loop heuristics is deployed and adjusts dynamically the test probability distribution so as to improve the coverage efficiency. Next, for each remaining hard-to-kill mutant, a search heuristics on test input space is developed to iteratively locate a target test, using a specific objective cost function for the goal of killing HDL mutant. The effectiveness of this integrated two-phase simulation flow is demonstrated by the results with the MB-LITE microprocessor IP."}],"doi":"10.1109/SOCC.2012.6398362","place":" Niagara Falls, NY, USA "},{"author":[{"last_name":"Xie","full_name":"Xie, Tao","first_name":"Tao"},{"full_name":"Müller, Wolfgang","first_name":"Wolfgang","last_name":"Müller","id":"16243"}],"title":"An IP-XACT-TO-SystemC Model Generator for Mutation Analysis","place":"Tampere, Finnland","user_id":"5786","citation":{"mla":"Xie, Tao, and Wolfgang Müller. “An IP-XACT-TO-SystemC Model Generator for Mutation Analysis.” <i>Proceedings of the MeCoES’12</i>, 2012.","apa":"Xie, T., &#38; Müller, W. (2012). An IP-XACT-TO-SystemC Model Generator for Mutation Analysis. <i>Proceedings of the MeCoES’12</i>.","ama":"Xie T, Müller W. An IP-XACT-TO-SystemC Model Generator for Mutation Analysis. In: <i>Proceedings of the MeCoES’12</i>. ; 2012.","bibtex":"@inproceedings{Xie_Müller_2012, place={Tampere, Finnland}, title={An IP-XACT-TO-SystemC Model Generator for Mutation Analysis}, booktitle={Proceedings of the MeCoES’12}, author={Xie, Tao and Müller, Wolfgang}, year={2012} }","short":"T. Xie, W. Müller, in: Proceedings of the MeCoES’12, Tampere, Finnland, 2012.","chicago":"Xie, Tao, and Wolfgang Müller. “An IP-XACT-TO-SystemC Model Generator for Mutation Analysis.” In <i>Proceedings of the MeCoES’12</i>. Tampere, Finnland, 2012.","ieee":"T. Xie and W. Müller, “An IP-XACT-TO-SystemC Model Generator for Mutation Analysis,” 2012."},"department":[{"_id":"672"}],"date_created":"2023-01-17T08:52:59Z","publication":"Proceedings of the MeCoES’12","status":"public","language":[{"iso":"eng"}],"year":"2012","type":"conference","_id":"36997","date_updated":"2023-01-17T08:53:54Z"},{"user_id":"21240","citation":{"short":"C. Kuznik, W. Müller, in: Proc. of the 8th International SoC Design Conference 2011 (ISOCC 2011), 2011.","mla":"Kuznik, Christoph, and Wolfgang Müller. “Aspect Enhanced Functional Coverage Driven Verification in the SystemC HDVL.” <i>Proc. of the 8th International SoC Design Conference 2011 (ISOCC 2011)</i>, 2011.","bibtex":"@inproceedings{Kuznik_Müller_2011, title={Aspect enhanced functional coverage driven verification in the SystemC HDVL}, booktitle={Proc. of the 8th International SoC Design Conference 2011 (ISOCC 2011)}, author={Kuznik, Christoph and Müller, Wolfgang}, year={2011} }","chicago":"Kuznik, Christoph, and Wolfgang Müller. “Aspect Enhanced Functional Coverage Driven Verification in the SystemC HDVL.” In <i>Proc. of the 8th International SoC Design Conference 2011 (ISOCC 2011)</i>, 2011.","ieee":"C. Kuznik and W. Müller, “Aspect enhanced functional coverage driven verification in the SystemC HDVL,” 2011.","apa":"Kuznik, C., &#38; Müller, W. (2011). Aspect enhanced functional coverage driven verification in the SystemC HDVL. <i>Proc. of the 8th International SoC Design Conference 2011 (ISOCC 2011)</i>.","ama":"Kuznik C, Müller W. Aspect enhanced functional coverage driven verification in the SystemC HDVL. In: <i>Proc. of the 8th International SoC Design Conference 2011 (ISOCC 2011)</i>. ; 2011."},"department":[{"_id":"672"}],"author":[{"last_name":"Kuznik","full_name":"Kuznik, Christoph","first_name":"Christoph"},{"full_name":"Müller, Wolfgang","first_name":"Wolfgang","id":"16243","last_name":"Müller"}],"title":"Aspect enhanced functional coverage driven verification in the SystemC HDVL","_id":"26667","date_updated":"2022-01-06T06:57:25Z","publication":"Proc. of the 8th International SoC Design Conference 2011 (ISOCC 2011)","date_created":"2021-10-21T10:59:51Z","status":"public","type":"conference","year":"2011","language":[{"iso":"eng"}]}]