---
_id: '37009'
abstract:
- lang: eng
  text: Today, mobile and embedded real time systems have to cope with the migration
    and allocation of multiple software tasks running on top of a real time operating
    system (RTOS) residing on one or several processors. For scaling of each task
    set and processor configuration, instruction set simulation and worst case timing
    analysis are typically applied. This paper presents a complementary approach for
    the verification of RTOS properties based on an abstract RTOS-Model in SystemC.
    We apply IEEE P1850 PSL for which we present an approach and first experiences
    for the assertion-based verification of RTOS properties.
author:
- first_name: Marcio F. S.
  full_name: Oliveira, Marcio F. S.
  last_name: Oliveira
- first_name: Henning
  full_name: Zabel, Henning
  last_name: Zabel
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Oliveira MFS, Zabel H, Müller W. Assertion-Based Verification of RTOS Properties.
    In: <i>Proceedings of DATE’10</i>. IEEE; 2010. doi:<a href="https://doi.org/10.1109/DATE.2010.5457130">10.1109/DATE.2010.5457130</a>'
  apa: Oliveira, M. F. S., Zabel, H., &#38; Müller, W. (2010). Assertion-Based Verification
    of RTOS Properties. <i>Proceedings of DATE’10</i>. 2010 Design, Automation &#38;
    Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden. <a href="https://doi.org/10.1109/DATE.2010.5457130">https://doi.org/10.1109/DATE.2010.5457130</a>
  bibtex: '@inproceedings{Oliveira_Zabel_Müller_2010, place={Dresden}, title={Assertion-Based
    Verification of RTOS Properties}, DOI={<a href="https://doi.org/10.1109/DATE.2010.5457130">10.1109/DATE.2010.5457130</a>},
    booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Oliveira, Marcio
    F. S. and Zabel, Henning and Müller, Wolfgang}, year={2010} }'
  chicago: 'Oliveira, Marcio F. S., Henning Zabel, and Wolfgang Müller. “Assertion-Based
    Verification of RTOS Properties.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE,
    2010. <a href="https://doi.org/10.1109/DATE.2010.5457130">https://doi.org/10.1109/DATE.2010.5457130</a>.'
  ieee: 'M. F. S. Oliveira, H. Zabel, and W. Müller, “Assertion-Based Verification
    of RTOS Properties,” presented at the 2010 Design, Automation &#38; Test in Europe
    Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi: <a href="https://doi.org/10.1109/DATE.2010.5457130">10.1109/DATE.2010.5457130</a>.'
  mla: Oliveira, Marcio F. S., et al. “Assertion-Based Verification of RTOS Properties.”
    <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href="https://doi.org/10.1109/DATE.2010.5457130">10.1109/DATE.2010.5457130</a>.
  short: 'M.F.S. Oliveira, H. Zabel, W. Müller, in: Proceedings of DATE’10, IEEE,
    Dresden, 2010.'
conference:
  location: Dresden
  name: 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
date_created: 2023-01-17T09:15:10Z
date_updated: 2023-01-17T09:15:18Z
department:
- _id: '672'
doi: 10.1109/DATE.2010.5457130
keyword:
- Operating systems
- Real time systems
- Timing
- Hardware
- Analytical models
- Embedded software
- Software systems
- Processor scheduling
- Software performance
- Performance analysis
language:
- iso: eng
place: Dresden
publication: Proceedings of DATE’10
publisher: IEEE
status: public
title: Assertion-Based Verification of RTOS Properties
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37011'
abstract:
- lang: eng
  text: Safety-critical automotive systems must fulfill hard real-time constraints
    for reliability and safety. This paper presents a case study for the application
    of an AUTOSAR-based language for timing modeling and analysis. We present and
    apply the Timing Augmented Description Language (TADL) and demonstrate a methodology
    for the development of a speed-adaptive steer-by-wire system. We examine the impact
    of TADL and the methodology on the development process and the suitability and
    interoperability of the applied tools with respect to the AUTOSAR-based tool chain
    in the context of our case study.
author:
- first_name: Kay
  full_name: Klobedanz, Kay
  last_name: Klobedanz
- first_name: Christoph
  full_name: Kuznik, Christoph
  last_name: Kuznik
- first_name: Andre
  full_name: Thuy, Andre
  last_name: Thuy
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Klobedanz K, Kuznik C, Thuy A, Müller W. Timing Modeling and Analysis for
    AUTOSAR-Based Software Development - A Case Study. In: <i>Proceedings of DATE’10,
    Dresden</i>. IEEE; 2010. doi:<a href="https://doi.org/10.1109/DATE.2010.5457125">10.1109/DATE.2010.5457125</a>'
  apa: Klobedanz, K., Kuznik, C., Thuy, A., &#38; Müller, W. (2010). Timing Modeling
    and Analysis for AUTOSAR-Based Software Development - A Case Study. <i>Proceedings
    of DATE’10, Dresden</i>. 2010 Design, Automation &#38; Test in Europe Conference
    &#38; Exhibition (DATE 2010), Dresden. <a href="https://doi.org/10.1109/DATE.2010.5457125">https://doi.org/10.1109/DATE.2010.5457125</a>
  bibtex: '@inproceedings{Klobedanz_Kuznik_Thuy_Müller_2010, place={Dresden}, title={Timing
    Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study},
    DOI={<a href="https://doi.org/10.1109/DATE.2010.5457125">10.1109/DATE.2010.5457125</a>},
    booktitle={Proceedings of DATE’10, Dresden}, publisher={IEEE}, author={Klobedanz,
    Kay and Kuznik, Christoph and Thuy, Andre and Müller, Wolfgang}, year={2010} }'
  chicago: 'Klobedanz, Kay, Christoph Kuznik, Andre Thuy, and Wolfgang Müller. “Timing
    Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study.”
    In <i>Proceedings of DATE’10, Dresden</i>. Dresden: IEEE, 2010. <a href="https://doi.org/10.1109/DATE.2010.5457125">https://doi.org/10.1109/DATE.2010.5457125</a>.'
  ieee: 'K. Klobedanz, C. Kuznik, A. Thuy, and W. Müller, “Timing Modeling and Analysis
    for AUTOSAR-Based Software Development - A Case Study,” presented at the 2010
    Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010),
    Dresden, 2010, doi: <a href="https://doi.org/10.1109/DATE.2010.5457125">10.1109/DATE.2010.5457125</a>.'
  mla: Klobedanz, Kay, et al. “Timing Modeling and Analysis for AUTOSAR-Based Software
    Development - A Case Study.” <i>Proceedings of DATE’10, Dresden</i>, IEEE, 2010,
    doi:<a href="https://doi.org/10.1109/DATE.2010.5457125">10.1109/DATE.2010.5457125</a>.
  short: 'K. Klobedanz, C. Kuznik, A. Thuy, W. Müller, in: Proceedings of DATE’10,
    Dresden, IEEE, Dresden, 2010.'
conference:
  location: Dresden
  name: 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
date_created: 2023-01-17T09:19:36Z
date_updated: 2023-01-17T09:19:46Z
department:
- _id: '672'
doi: 10.1109/DATE.2010.5457125
keyword:
- Timing
- Programming
- Automotive engineering
- Application software
- Hardware
- Computer architecture
- Communication system software
- Software architecture
- Delay
- Software standards
language:
- iso: eng
place: Dresden
publication: Proceedings of DATE’10, Dresden
publisher: IEEE
status: public
title: Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case
  Study
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37037'
abstract:
- lang: eng
  text: Today we can identify a big gap between requirement specification and the
    generation of test environments. This article extends the Classification Tree
    Method for Embedded Systems (CTM/ES) to fill this gap by new concepts for the
    precise specification of stimuli for operational ranges of continuous control
    systems. It introduces novel means for continuous acceptance criteria definition
    and for functional coverage definition.
author:
- first_name: Alexander
  full_name: Krupp, Alexander
  last_name: Krupp
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Krupp A, Müller W. A Systematic Approach to Combined HW/SW System Test. In:
    <i>Proceedings of DATE’10</i>. IEEE; 2010. doi:<a href="https://doi.org/10.1109/DATE.2010.5457186">10.1109/DATE.2010.5457186</a>'
  apa: Krupp, A., &#38; Müller, W. (2010). A Systematic Approach to Combined HW/SW
    System Test. <i>Proceedings of DATE’10</i>. Design, Automation &#38; Test in Europe
    Conference &#38; Exhibition (DATE 2010), Dresden. <a href="https://doi.org/10.1109/DATE.2010.5457186">https://doi.org/10.1109/DATE.2010.5457186</a>
  bibtex: '@inproceedings{Krupp_Müller_2010, place={Dresden}, title={A Systematic
    Approach to Combined HW/SW System Test}, DOI={<a href="https://doi.org/10.1109/DATE.2010.5457186">10.1109/DATE.2010.5457186</a>},
    booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Krupp, Alexander
    and Müller, Wolfgang}, year={2010} }'
  chicago: 'Krupp, Alexander, and Wolfgang Müller. “A Systematic Approach to Combined
    HW/SW System Test.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a
    href="https://doi.org/10.1109/DATE.2010.5457186">https://doi.org/10.1109/DATE.2010.5457186</a>.'
  ieee: 'A. Krupp and W. Müller, “A Systematic Approach to Combined HW/SW System Test,”
    presented at the Design, Automation &#38; Test in Europe Conference &#38; Exhibition
    (DATE 2010), Dresden, 2010, doi: <a href="https://doi.org/10.1109/DATE.2010.5457186">10.1109/DATE.2010.5457186</a>.'
  mla: Krupp, Alexander, and Wolfgang Müller. “A Systematic Approach to Combined HW/SW
    System Test.” <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href="https://doi.org/10.1109/DATE.2010.5457186">10.1109/DATE.2010.5457186</a>.
  short: 'A. Krupp, W. Müller, in: Proceedings of DATE’10, IEEE, Dresden, 2010.'
conference:
  location: Dresden
  name: Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
date_created: 2023-01-17T10:41:15Z
date_updated: 2023-01-17T10:41:25Z
department:
- _id: '672'
doi: 10.1109/DATE.2010.5457186
keyword:
- System testing
- Automatic testing
- Object oriented modeling
- Classification tree analysis
- Automotive engineering
- Mathematical model
- Embedded system
- Control systems
- Electronic equipment testing
- Software testing
language:
- iso: eng
place: Dresden
publication: Proceedings of DATE’10
publisher: IEEE
status: public
title: A Systematic Approach to Combined HW/SW System Test
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37040'
abstract:
- lang: eng
  text: Refinement of untimed TLM models into a timed HW/SW platform is a step by
    step design process which is a trade-off between timing accuracy of the used models
    and correct estimation of the final timing performance. The use of an RTOS on
    the target platform is mandatory in the case real-time properties must be guaranteed.
    Thus, the question is when the RTOS must be introduced in this step by step refinement
    process. This paper proposes a four-level RTOS-aware refinement methodology that,
    starting from an untimed TLM SystemC description of the whole system, progressively
    introduce HW/SW partitioning, timing, device driver and RTOS functionalities,
    till to obtain an accurate model of the final platform, where SW tasks run upon
    an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions.
    Each refinement level allows the designer to estimate more and more accurate timing
    properties, thus anticipating design decisions without being constrained to leave
    timing analysis to the final step of the refinement. The effectiveness of the
    methodology has been evaluated in the design of two complex platforms.
author:
- first_name: Markus
  full_name: Becker, Markus
  last_name: Becker
- first_name: Giuseppe
  full_name: Di Guglielmo, Giuseppe
  last_name: Di Guglielmo
- first_name: Franco
  full_name: Fummi, Franco
  last_name: Fummi
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Graziano
  full_name: Pravadelli, Graziano
  last_name: Pravadelli
- first_name: Tao
  full_name: Xie, Tao
  last_name: Xie
citation:
  ama: 'Becker M, Di Guglielmo G, Fummi F, Müller W, Pravadelli G, Xie T. RTOS-Aware
    Refinement for TLM2.0-based HW/SW Design. In: <i>Proceedings of DATE’10</i>. IEEE;
    2010. doi:<a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>'
  apa: Becker, M., Di Guglielmo, G., Fummi, F., Müller, W., Pravadelli, G., &#38;
    Xie, T. (2010). RTOS-Aware Refinement for TLM2.0-based HW/SW Design. <i>Proceedings
    of DATE’10</i>. Design, Automation &#38; Test in Europe Conference &#38; Exhibition
    (DATE 2010), Dresden. <a href="https://doi.org/10.1109/DATE.2010.5456965">https://doi.org/10.1109/DATE.2010.5456965</a>
  bibtex: '@inproceedings{Becker_Di Guglielmo_Fummi_Müller_Pravadelli_Xie_2010, place={Dresden},
    title={RTOS-Aware Refinement for TLM2.0-based HW/SW Design}, DOI={<a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>},
    booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Becker, Markus and
    Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli,
    Graziano and Xie, Tao}, year={2010} }'
  chicago: 'Becker, Markus, Giuseppe Di Guglielmo, Franco Fummi, Wolfgang Müller,
    Graziano Pravadelli, and Tao Xie. “RTOS-Aware Refinement for TLM2.0-Based HW/SW
    Design.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href="https://doi.org/10.1109/DATE.2010.5456965">https://doi.org/10.1109/DATE.2010.5456965</a>.'
  ieee: 'M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, and T. Xie,
    “RTOS-Aware Refinement for TLM2.0-based HW/SW Design,” presented at the Design,
    Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden,
    2010, doi: <a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>.'
  mla: Becker, Markus, et al. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.”
    <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>.
  short: 'M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, T. Xie,
    in: Proceedings of DATE’10, IEEE, Dresden, 2010.'
conference:
  location: Dresden
  name: Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
date_created: 2023-01-17T10:47:29Z
date_updated: 2023-01-17T10:47:37Z
department:
- _id: '672'
doi: 10.1109/DATE.2010.5456965
keyword:
- Timing
- Hardware
- Operating systems
- Process design
- Accuracy
- Standards development
- Context modeling
- Real time systems
- Communication channels
- Microprogramming
language:
- iso: eng
place: Dresden
publication: Proceedings of DATE’10
publication_identifier:
  eisbn:
  - 978-3-9810801-6-2
publisher: IEEE
status: public
title: RTOS-Aware Refinement for TLM2.0-based HW/SW Design
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37046'
abstract:
- lang: eng
  text: In this article, we present a flexible simulation environment for embedded
    real-time software refinement by a mixed level cosimulation. For this, we combine
    the native speed of an abstract real-time operating system (RTOS) model in SystemC
    with dynamic binary translation for fast Instruction Set Simulation (ISS) by QEMU.
    In order to support stepwise RTOS software refinement from system level to the
    target software, each task can be separately migrated between the native execution
    and the ISS. By adapting the dynamic binary translation approach to an efficient
    but yet very accurate synchronization scheme the overhead of QEMU user mode execution
    is only factor two compared to native SystemC. Furthermore, the simulation speed
    increases almost linearly according to the utilization of the task set abstracted
    by the native execution. Hereby, the simulation time can be considerably reduced
    by cosimulating just a subset of tasks on QEMU.
author:
- first_name: Markus
  full_name: Becker, Markus
  last_name: Becker
- first_name: Henning
  full_name: Zabel, Henning
  last_name: Zabel
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Becker M, Zabel H, Müller W. A Mixed Level Simulation Environment for Stepwise
    RTOS Software Refinement. In: Kleinjohann L, Kleinjohann B, eds. Springer Verlag;
    2010. doi:<a href="https://doi.org/10.1007/978-3-642-15234-4_15">10.1007/978-3-642-15234-4_15</a>'
  apa: Becker, M., Zabel, H., &#38; Müller, W. (2010). <i>A Mixed Level Simulation
    Environment for Stepwise RTOS Software Refinement</i> (L. Kleinjohann &#38; B.
    Kleinjohann, Eds.). Springer Verlag. <a href="https://doi.org/10.1007/978-3-642-15234-4_15">https://doi.org/10.1007/978-3-642-15234-4_15</a>
  bibtex: '@inproceedings{Becker_Zabel_Müller_2010, place={Dordrecht}, title={A Mixed
    Level Simulation Environment for Stepwise RTOS Software Refinement}, DOI={<a href="https://doi.org/10.1007/978-3-642-15234-4_15">10.1007/978-3-642-15234-4_15</a>},
    publisher={Springer Verlag}, author={Becker, Markus and Zabel, Henning and Müller,
    Wolfgang}, editor={Kleinjohann, L. and Kleinjohann, B.}, year={2010} }'
  chicago: 'Becker, Markus, Henning Zabel, and Wolfgang Müller. “A Mixed Level Simulation
    Environment for Stepwise RTOS Software Refinement.” edited by L. Kleinjohann and
    B. Kleinjohann. Dordrecht: Springer Verlag, 2010. <a href="https://doi.org/10.1007/978-3-642-15234-4_15">https://doi.org/10.1007/978-3-642-15234-4_15</a>.'
  ieee: 'M. Becker, H. Zabel, and W. Müller, “A Mixed Level Simulation Environment
    for Stepwise RTOS Software Refinement,” 2010, doi: <a href="https://doi.org/10.1007/978-3-642-15234-4_15">10.1007/978-3-642-15234-4_15</a>.'
  mla: Becker, Markus, et al. <i>A Mixed Level Simulation Environment for Stepwise
    RTOS Software Refinement</i>. Edited by L. Kleinjohann and B. Kleinjohann, Springer
    Verlag, 2010, doi:<a href="https://doi.org/10.1007/978-3-642-15234-4_15">10.1007/978-3-642-15234-4_15</a>.
  short: 'M. Becker, H. Zabel, W. Müller, in: L. Kleinjohann, B. Kleinjohann (Eds.),
    Springer Verlag, Dordrecht, 2010.'
conference:
  name: IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES
    2010)
date_created: 2023-01-17T11:01:30Z
date_updated: 2023-01-17T11:03:00Z
department:
- _id: '672'
doi: 10.1007/978-3-642-15234-4_15
editor:
- first_name: L.
  full_name: Kleinjohann, L.
  last_name: Kleinjohann
- first_name: B.
  full_name: Kleinjohann, B.
  last_name: Kleinjohann
keyword:
- Application Programming Interface     User Mode     Kernel Space     System Level
  Design     Mixed Level
language:
- iso: eng
place: Dordrecht
publication_identifier:
  isbn:
  - 978-3-642-15233-7
publisher: Springer Verlag
status: public
title: A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37044'
abstract:
- lang: eng
  text: In this paper we present new concepts to resolve ECU (Electronic Control Unit)
    failures in FlexRay networks. Our approach extends the FlexRay bus schedule by
    redundant slots with modifications in the communication and slot assignment. We
    introduce additional backup nodes to replace faulty nodes. To reduce the required
    memory resources of the backup nodes, we distribute redundant tasks over different
    nodes and propose the migration of tasks to the backup node at runtime. We investigate
    different solutions to migrate the redundant tasks to the backup node by time-triggered
    and event-triggered transmissions.
author:
- first_name: Kay
  full_name: Klobedanz, Kay
  last_name: Klobedanz
- first_name: Gilles B.
  full_name: Defo, Gilles B.
  last_name: Defo
- first_name: Henning
  full_name: Zabel, Henning
  last_name: Zabel
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Yuan
  full_name: Zhi, Yuan
  last_name: Zhi
citation:
  ama: 'Klobedanz K, Defo GB, Zabel H, Müller W, Zhi Y. Task Migration for Fault-Tolerant
    FlexRay Networks. In: Kleinjohann L, Kleinjohann B, eds. Springer Verlag; 2010.
    doi:<a href="https://doi.org/10.1007/978-3-642-15234-4_7">10.1007/978-3-642-15234-4_7</a>'
  apa: Klobedanz, K., Defo, G. B., Zabel, H., Müller, W., &#38; Zhi, Y. (2010). <i>Task
    Migration for Fault-Tolerant FlexRay Networks</i> (L. Kleinjohann &#38; B. Kleinjohann,
    Eds.). Springer Verlag. <a href="https://doi.org/10.1007/978-3-642-15234-4_7">https://doi.org/10.1007/978-3-642-15234-4_7</a>
  bibtex: '@inproceedings{Klobedanz_Defo_Zabel_Müller_Zhi_2010, place={Dordrecht},
    title={Task Migration for Fault-Tolerant FlexRay Networks}, DOI={<a href="https://doi.org/10.1007/978-3-642-15234-4_7">10.1007/978-3-642-15234-4_7</a>},
    publisher={Springer Verlag}, author={Klobedanz, Kay and Defo, Gilles B. and Zabel,
    Henning and Müller, Wolfgang and Zhi, Yuan}, editor={Kleinjohann, L. and Kleinjohann,
    B.}, year={2010} }'
  chicago: 'Klobedanz, Kay, Gilles B. Defo, Henning Zabel, Wolfgang Müller, and Yuan
    Zhi. “Task Migration for Fault-Tolerant FlexRay Networks.” edited by L. Kleinjohann
    and B. Kleinjohann. Dordrecht: Springer Verlag, 2010. <a href="https://doi.org/10.1007/978-3-642-15234-4_7">https://doi.org/10.1007/978-3-642-15234-4_7</a>.'
  ieee: 'K. Klobedanz, G. B. Defo, H. Zabel, W. Müller, and Y. Zhi, “Task Migration
    for Fault-Tolerant FlexRay Networks,” 2010, doi: <a href="https://doi.org/10.1007/978-3-642-15234-4_7">10.1007/978-3-642-15234-4_7</a>.'
  mla: Klobedanz, Kay, et al. <i>Task Migration for Fault-Tolerant FlexRay Networks</i>.
    Edited by L. Kleinjohann and B. Kleinjohann, Springer Verlag, 2010, doi:<a href="https://doi.org/10.1007/978-3-642-15234-4_7">10.1007/978-3-642-15234-4_7</a>.
  short: 'K. Klobedanz, G.B. Defo, H. Zabel, W. Müller, Y. Zhi, in: L. Kleinjohann,
    B. Kleinjohann (Eds.), Springer Verlag, Dordrecht, 2010.'
conference:
  name: IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES
    2010)
date_created: 2023-01-17T10:59:52Z
date_updated: 2023-01-17T11:00:00Z
department:
- _id: '672'
doi: 10.1007/978-3-642-15234-4_7
editor:
- first_name: L.
  full_name: Kleinjohann, L.
  last_name: Kleinjohann
- first_name: B.
  full_name: Kleinjohann, B.
  last_name: Kleinjohann
keyword:
- Faulty Node     Static Segment     Slot Assignment     Task Migration     Communication
  Controller
language:
- iso: eng
place: Dordrecht
publication_identifier:
  isbn:
  - 978-3-642-15233-7
publisher: Springer Verlag
status: public
title: Task Migration for Fault-Tolerant FlexRay Networks
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37042'
abstract:
- lang: eng
  text: It's wide application in the area of software engineering, UML is still not
    fully accepted for other engineering domains like for electronic systems design.
    The main obstacle is due to a major gap in the design flow between UML-based modeling
    and verification. To overcome this gap, we introduce a UML profile for synthesizable
    SystemC and C and present its implementation in the context of the advanced SysML
    modeling environment of ARTiSAN Studio. We demonstrate how to customize Studio
    for SystemC/C comodeling so that it can serve as a verification and synthesis
    front-end.
author:
- first_name: Fabian
  full_name: Mischkalla, Fabian
  last_name: Mischkalla
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Da
  full_name: He, Da
  last_name: He
citation:
  ama: 'Mischkalla F, Müller W, He D. A UML Profile for SysML-Based Comodeling for
    Embedded Systems Simulation and Synthesis. In: <i>Proceedings of the M-BED Workshop</i>.
    ; 2010.'
  apa: Mischkalla, F., Müller, W., &#38; He, D. (2010). A UML Profile for SysML-Based
    Comodeling for Embedded Systems Simulation and Synthesis. <i>Proceedings of the
    M-BED Workshop</i>.
  bibtex: '@inproceedings{Mischkalla_Müller_He_2010, place={Dresden}, title={A UML
    Profile for SysML-Based Comodeling for Embedded Systems Simulation and Synthesis},
    booktitle={Proceedings of the M-BED Workshop}, author={Mischkalla, Fabian and
    Müller, Wolfgang and He, Da}, year={2010} }'
  chicago: Mischkalla, Fabian, Wolfgang Müller, and Da He. “A UML Profile for SysML-Based
    Comodeling for Embedded Systems Simulation and Synthesis.” In <i>Proceedings of
    the M-BED Workshop</i>. Dresden, 2010.
  ieee: F. Mischkalla, W. Müller, and D. He, “A UML Profile for SysML-Based Comodeling
    for Embedded Systems Simulation and Synthesis,” 2010.
  mla: Mischkalla, Fabian, et al. “A UML Profile for SysML-Based Comodeling for Embedded
    Systems Simulation and Synthesis.” <i>Proceedings of the M-BED Workshop</i>, 2010.
  short: 'F. Mischkalla, W. Müller, D. He, in: Proceedings of the M-BED Workshop,
    Dresden, 2010.'
date_created: 2023-01-17T10:50:01Z
date_updated: 2023-01-17T10:50:10Z
department:
- _id: '672'
language:
- iso: eng
place: Dresden
publication: Proceedings of the M-BED Workshop
status: public
title: A UML Profile for SysML-Based Comodeling for Embedded Systems Simulation and
  Synthesis
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37043'
author:
- first_name: Alexander
  full_name: Bol, Alexander
  last_name: Bol
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Alexander
  full_name: Krupp, Alexander
  last_name: Krupp
citation:
  ama: 'Bol A, Müller W, Krupp A. Eine strukturierte Methode zur Generierung von SystemVerilog-Testumgebungen
    aus textuellen Anforderungsbeschreibungen. In: <i>Methoden Und Beschreibungssprachen
    Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV)</i>. ; 2010.'
  apa: Bol, A., Müller, W., &#38; Krupp, A. (2010). Eine strukturierte Methode zur
    Generierung von SystemVerilog-Testumgebungen aus textuellen Anforderungsbeschreibungen.
    <i>Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen
    Und Systemen (MBMV)</i>.
  bibtex: '@inproceedings{Bol_Müller_Krupp_2010, place={Dresden}, title={Eine strukturierte
    Methode zur Generierung von SystemVerilog-Testumgebungen aus textuellen Anforderungsbeschreibungen},
    booktitle={Methoden und Beschreibungssprachen zur Modellierung und Verifikation
    von Schaltungen und Systemen (MBMV)}, author={Bol, Alexander and Müller, Wolfgang
    and Krupp, Alexander}, year={2010} }'
  chicago: Bol, Alexander, Wolfgang Müller, and Alexander Krupp. “Eine Strukturierte
    Methode Zur Generierung von SystemVerilog-Testumgebungen Aus Textuellen Anforderungsbeschreibungen.”
    In <i>Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von
    Schaltungen Und Systemen (MBMV)</i>. Dresden, 2010.
  ieee: A. Bol, W. Müller, and A. Krupp, “Eine strukturierte Methode zur Generierung
    von SystemVerilog-Testumgebungen aus textuellen Anforderungsbeschreibungen,” 2010.
  mla: Bol, Alexander, et al. “Eine Strukturierte Methode Zur Generierung von SystemVerilog-Testumgebungen
    Aus Textuellen Anforderungsbeschreibungen.” <i>Methoden Und Beschreibungssprachen
    Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV)</i>, 2010.
  short: 'A. Bol, W. Müller, A. Krupp, in: Methoden Und Beschreibungssprachen Zur
    Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV), Dresden, 2010.'
date_created: 2023-01-17T10:55:18Z
date_updated: 2023-01-17T10:55:24Z
department:
- _id: '672'
language:
- iso: eng
place: Dresden
publication: Methoden und Beschreibungssprachen zur Modellierung und Verifikation
  von Schaltungen und Systemen (MBMV)
status: public
title: Eine strukturierte Methode zur Generierung von SystemVerilog-Testumgebungen
  aus textuellen Anforderungsbeschreibungen
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37050'
abstract:
- lang: eng
  text: The main obstacle for the wide acceptance of UML and SysML in the design of
    electronic systems is due to a major gap in the design flow between UML-based
    modeling and SystemC-based verification. To overcome this gap, we present an approach
    developed in the SATURN project which introduces UML profiles for the co-modeling
    of SystemC and C with code generation support in the context of the SysML tool
    suite ARTiSAN Studio®. We finally discuss the evaluation of the approach by two
    case studies.
author:
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Da
  full_name: He, Da
  last_name: He
- first_name: Fabian
  full_name: Mischkalla, Fabian
  last_name: Mischkalla
- first_name: Arthur
  full_name: Wegele, Arthur
  last_name: Wegele
- first_name: Adrian
  full_name: Larkham, Adrian
  last_name: Larkham
- first_name: Paul
  full_name: Whiston, Paul
  last_name: Whiston
- first_name: Pablo
  full_name: Penil, Pablo
  last_name: Penil
- first_name: Eugenio
  full_name: Villar, Eugenio
  last_name: Villar
- first_name: Nikolaos
  full_name: Mitas, Nikolaos
  last_name: Mitas
- first_name: Dimitros
  full_name: Kritharidis, Dimitros
  last_name: Kritharidis
- first_name: Florent
  full_name: Azcarate, Florent
  last_name: Azcarate
- first_name: Manuel
  full_name: Carballeda, Manuel
  last_name: Carballeda
citation:
  ama: 'Müller W, He D, Mischkalla F, et al. The SATURN Approach to SysML-based HW/SW
    Codesign. In: <i>Proceedings of the IEEE Computer Society Annual Symposium on
    VLSI</i>. Lecture Notes in Electrical Engineering. ; 2010. doi:<a href="https://doi.org/10.1007/978-94-007-1488-5_9">10.1007/978-94-007-1488-5_9</a>'
  apa: Müller, W., He, D., Mischkalla, F., Wegele, A., Larkham, A., Whiston, P., Penil,
    P., Villar, E., Mitas, N., Kritharidis, D., Azcarate, F., &#38; Carballeda, M.
    (2010). The SATURN Approach to SysML-based HW/SW Codesign. <i>Proceedings of the
    IEEE Computer Society Annual Symposium on VLSI</i>. <a href="https://doi.org/10.1007/978-94-007-1488-5_9">https://doi.org/10.1007/978-94-007-1488-5_9</a>
  bibtex: '@inproceedings{Müller_He_Mischkalla_Wegele_Larkham_Whiston_Penil_Villar_Mitas_Kritharidis_et
    al._2010, series={Lecture Notes in Electrical Engineering}, title={The SATURN
    Approach to SysML-based HW/SW Codesign}, DOI={<a href="https://doi.org/10.1007/978-94-007-1488-5_9">10.1007/978-94-007-1488-5_9</a>},
    booktitle={Proceedings of the IEEE Computer Society Annual Symposium on VLSI},
    author={Müller, Wolfgang and He, Da and Mischkalla, Fabian and Wegele, Arthur
    and Larkham, Adrian and Whiston, Paul and Penil, Pablo and Villar, Eugenio and
    Mitas, Nikolaos and Kritharidis, Dimitros and et al.}, year={2010}, collection={Lecture
    Notes in Electrical Engineering} }'
  chicago: Müller, Wolfgang, Da He, Fabian Mischkalla, Arthur Wegele, Adrian Larkham,
    Paul Whiston, Pablo Penil, et al. “The SATURN Approach to SysML-Based HW/SW Codesign.”
    In <i>Proceedings of the IEEE Computer Society Annual Symposium on VLSI</i>. Lecture
    Notes in Electrical Engineering, 2010. <a href="https://doi.org/10.1007/978-94-007-1488-5_9">https://doi.org/10.1007/978-94-007-1488-5_9</a>.
  ieee: 'W. Müller <i>et al.</i>, “The SATURN Approach to SysML-based HW/SW Codesign,”
    2010, doi: <a href="https://doi.org/10.1007/978-94-007-1488-5_9">10.1007/978-94-007-1488-5_9</a>.'
  mla: Müller, Wolfgang, et al. “The SATURN Approach to SysML-Based HW/SW Codesign.”
    <i>Proceedings of the IEEE Computer Society Annual Symposium on VLSI</i>, 2010,
    doi:<a href="https://doi.org/10.1007/978-94-007-1488-5_9">10.1007/978-94-007-1488-5_9</a>.
  short: 'W. Müller, D. He, F. Mischkalla, A. Wegele, A. Larkham, P. Whiston, P. Penil,
    E. Villar, N. Mitas, D. Kritharidis, F. Azcarate, M. Carballeda, in: Proceedings
    of the IEEE Computer Society Annual Symposium on VLSI, 2010.'
date_created: 2023-01-17T11:19:45Z
date_updated: 2023-01-17T11:19:53Z
department:
- _id: '672'
doi: 10.1007/978-94-007-1488-5_9
keyword:
- Communicate Sequential Process     Virtual Platform     Smart Camera     Synchronous
  Data Flow     Artisan Studio
language:
- iso: eng
publication: Proceedings of the IEEE Computer Society Annual Symposium on VLSI
publication_identifier:
  eisbn:
  - 978-94-007-1488-5
series_title: Lecture Notes in Electrical Engineering
status: public
title: The SATURN Approach to SysML-based HW/SW Codesign
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37048'
abstract:
- lang: eng
  text: We introduce a structured methodology for the generation of executable test
    environments from textual requirement specifications via UML class diagrams and
    the application of the classification tree methodology for embedded systems. The
    first phase is a stepwise transformation from unstructured English text into a
    textual normal form (TNF), which is automatically translated into UML class diagrams.
    After annotations of the class diagrams and the definition of test cases by sequence
    diagrams, both are converted into classification trees. From the classification
    trees we can finally generate SystemVerilog code. The methodology is introduced
    and evaluated by the example of an Adaptive Cruise Controller.
author:
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Alexander
  full_name: Bol, Alexander
  last_name: Bol
- first_name: Alexander
  full_name: Krupp, Alexander
  last_name: Krupp
- first_name: Ola
  full_name: Lundkvist, Ola
  last_name: Lundkvist
citation:
  ama: 'Müller W, Bol A, Krupp A, Lundkvist O. Generation of Executable Testbenches
    from Natural Language Requirement Specifications for Embedded Real-Time Systems.
    In: Kleinjohann L, Kleinjohann B, eds. Springer Verlag; 2010. doi:<a href="https://doi.org/10.1007/978-3-642-15234-4_9">10.1007/978-3-642-15234-4_9</a>'
  apa: Müller, W., Bol, A., Krupp, A., &#38; Lundkvist, O. (2010). <i>Generation of
    Executable Testbenches from Natural Language Requirement Specifications for Embedded
    Real-Time Systems</i> (L. Kleinjohann &#38; B. Kleinjohann, Eds.). Springer Verlag.
    <a href="https://doi.org/10.1007/978-3-642-15234-4_9">https://doi.org/10.1007/978-3-642-15234-4_9</a>
  bibtex: '@inproceedings{Müller_Bol_Krupp_Lundkvist_2010, place={Dordrecht}, title={Generation
    of Executable Testbenches from Natural Language Requirement Specifications for
    Embedded Real-Time Systems}, DOI={<a href="https://doi.org/10.1007/978-3-642-15234-4_9">10.1007/978-3-642-15234-4_9</a>},
    publisher={Springer Verlag}, author={Müller, Wolfgang and Bol, Alexander and Krupp,
    Alexander and Lundkvist, Ola}, editor={Kleinjohann, L. and Kleinjohann, B.}, year={2010}
    }'
  chicago: 'Müller, Wolfgang, Alexander Bol, Alexander Krupp, and Ola Lundkvist. “Generation
    of Executable Testbenches from Natural Language Requirement Specifications for
    Embedded Real-Time Systems.” edited by L. Kleinjohann and B. Kleinjohann. Dordrecht:
    Springer Verlag, 2010. <a href="https://doi.org/10.1007/978-3-642-15234-4_9">https://doi.org/10.1007/978-3-642-15234-4_9</a>.'
  ieee: 'W. Müller, A. Bol, A. Krupp, and O. Lundkvist, “Generation of Executable
    Testbenches from Natural Language Requirement Specifications for Embedded Real-Time
    Systems,” 2010, doi: <a href="https://doi.org/10.1007/978-3-642-15234-4_9">10.1007/978-3-642-15234-4_9</a>.'
  mla: Müller, Wolfgang, et al. <i>Generation of Executable Testbenches from Natural
    Language Requirement Specifications for Embedded Real-Time Systems</i>. Edited
    by L. Kleinjohann and B. Kleinjohann, Springer Verlag, 2010, doi:<a href="https://doi.org/10.1007/978-3-642-15234-4_9">10.1007/978-3-642-15234-4_9</a>.
  short: 'W. Müller, A. Bol, A. Krupp, O. Lundkvist, in: L. Kleinjohann, B. Kleinjohann
    (Eds.), Springer Verlag, Dordrecht, 2010.'
conference:
  name: IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES
    2010)
date_created: 2023-01-17T11:09:48Z
date_updated: 2023-01-17T11:09:54Z
department:
- _id: '672'
doi: 10.1007/978-3-642-15234-4_9
editor:
- first_name: L.
  full_name: Kleinjohann, L.
  last_name: Kleinjohann
- first_name: B.
  full_name: Kleinjohann, B.
  last_name: Kleinjohann
keyword:
- Natural Language     UML     SystemVerilog     Testbenches
language:
- iso: eng
place: Dordrecht
publication_identifier:
  isbn:
  - 978-3-642-15233-7
publisher: Springer Verlag
status: public
title: Generation of Executable Testbenches from Natural Language Requirement Specifications
  for Embedded Real-Time Systems
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37049'
author:
- first_name: Tao
  full_name: Xie, Tao
  last_name: Xie
- first_name: Florian
  full_name: Letombe, Florian
  last_name: Letombe
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Xie T, Letombe F, Müller W. Mutation-Analysis Directed Constrained Random
    Verification. In: Kleinjohann L, Kleinjohann B, eds. Springer Verlag; 2010.'
  apa: Xie, T., Letombe, F., &#38; Müller, W. (2010). <i>Mutation-Analysis Directed
    Constrained Random Verification</i> (L. Kleinjohann &#38; B. Kleinjohann, Eds.).
    Springer Verlag.
  bibtex: '@inproceedings{Xie_Letombe_Müller_2010, place={Dordrecht}, title={Mutation-Analysis
    Directed Constrained Random Verification}, publisher={Springer Verlag}, author={Xie,
    Tao and Letombe, Florian and Müller, Wolfgang}, editor={Kleinjohann, L. and Kleinjohann,
    B.}, year={2010} }'
  chicago: 'Xie, Tao, Florian Letombe, and Wolfgang Müller. “Mutation-Analysis Directed
    Constrained Random Verification.” edited by L. Kleinjohann and B. Kleinjohann.
    Dordrecht: Springer Verlag, 2010.'
  ieee: T. Xie, F. Letombe, and W. Müller, “Mutation-Analysis Directed Constrained
    Random Verification,” 2010.
  mla: Xie, Tao, et al. <i>Mutation-Analysis Directed Constrained Random Verification</i>.
    Edited by L. Kleinjohann and B. Kleinjohann, Springer Verlag, 2010.
  short: 'T. Xie, F. Letombe, W. Müller, in: L. Kleinjohann, B. Kleinjohann (Eds.),
    Springer Verlag, Dordrecht, 2010.'
conference:
  name: IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES
    2010)
date_created: 2023-01-17T11:11:51Z
date_updated: 2023-01-17T11:12:52Z
department:
- _id: '672'
editor:
- first_name: L.
  full_name: Kleinjohann, L.
  last_name: Kleinjohann
- first_name: B.
  full_name: Kleinjohann, B.
  last_name: Kleinjohann
language:
- iso: eng
place: Dordrecht
publisher: Springer Verlag
status: public
title: Mutation-Analysis Directed Constrained Random Verification
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37051'
author:
- first_name: Tao
  full_name: Xie, Tao
  last_name: Xie
- first_name: Gilles B.
  full_name: Defo, Gilles B.
  last_name: Defo
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Xie T, Defo GB, Müller W. An Eclipse-based Framework for the IP-XACT-enabled
    Assembly of Mixed-Level IPs. In: ; 2010.'
  apa: Xie, T., Defo, G. B., &#38; Müller, W. (2010). <i>An Eclipse-based Framework
    for the IP-XACT-enabled Assembly of Mixed-Level IPs</i>. First Workshop on Hands-on
    Platforms and tools for model-based engineering of Embedded Systems (HoPES 2010),
    Paris.
  bibtex: '@inproceedings{Xie_Defo_Müller_2010, place={Paris}, title={An Eclipse-based
    Framework for the IP-XACT-enabled Assembly of Mixed-Level IPs}, author={Xie, Tao
    and Defo, Gilles B. and Müller, Wolfgang}, year={2010} }'
  chicago: Xie, Tao, Gilles B. Defo, and Wolfgang Müller. “An Eclipse-Based Framework
    for the IP-XACT-Enabled Assembly of Mixed-Level IPs.” Paris, 2010.
  ieee: T. Xie, G. B. Defo, and W. Müller, “An Eclipse-based Framework for the IP-XACT-enabled
    Assembly of Mixed-Level IPs,” presented at the First Workshop on Hands-on Platforms
    and tools for model-based engineering of Embedded Systems (HoPES 2010), Paris,
    2010.
  mla: Xie, Tao, et al. <i>An Eclipse-Based Framework for the IP-XACT-Enabled Assembly
    of Mixed-Level IPs</i>. 2010.
  short: 'T. Xie, G.B. Defo, W. Müller, in: Paris, 2010.'
conference:
  location: Paris
  name: First Workshop on Hands-on Platforms and tools for model-based engineering
    of Embedded Systems (HoPES 2010)
date_created: 2023-01-17T11:22:10Z
date_updated: 2023-01-17T11:22:16Z
department:
- _id: '672'
language:
- iso: eng
place: Paris
status: public
title: An Eclipse-based Framework for the IP-XACT-enabled Assembly of Mixed-Level
  IPs
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37057'
abstract:
- lang: eng
  text: Many heterogeneous embedded systems, for example industrial automation and
    automotive applications, require hard-real time constraints to be exhaustively
    verified - which is a challenging task for the verification engineer. To cope
    with complexity, verification techniques working on different abstraction levels
    are best practice. SystemC is a versatile C++ based design and verification language,
    offering various mechanisms and constructs required for embedded systems modeling.
    Using the add-on SystemC Verification Library (SCV) elemental constrained-random
    stimuli techniques may be used for verification. However, SCV has several drawbacks
    such as lack of functional coverage. In this paper we present a functional coverage
    library that implements parts of the IEEE 1800-2005 SystemVerilog standard and
    allows capturing functional coverage throughout the design and verification process
    with SystemC. Moreover, we will demonstrate the usability of the approach with
    a case study working on a CAN bus model written in SystemC.
author:
- first_name: Gilles B.
  full_name: Defo, Gilles B.
  last_name: Defo
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Christoph
  full_name: Kuznik, Christoph
  last_name: Kuznik
citation:
  ama: 'Defo GB, Müller W, Kuznik C. Verification of a CAN Bus Model in SystemC with
    Functional Coverage. In: <i>Proceedings of SIES 2010</i>. IEEE; 2010. doi:<a href="https://doi.org/10.1109/SIES.2010.5551379">10.1109/SIES.2010.5551379</a>'
  apa: Defo, G. B., Müller, W., &#38; Kuznik, C. (2010). Verification of a CAN Bus
    Model in SystemC with Functional Coverage. <i>Proceedings of SIES 2010</i>. International
    Symposium on Industrial Embedded System (SIES),  Trento, Italy. <a href="https://doi.org/10.1109/SIES.2010.5551379">https://doi.org/10.1109/SIES.2010.5551379</a>
  bibtex: '@inproceedings{Defo_Müller_Kuznik_2010, place={ Trento, Italy}, title={Verification
    of a CAN Bus Model in SystemC with Functional Coverage}, DOI={<a href="https://doi.org/10.1109/SIES.2010.5551379">10.1109/SIES.2010.5551379</a>},
    booktitle={Proceedings of SIES 2010}, publisher={IEEE}, author={Defo, Gilles B.
    and Müller, Wolfgang and Kuznik, Christoph}, year={2010} }'
  chicago: 'Defo, Gilles B., Wolfgang Müller, and Christoph Kuznik. “Verification
    of a CAN Bus Model in SystemC with Functional Coverage.” In <i>Proceedings of
    SIES 2010</i>.  Trento, Italy: IEEE, 2010. <a href="https://doi.org/10.1109/SIES.2010.5551379">https://doi.org/10.1109/SIES.2010.5551379</a>.'
  ieee: 'G. B. Defo, W. Müller, and C. Kuznik, “Verification of a CAN Bus Model in
    SystemC with Functional Coverage,” presented at the International Symposium on
    Industrial Embedded System (SIES),  Trento, Italy, 2010, doi: <a href="https://doi.org/10.1109/SIES.2010.5551379">10.1109/SIES.2010.5551379</a>.'
  mla: Defo, Gilles B., et al. “Verification of a CAN Bus Model in SystemC with Functional
    Coverage.” <i>Proceedings of SIES 2010</i>, IEEE, 2010, doi:<a href="https://doi.org/10.1109/SIES.2010.5551379">10.1109/SIES.2010.5551379</a>.
  short: 'G.B. Defo, W. Müller, C. Kuznik, in: Proceedings of SIES 2010, IEEE,  Trento,
    Italy, 2010.'
conference:
  location: ' Trento, Italy'
  name: International Symposium on Industrial Embedded System (SIES)
date_created: 2023-01-17T11:34:56Z
date_updated: 2023-01-17T11:35:03Z
department:
- _id: '672'
doi: 10.1109/SIES.2010.5551379
keyword:
- Libraries
- Generators
- Transfer functions
- Monitoring
- Computational modeling
- Driver circuits
- Adaptation model
language:
- iso: eng
place: ' Trento, Italy'
publication: Proceedings of SIES 2010
publication_identifier:
  eisbn:
  - 978-1-4244-5841-7
publisher: IEEE
status: public
title: Verification of a CAN Bus Model in SystemC with Functional Coverage
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37056'
abstract:
- lang: eng
  text: In this paper we present an approach to increase the fault tolerance in FlexRay
    networks by introducing backup nodes to replace defect ECUs (Electronic Control
    Units). In order to reduce the memory requirements of such backup nodes, we distribute
    redundant tasks over different nodes and propose the distributed coordinated migration
    of tasks of the defect ECU to the backup node at runtime. This approach enhances
    our former work in, where we extended the FlexRay bus schedule by redundant slots
    to consider changes in the communication/slot assignment and investigated and
    evaluated different solutions to migrate the redundant tasks to the backup node
    using the static and/or dynamic segment of the communication cycle for transmissions.
    We present the approach of distributed coordination for migration and communication
    instead of additional dedicated coordinator nodes to further increase the fault
    tolerance. With this approach we improve the safety of FlexRay networks by avoiding
    a possible single point of failure due to a dedicated coordinator node also minimizing
    the necessary time needed for a reconfiguration after an ECU failure. Furthermore,
    we reduce the overhead within the communication and the demand for additional
    hardware components.
author:
- first_name: Kay
  full_name: Klobedanz, Kay
  last_name: Klobedanz
- first_name: Gilles B.
  full_name: Defo, Gilles B.
  last_name: Defo
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Timo
  full_name: Kerstan, Timo
  last_name: Kerstan
citation:
  ama: 'Klobedanz K, Defo GB, Müller W, Kerstan T. Distributed Coordination of Task
    Migration for Fault-Tolerant FlexRay Networks. In: <i>Proceedings of SIES 2010</i>.
    ; 2010. doi:<a href="https://doi.org/10.1109/SIES.2010.5551384">10.1109/SIES.2010.5551384</a>'
  apa: Klobedanz, K., Defo, G. B., Müller, W., &#38; Kerstan, T. (2010). Distributed
    Coordination of Task Migration for Fault-Tolerant FlexRay Networks. <i>Proceedings
    of SIES 2010</i>. International Symposium on Industrial Embedded System (SIES).
    <a href="https://doi.org/10.1109/SIES.2010.5551384">https://doi.org/10.1109/SIES.2010.5551384</a>
  bibtex: '@inproceedings{Klobedanz_Defo_Müller_Kerstan_2010, place={Trento, Italien},
    title={Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks},
    DOI={<a href="https://doi.org/10.1109/SIES.2010.5551384">10.1109/SIES.2010.5551384</a>},
    booktitle={Proceedings of SIES 2010}, author={Klobedanz, Kay and Defo, Gilles
    B. and Müller, Wolfgang and Kerstan, Timo}, year={2010} }'
  chicago: Klobedanz, Kay, Gilles B. Defo, Wolfgang Müller, and Timo Kerstan. “Distributed
    Coordination of Task Migration for Fault-Tolerant FlexRay Networks.” In <i>Proceedings
    of SIES 2010</i>. Trento, Italien, 2010. <a href="https://doi.org/10.1109/SIES.2010.5551384">https://doi.org/10.1109/SIES.2010.5551384</a>.
  ieee: 'K. Klobedanz, G. B. Defo, W. Müller, and T. Kerstan, “Distributed Coordination
    of Task Migration for Fault-Tolerant FlexRay Networks,” presented at the International
    Symposium on Industrial Embedded System (SIES), 2010, doi: <a href="https://doi.org/10.1109/SIES.2010.5551384">10.1109/SIES.2010.5551384</a>.'
  mla: Klobedanz, Kay, et al. “Distributed Coordination of Task Migration for Fault-Tolerant
    FlexRay Networks.” <i>Proceedings of SIES 2010</i>, 2010, doi:<a href="https://doi.org/10.1109/SIES.2010.5551384">10.1109/SIES.2010.5551384</a>.
  short: 'K. Klobedanz, G.B. Defo, W. Müller, T. Kerstan, in: Proceedings of SIES
    2010, Trento, Italien, 2010.'
conference:
  name: International Symposium on Industrial Embedded System (SIES)
date_created: 2023-01-17T11:31:38Z
date_updated: 2023-01-17T11:31:47Z
department:
- _id: '672'
doi: 10.1109/SIES.2010.5551384
keyword:
- Fault tolerant systems
- Protocols
- Redundancy
- Runtime
- Payloads
- Schedules
language:
- iso: eng
place: Trento, Italien
publication: Proceedings of SIES 2010
publication_identifier:
  eisbn:
  - 978-1-4244-5841-7
status: public
title: Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37053'
abstract:
- lang: eng
  text: Seamless HW/SW codesign flows support early verification of hardware and Hardware-dependent
    Software (HdS) like drivers, operating systems, and firmware. For early estimation
    and verification, the application of SystemC in combination with Instruction Set
    Simulators and Software Emulators like QEMU is widely accepted. In this article,
    we present an advanced design flow for HW, (RT)OS and HdS refinement and verification
    with focus on the transition from abstract RTOS verification to full system RTOS/HdS
    emulation. In the context of assertion-based verification, we introduce a set
    of generic real-time properties which can be reused and verified at different
    abstraction levels and discuss their application. The properties are presented
    by the means of IEEE standard PSL assertions which are applied for mixed SystemC/HdS
    models.
author:
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Marcio F.
  full_name: da S. Oliveira, Marcio F.
  last_name: da S. Oliveira
- first_name: Henning
  full_name: Zabel, Henning
  last_name: Zabel
- first_name: Markus
  full_name: Becker, Markus
  last_name: Becker
citation:
  ama: 'Müller W, da S. Oliveira MF, Zabel H, Becker M. Verification of Real-Time
    Properties for Hardware-Dependant Software. In: <i>Proceedings of HLDVT2010</i>.
    IEEE; 2010.'
  apa: Müller, W., da S. Oliveira, M. F., Zabel, H., &#38; Becker, M. (2010). Verification
    of Real-Time Properties for Hardware-Dependant Software. <i>Proceedings of HLDVT2010</i>.
    IEEE International High Level Design Validation and Test Workshop (HLDVT), Anaheim,
    FL, USA.
  bibtex: '@inproceedings{Müller_da S. Oliveira_Zabel_Becker_2010, title={Verification
    of Real-Time Properties for Hardware-Dependant Software}, booktitle={Proceedings
    of HLDVT2010}, publisher={IEEE}, author={Müller, Wolfgang and da S. Oliveira,
    Marcio F. and Zabel, Henning and Becker, Markus}, year={2010} }'
  chicago: Müller, Wolfgang, Marcio F. da S. Oliveira, Henning Zabel, and Markus Becker.
    “Verification of Real-Time Properties for Hardware-Dependant Software.” In <i>Proceedings
    of HLDVT2010</i>. IEEE, 2010.
  ieee: W. Müller, M. F. da S. Oliveira, H. Zabel, and M. Becker, “Verification of
    Real-Time Properties for Hardware-Dependant Software,” presented at the IEEE International
    High Level Design Validation and Test Workshop (HLDVT), Anaheim, FL, USA, 2010.
  mla: Müller, Wolfgang, et al. “Verification of Real-Time Properties for Hardware-Dependant
    Software.” <i>Proceedings of HLDVT2010</i>, IEEE, 2010.
  short: 'W. Müller, M.F. da S. Oliveira, H. Zabel, M. Becker, in: Proceedings of
    HLDVT2010, IEEE, 2010.'
conference:
  location: Anaheim, FL, USA
  name: IEEE International High Level Design Validation and Test Workshop (HLDVT)
date_created: 2023-01-17T11:28:26Z
date_updated: 2023-01-17T11:28:30Z
department:
- _id: '672'
keyword:
- Hardware
- Microprogramming
- Application software
- Timing
- Protocols
- Virtual prototyping
- Real time systems
- Sampling methods
- Operating systems
- Emulation
language:
- iso: eng
publication: Proceedings of HLDVT2010
publication_identifier:
  eisbn:
  - 978-1-4244-7806-4
publisher: IEEE
status: public
title: Verification of Real-Time Properties for Hardware-Dependant Software
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37060'
author:
- first_name: Marcio F. S.
  full_name: Oliveira, Marcio F. S.
  last_name: Oliveira
- first_name: Francisco Assis M.
  full_name: do Nascimento, Francisco Assis M.
  last_name: do Nascimento
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Oliveira MFS, do Nascimento FAM, Müller W. Design Space Abstraction and Metamodeling
    for Embedded Systems Design Space Exploration. In: <i>Proceedings of MoMPES 2010</i>.
    ; 2010.'
  apa: Oliveira, M. F. S., do Nascimento, F. A. M., &#38; Müller, W. (2010). Design
    Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration.
    <i>Proceedings of MoMPES 2010</i>.
  bibtex: '@inproceedings{Oliveira_do Nascimento_Müller_2010, place={Antwerp, Belgium},
    title={Design Space Abstraction and Metamodeling for Embedded Systems Design Space
    Exploration}, booktitle={Proceedings of MoMPES 2010}, author={Oliveira, Marcio
    F. S. and do Nascimento, Francisco Assis M. and Müller, Wolfgang}, year={2010}
    }'
  chicago: Oliveira, Marcio F. S., Francisco Assis M. do Nascimento, and Wolfgang
    Müller. “Design Space Abstraction and Metamodeling for Embedded Systems Design
    Space Exploration.” In <i>Proceedings of MoMPES 2010</i>. Antwerp, Belgium, 2010.
  ieee: M. F. S. Oliveira, F. A. M. do Nascimento, and W. Müller, “Design Space Abstraction
    and Metamodeling for Embedded Systems Design Space Exploration,” 2010.
  mla: Oliveira, Marcio F. S., et al. “Design Space Abstraction and Metamodeling for
    Embedded Systems Design Space Exploration.” <i>Proceedings of MoMPES 2010</i>,
    2010.
  short: 'M.F.S. Oliveira, F.A.M. do Nascimento, W. Müller, in: Proceedings of MoMPES
    2010, Antwerp, Belgium, 2010.'
date_created: 2023-01-17T11:37:39Z
date_updated: 2023-01-17T11:37:44Z
department:
- _id: '672'
language:
- iso: eng
place: Antwerp, Belgium
publication: Proceedings of MoMPES 2010
status: public
title: Design Space Abstraction and Metamodeling for Embedded Systems Design Space
  Exploration
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37039'
abstract:
- lang: eng
  text: Refinement of untimed TLM models into a timed HW/SW platform is a step by
    step design process which is a trade-off between timing accuracy of the used models
    and correct estimation of the final timing performance. The use of an RTOS on
    the target platform is mandatory in the case real-time properties must be guaranteed.
    Thus, the question is when the RTOS must be introduced in this step by step refinement
    process. This paper proposes a four-level RTOS-aware refinement methodology that,
    starting from an untimed TLM SystemC description of the whole system, progressively
    introduce HW/SW partitioning, timing, device driver and RTOS functionalities,
    till to obtain an accurate model of the final platform, where SW tasks run upon
    an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions.
    Each refinement level allows the designer to estimate more and more accurate timing
    properties, thus anticipating design decisions without being constrained to leave
    timing analysis to the final step of the refinement. The effectiveness of the
    methodology has been evaluated in the design of two complex platforms.
author:
- first_name: Markus
  full_name: Becker, Markus
  last_name: Becker
- first_name: Giuseppe
  full_name: Di Guglielmo, Giuseppe
  last_name: Di Guglielmo
- first_name: Franco
  full_name: Fummi, Franco
  last_name: Fummi
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Graziano
  full_name: Pravadelli, Graziano
  last_name: Pravadelli
- first_name: Tao
  full_name: Xie, Tao
  last_name: Xie
citation:
  ama: 'Becker M, Di Guglielmo G, Fummi F, Müller W, Pravadelli G, Xie T. RTOS-Aware
    Refinement for TLM2.0-based HW/SW Design. In: <i>Proceedings of DATE’10</i>. IEEE;
    2010. doi:<a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>'
  apa: Becker, M., Di Guglielmo, G., Fummi, F., Müller, W., Pravadelli, G., &#38;
    Xie, T. (2010). RTOS-Aware Refinement for TLM2.0-based HW/SW Design. <i>Proceedings
    of DATE’10</i>. Design, Automation &#38; Test in Europe Conference &#38; Exhibition
    (DATE 2010), Dresden. <a href="https://doi.org/10.1109/DATE.2010.5456965">https://doi.org/10.1109/DATE.2010.5456965</a>
  bibtex: '@inproceedings{Becker_Di Guglielmo_Fummi_Müller_Pravadelli_Xie_2010, place={Dresden},
    title={RTOS-Aware Refinement for TLM2.0-based HW/SW Design}, DOI={<a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>},
    booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Becker, Markus and
    Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli,
    Graziano and Xie, Tao}, year={2010} }'
  chicago: 'Becker, Markus, Giuseppe Di Guglielmo, Franco Fummi, Wolfgang Müller,
    Graziano Pravadelli, and Tao Xie. “RTOS-Aware Refinement for TLM2.0-Based HW/SW
    Design.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href="https://doi.org/10.1109/DATE.2010.5456965">https://doi.org/10.1109/DATE.2010.5456965</a>.'
  ieee: 'M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, and T. Xie,
    “RTOS-Aware Refinement for TLM2.0-based HW/SW Design,” presented at the Design,
    Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden,
    2010, doi: <a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>.'
  mla: Becker, Markus, et al. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.”
    <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>.
  short: 'M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, T. Xie,
    in: Proceedings of DATE’10, IEEE, Dresden, 2010.'
conference:
  location: Dresden
  name: Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
date_created: 2023-01-17T10:44:46Z
date_updated: 2025-03-12T16:39:17Z
doi: 10.1109/DATE.2010.5456965
keyword:
- Timing
- Hardware
- Operating systems
- Process design
- Accuracy
- Standards development
- Context modeling
- Real time systems
- Communication channels
- Microprogramming
language:
- iso: eng
place: Dresden
publication: Proceedings of DATE’10
publication_identifier:
  eisbn:
  - 978-3-9810801-6-2
publisher: IEEE
status: public
title: RTOS-Aware Refinement for TLM2.0-based HW/SW Design
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37047'
abstract:
- lang: eng
  text: We introduce a structured methodology for the generation of executable test
    environments from textual requirement specifications via UML class diagrams and
    the application of the classification tree methodology for embedded systems. The
    first phase is a stepwise transformation from unstructured English text into a
    textual normal form (TNF), which is automatically translated into UML class diagrams.
    After annotations of the class diagrams and the definition of test cases by sequence
    diagrams, both are converted into classification trees. From the classification
    trees we can finally generate SystemVerilog code. The methodology is introduced
    and evaluated by the example of an Adaptive Cruise Controller.
author:
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Alexander
  full_name: Bol, Alexander
  last_name: Bol
- first_name: Alexander
  full_name: Krupp, Alexander
  last_name: Krupp
- first_name: Ola
  full_name: Lundkvist, Ola
  last_name: Lundkvist
citation:
  ama: 'Müller W, Bol A, Krupp A, Lundkvist O. Generation of Executable Testbenches
    from Natural Language Requirement Specifications for Embedded Real-Time Systems.
    In: Kleinjohann L, Kleinjohann B, eds. Springer Verlag; 2010. doi:<a href="https://doi.org/10.1007/978-3-642-15234-4_9">10.1007/978-3-642-15234-4_9</a>'
  apa: Müller, W., Bol, A., Krupp, A., &#38; Lundkvist, O. (2010). <i>Generation of
    Executable Testbenches from Natural Language Requirement Specifications for Embedded
    Real-Time Systems</i> (L. Kleinjohann &#38; B. Kleinjohann, Eds.). Springer Verlag.
    <a href="https://doi.org/10.1007/978-3-642-15234-4_9">https://doi.org/10.1007/978-3-642-15234-4_9</a>
  bibtex: '@inproceedings{Müller_Bol_Krupp_Lundkvist_2010, place={Dordrecht}, title={Generation
    of Executable Testbenches from Natural Language Requirement Specifications for
    Embedded Real-Time Systems}, DOI={<a href="https://doi.org/10.1007/978-3-642-15234-4_9">10.1007/978-3-642-15234-4_9</a>},
    publisher={Springer Verlag}, author={Müller, Wolfgang and Bol, Alexander and Krupp,
    Alexander and Lundkvist, Ola}, editor={Kleinjohann, L. and Kleinjohann, B.}, year={2010}
    }'
  chicago: 'Müller, Wolfgang, Alexander Bol, Alexander Krupp, and Ola Lundkvist. “Generation
    of Executable Testbenches from Natural Language Requirement Specifications for
    Embedded Real-Time Systems.” edited by L. Kleinjohann and B. Kleinjohann. Dordrecht:
    Springer Verlag, 2010. <a href="https://doi.org/10.1007/978-3-642-15234-4_9">https://doi.org/10.1007/978-3-642-15234-4_9</a>.'
  ieee: 'W. Müller, A. Bol, A. Krupp, and O. Lundkvist, “Generation of Executable
    Testbenches from Natural Language Requirement Specifications for Embedded Real-Time
    Systems,” 2010, doi: <a href="https://doi.org/10.1007/978-3-642-15234-4_9">10.1007/978-3-642-15234-4_9</a>.'
  mla: Müller, Wolfgang, et al. <i>Generation of Executable Testbenches from Natural
    Language Requirement Specifications for Embedded Real-Time Systems</i>. Edited
    by L. Kleinjohann and B. Kleinjohann, Springer Verlag, 2010, doi:<a href="https://doi.org/10.1007/978-3-642-15234-4_9">10.1007/978-3-642-15234-4_9</a>.
  short: 'W. Müller, A. Bol, A. Krupp, O. Lundkvist, in: L. Kleinjohann, B. Kleinjohann
    (Eds.), Springer Verlag, Dordrecht, 2010.'
conference:
  name: IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES
    2010)
date_created: 2023-01-17T11:05:55Z
date_updated: 2025-03-12T16:39:13Z
doi: 10.1007/978-3-642-15234-4_9
editor:
- first_name: L.
  full_name: Kleinjohann, L.
  last_name: Kleinjohann
- first_name: B.
  full_name: Kleinjohann, B.
  last_name: Kleinjohann
keyword:
- Natural Language     UML     SystemVerilog     Testbenches
language:
- iso: eng
place: Dordrecht
publication_identifier:
  isbn:
  - 978-3-642-15233-7
publisher: Springer Verlag
status: public
title: Generation of Executable Testbenches from Natural Language Requirement Specifications
  for Embedded Real-Time Systems
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '33813'
abstract:
- lang: eng
  text: "Today, mobile and embedded real-time systems have to cope with the migration\r\nand
    allocation of multiple software tasks running on top of a real-time operating\r\nsystem
    (RTOS) residing on one or several system processors. Each RTOS has to\r\nbe configured
    towards the individual needs of the application and environment.\r\nFor this,
    different scheduling strategies and task priorities have to be evaluated in\r\norder
    to keep execution and response times for a given task set. Abstract RTOS\r\nsimulation
    is applied to analyze different parameters in early design phases. This\r\nchapter
    presents a SystemC RTOS library for abstract yet accurate RTOS sim-\r\nulation,
    supporting modeling of preemption in the presence of prioritized and\r\nnested
    interrupts. After introducing basic principles of abstract RTOS simula-\r\ntion,
    we present our SystemC library in detail. Thereafter, we discuss related\r\napproaches
    and close with applications in electronic automotive systems design\r\nand some
    evaluations."
author:
- first_name: Henning
  full_name: Zabel, Henning
  last_name: Zabel
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Andreas
  full_name: Gerstlauer, Andreas
  last_name: Gerstlauer
citation:
  ama: 'Zabel H, Müller W, Gerstlauer A. Accurate RTOS Modelling and Analysis with
    SystemC. In: Ecker W, Müller W, Dömer R, eds. <i>Hardware Dependent Software -
    Principles and Practice</i>. Springer Verlag; 2009:233-260. doi:<a href="https://doi.org/10.1007/978-1-4020-9436-1_9">10.1007/978-1-4020-9436-1_9</a>'
  apa: Zabel, H., Müller, W., &#38; Gerstlauer, A. (2009). Accurate RTOS Modelling
    and Analysis with SystemC. In W. Ecker, W. Müller, &#38; R. Dömer (Eds.), <i>Hardware
    Dependent Software - Principles and Practice</i> (pp. 233–260). Springer Verlag.
    <a href="https://doi.org/10.1007/978-1-4020-9436-1_9">https://doi.org/10.1007/978-1-4020-9436-1_9</a>
  bibtex: '@inbook{Zabel_Müller_Gerstlauer_2009, place={Dordrecht}, title={Accurate
    RTOS Modelling and Analysis with SystemC}, DOI={<a href="https://doi.org/10.1007/978-1-4020-9436-1_9">10.1007/978-1-4020-9436-1_9</a>},
    booktitle={Hardware Dependent Software - Principles and Practice}, publisher={Springer
    Verlag}, author={Zabel, Henning and Müller, Wolfgang and Gerstlauer, Andreas},
    editor={Ecker, Wolfgang and Müller, Wolfgang and Dömer, Rainer}, year={2009},
    pages={233–260} }'
  chicago: 'Zabel, Henning, Wolfgang Müller, and Andreas Gerstlauer. “Accurate RTOS
    Modelling and Analysis with SystemC.” In <i>Hardware Dependent Software - Principles
    and Practice</i>, edited by Wolfgang Ecker, Wolfgang Müller, and Rainer Dömer,
    233–60. Dordrecht: Springer Verlag, 2009. <a href="https://doi.org/10.1007/978-1-4020-9436-1_9">https://doi.org/10.1007/978-1-4020-9436-1_9</a>.'
  ieee: 'H. Zabel, W. Müller, and A. Gerstlauer, “Accurate RTOS Modelling and Analysis
    with SystemC,” in <i>Hardware Dependent Software - Principles and Practice</i>,
    W. Ecker, W. Müller, and R. Dömer, Eds. Dordrecht: Springer Verlag, 2009, pp.
    233–260.'
  mla: Zabel, Henning, et al. “Accurate RTOS Modelling and Analysis with SystemC.”
    <i>Hardware Dependent Software - Principles and Practice</i>, edited by Wolfgang
    Ecker et al., Springer Verlag, 2009, pp. 233–60, doi:<a href="https://doi.org/10.1007/978-1-4020-9436-1_9">10.1007/978-1-4020-9436-1_9</a>.
  short: 'H. Zabel, W. Müller, A. Gerstlauer, in: W. Ecker, W. Müller, R. Dömer (Eds.),
    Hardware Dependent Software - Principles and Practice, Springer Verlag, Dordrecht,
    2009, pp. 233–260.'
date_created: 2022-10-18T10:45:06Z
date_updated: 2022-10-18T10:55:55Z
department:
- _id: '672'
doi: 10.1007/978-1-4020-9436-1_9
editor:
- first_name: Wolfgang
  full_name: Ecker, Wolfgang
  last_name: Ecker
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  last_name: Müller
- first_name: Rainer
  full_name: Dömer, Rainer
  last_name: Dömer
keyword:
- RTOS Modelling
- RTOS Simulation
- SystemC
- Task Scheduling
- Interrupt Analysis
language:
- iso: eng
page: 233-260
place: Dordrecht
publication: Hardware Dependent Software - Principles and Practice
publication_identifier:
  isbn:
  - 978-1-4020-9435-4
publisher: Springer Verlag
status: public
title: Accurate RTOS Modelling and Analysis with SystemC
type: book_chapter
user_id: '5786'
year: '2009'
...
---
_id: '33814'
abstract:
- lang: eng
  text: "Rapidly rising system complexity has created a growing productivity gap in
    the\r\ndesign of electronic systems. One critical component is Hardware-dependent\r\nSoftware
    (HdS), the importance of which is often underestimated. In this chap-\r\nter,
    we introduce HdS and illustrate its role in the overall system design context.\r\nWe
    also provide a brief overview and define a basic HdS terminology and con-\r\nclude
    with a brief outlook over the following chapters in this book."
author:
- first_name: Wolfgang
  full_name: Ecker, Wolfgang
  last_name: Ecker
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Rainer
  full_name: Dömer, Rainer
  last_name: Dömer
citation:
  ama: 'Ecker W, Müller W, Dömer R. Hardware-dependent Software - Introduction and
    Overview. In: Ecker W, Müller W, Dömer R, eds. <i>Hardware Dependent Software
    - Principles and Practice</i>. Springer Verlag; 2009:1-14. doi:<a href="https://doi.org/10.1007/978-1-4020-9436-1_1">10.1007/978-1-4020-9436-1_1</a>'
  apa: Ecker, W., Müller, W., &#38; Dömer, R. (2009). Hardware-dependent Software
    - Introduction and Overview. In W. Ecker, W. Müller, &#38; R. Dömer (Eds.), <i>Hardware
    Dependent Software - Principles and Practice</i> (pp. 1–14). Springer Verlag.
    <a href="https://doi.org/10.1007/978-1-4020-9436-1_1">https://doi.org/10.1007/978-1-4020-9436-1_1</a>
  bibtex: '@inbook{Ecker_Müller_Dömer_2009, place={Dordrecht}, title={Hardware-dependent
    Software - Introduction and Overview}, DOI={<a href="https://doi.org/10.1007/978-1-4020-9436-1_1">10.1007/978-1-4020-9436-1_1</a>},
    booktitle={Hardware Dependent Software - Principles and Practice}, publisher={Springer
    Verlag}, author={Ecker, Wolfgang and Müller, Wolfgang and Dömer, Rainer}, editor={Ecker,
    Wolfgang and Müller, Wolfgang and Dömer, Rainer}, year={2009}, pages={1–14} }'
  chicago: 'Ecker, Wolfgang, Wolfgang Müller, and Rainer Dömer. “Hardware-Dependent
    Software - Introduction and Overview.” In <i>Hardware Dependent Software - Principles
    and Practice</i>, edited by Wolfgang Ecker, Wolfgang Müller, and Rainer Dömer,
    1–14. Dordrecht: Springer Verlag, 2009. <a href="https://doi.org/10.1007/978-1-4020-9436-1_1">https://doi.org/10.1007/978-1-4020-9436-1_1</a>.'
  ieee: 'W. Ecker, W. Müller, and R. Dömer, “Hardware-dependent Software - Introduction
    and Overview,” in <i>Hardware Dependent Software - Principles and Practice</i>,
    W. Ecker, W. Müller, and R. Dömer, Eds. Dordrecht: Springer Verlag, 2009, pp.
    1–14.'
  mla: Ecker, Wolfgang, et al. “Hardware-Dependent Software - Introduction and Overview.”
    <i>Hardware Dependent Software - Principles and Practice</i>, edited by Wolfgang
    Ecker et al., Springer Verlag, 2009, pp. 1–14, doi:<a href="https://doi.org/10.1007/978-1-4020-9436-1_1">10.1007/978-1-4020-9436-1_1</a>.
  short: 'W. Ecker, W. Müller, R. Dömer, in: W. Ecker, W. Müller, R. Dömer (Eds.),
    Hardware Dependent Software - Principles and Practice, Springer Verlag, Dordrecht,
    2009, pp. 1–14.'
date_created: 2022-10-18T10:54:39Z
date_updated: 2022-10-18T10:54:56Z
department:
- _id: '672'
doi: 10.1007/978-1-4020-9436-1_1
editor:
- first_name: Wolfgang
  full_name: Ecker, Wolfgang
  last_name: Ecker
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  last_name: Müller
- first_name: Rainer
  full_name: Dömer, Rainer
  last_name: Dömer
keyword:
- Hardware-dependent Software
- Systems Complexity
- Productivity Gap
language:
- iso: eng
page: 1-14
place: Dordrecht
publication: Hardware Dependent Software - Principles and Practice
publication_identifier:
  isbn:
  - 978-1-4020-9435-4
publisher: Springer Verlag
status: public
title: Hardware-dependent Software - Introduction and Overview
type: book_chapter
user_id: '5786'
year: '2009'
...